From 15fd96a219edeeb8edef6005041a46c58950baab Mon Sep 17 00:00:00 2001 From: James Ball Date: Sat, 21 Dec 2024 08:16:31 -0800 Subject: [PATCH] Merged in Dave's RVA23/RVB23. Adding lots of extensions. Still in progress. --- Rakefile | 6 + arch/ext/S.yaml | 6 + arch/ext/Smmpm.yaml | 21 ++ arch/ext/Smnpm.yaml | 22 ++ arch/ext/Ssnpm.yaml | 22 ++ arch/ext/Sspm.yaml | 20 ++ arch/ext/Ssstrict.yaml | 35 ++ arch/ext/Supm.yaml | 20 ++ arch/ext/Za64rs.yaml | 25 ++ arch/ext/Zama16b.yaml | 19 + arch/ext/Zcmop.yaml | 53 +++ arch/ext/Ziccamoc.yaml | 18 + arch/ext/Zihintntl.yaml | 197 +++++++++++ arch/ext/Zimop.yaml | 57 ++- arch/ext/Zvfh.yaml | 38 ++ arch/ext/Zvfhmin.yaml | 21 ++ arch/ext/Zvknc.yaml | 20 ++ arch/ext/Zvkng.yaml | 20 ++ arch/ext/Zvksc.yaml | 20 ++ arch/ext/Zvksg.yaml | 20 ++ arch/profile/RVA23S64.yaml | 29 ++ arch/profile/RVA23U64.yaml | 64 ++++ arch/profile/RVB23S64.yaml | 268 ++++++++++++++ arch/profile/RVB23U64.yaml | 288 ++++++++++++++++ arch/profile_release/RVA23.yaml | 100 +----- arch/profile_release/RVB23.yaml | 575 +------------------------------ lib/arch_obj_models/portfolio.rb | 48 ++- 27 files changed, 1342 insertions(+), 690 deletions(-) create mode 100644 arch/ext/Smmpm.yaml create mode 100644 arch/ext/Smnpm.yaml create mode 100644 arch/ext/Ssnpm.yaml create mode 100644 arch/ext/Sspm.yaml create mode 100644 arch/ext/Ssstrict.yaml create mode 100644 arch/ext/Supm.yaml create mode 100644 arch/ext/Za64rs.yaml create mode 100644 arch/ext/Zama16b.yaml create mode 100644 arch/ext/Zcmop.yaml create mode 100644 arch/ext/Ziccamoc.yaml create mode 100644 arch/ext/Zihintntl.yaml create mode 100644 arch/ext/Zvfh.yaml create mode 100644 arch/ext/Zvfhmin.yaml create mode 100644 arch/ext/Zvknc.yaml create mode 100644 arch/ext/Zvkng.yaml create mode 100644 arch/ext/Zvksc.yaml create mode 100644 arch/ext/Zvksg.yaml create mode 100644 arch/profile/RVA23S64.yaml create mode 100644 arch/profile/RVA23U64.yaml create mode 100644 arch/profile/RVB23S64.yaml create mode 100644 arch/profile/RVB23U64.yaml diff --git a/Rakefile b/Rakefile index 30b3c9b86..f9a3d858c 100644 --- a/Rakefile +++ b/Rakefile @@ -359,6 +359,10 @@ task :portfolios do Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke portfolio_start_msg("RVA22") Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke + portfolio_start_msg("RVA23") + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA23.pdf"].invoke + portfolio_start_msg("RVB23") + Rake::Task["#{$root}/gen/profile_doc/pdf/RVB23.pdf"].invoke end def portfolio_start_msg(name) @@ -381,3 +385,5 @@ task "MockProfileRelease": "#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf" task "RVI20": "#{$root}/gen/profile_doc/pdf/RVI20.pdf" task "RVA20": "#{$root}/gen/profile_doc/pdf/RVA20.pdf" task "RVA22": "#{$root}/gen/profile_doc/pdf/RVA22.pdf" +task "RVA23": "#{$root}/gen/profile_doc/pdf/RVA23.pdf" +task "RVB23": "#{$root}/gen/profile_doc/pdf/RVB23.pdf" diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index 6d350dcd8..165d40097 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -18,6 +18,12 @@ versions: requires: name: U version: "= 1.0.0" +- version: "1.13.0" + state: ratified + ratification_date: null + requires: + name: U + version: "= 1.0.0" description: | This chapter describes the RISC-V supervisor-level architecture, which contains a common core that is used with various supervisor-level diff --git a/arch/ext/Smmpm.yaml b/arch/ext/Smmpm.yaml new file mode 100644 index 000000000..c7b49f8ad --- /dev/null +++ b/arch/ext/Smmpm.yaml @@ -0,0 +1,21 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smmpm +long_name: Pointer masking for M-mode +description: | + A machine-level extension that provides pointer masking for M-mode. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null +params: + PMLEN: + description: | + The number of high-order bits of an address that are masked by the + pointer masking facility. + schema: + type: integer + also_defined_in: [Ssnpm, Smmpm] diff --git a/arch/ext/Smnpm.yaml b/arch/ext/Smnpm.yaml new file mode 100644 index 000000000..fa47b05a1 --- /dev/null +++ b/arch/ext/Smnpm.yaml @@ -0,0 +1,22 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smnpm +long_name: Pointer masking for next privilege level less than M-mode +description: | + A machine-level extension that provides pointer masking for the next lower privilege mode + (S/HS if S-mode is implemented, or U-mode otherwise). +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null +params: + PMLEN: + description: | + The number of high-order bits of an address that are masked by the + pointer masking facility. + schema: + type: integer + also_defined_in: [Ssnpm, Smmpm] diff --git a/arch/ext/Ssnpm.yaml b/arch/ext/Ssnpm.yaml new file mode 100644 index 000000000..652e87912 --- /dev/null +++ b/arch/ext/Ssnpm.yaml @@ -0,0 +1,22 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Ssnpm +long_name: Pointer masking for next privilege level less than S-mode +description: | + A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode), + and for VS-modes and VU-modes if the H extension is present. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null +params: + PMLEN: + description: | + The number of high-order bits of an address that are masked by the + pointer masking facility. + schema: + type: integer + also_defined_in: [Smnpm, Smmpm] diff --git a/arch/ext/Sspm.yaml b/arch/ext/Sspm.yaml new file mode 100644 index 000000000..01e0835cf --- /dev/null +++ b/arch/ext/Sspm.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Sspm +long_name: Pointer masking available in supervisor mode +description: | + Indicates that there is pointer-masking support available in supervisor mode, + with some facility provided in the application execution environment to control pointer masking. + + This extension describes an execution environment but has no bearing on hardware implementations. + It is intended to be used in profile specifications where a Supervisor profile + can only reference Supervisor level pointer masking functionality, + and not the associated CSR controls that exist at a higher privilege level (i.e., in the execution environment). + +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Ssstrict.yaml b/arch/ext/Ssstrict.yaml new file mode 100644 index 000000000..7e1f162bc --- /dev/null +++ b/arch/ext/Ssstrict.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Ssstrict +long_name: Unimplemented reserved encodings trap and no no-conforming extensions +description: | + No non-conforming extensions are present. Attempts to + execute unimplemented opcodes or access unimplemented CSRs in the + standard or reserved encoding spaces raises an illegal instruction + exception that results in a contained trap to the supervisor-mode + trap handler. + + [NOTE] Ssstrict does not prescribe behavior for the custom encoding + spaces or CSRs. + + [NOTE] Ssstrict definition applies to the execution environment + claiming to be RVA23/RVB23-compatible. + If the hypervisor extension is present, that execution environment will take a contained trap to + supervisor-mode (however that trap is implemented, including, but not + limited to, emulation/delegation in the outer execution + environment). Ssstrict (and all the other RVA23/RVB23 mandates and options) + do not apply to any guest VMs run by a hypervisor. An RVA23/RVB23 hypervisor + can provide guest VMs that are also RVA23/RVB23-compatible but with an + expanded set of emulated standard instructions. An RVA23/RVB23 hypervisor + can also choose to implement guest VMs that are not RVA23/RVB23 compatible + (e.g., lacking H, or only RVA20). + + [NOTE] Ssstrict is a new RVA23/RVB23 profile-defined extension that restricts the + behavior of reserved encoding spaces. The extension will be added to + the supervisor chapter of the privileged architecture. +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Supm.yaml b/arch/ext/Supm.yaml new file mode 100644 index 000000000..428195abc --- /dev/null +++ b/arch/ext/Supm.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Supm +long_name: Pointer masking available in user mode +description: | + Indicates that there is pointer-masking support available in user mode, + with some facility provided in the application execution environment to control pointer masking. + + This extension describes an execution environment but has no bearing on hardware implementations. + It is intended to be used in profile specifications where a User profile + can only reference User level pointer masking functionality, + and not the associated CSR controls that exist at a higher privilege level (i.e., in the execution environment). + +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Za64rs.yaml b/arch/ext/Za64rs.yaml new file mode 100644 index 000000000..ea833511a --- /dev/null +++ b/arch/ext/Za64rs.yaml @@ -0,0 +1,25 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Za64rs +long_name: Reservation set requirement for RVA profiles +description: | + Reservation sets must be contiguous, naturally aligned, and at most 64 bytes in size. + + [NOTE] + This extension was ratified as part of the RVA22 profile. + + [NOTE] + The minimum reservation set size is effectively determined by the size of atomic accesses in + the A extension. +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + param_constraints: + LRSC_RESERVATION_STRATEGY: + schema: + oneOf: + - const: reserve exactly enough to cover the access + - const: reserve naturally-aligned 64-byte region diff --git a/arch/ext/Zama16b.yaml b/arch/ext/Zama16b.yaml new file mode 100644 index 000000000..b401bda13 --- /dev/null +++ b/arch/ext/Zama16b.yaml @@ -0,0 +1,19 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zama16b +long_name: Misaligned load/store/AMO within aligned 16-byte address are atomic +description: | + Misaligned loads, stores, and AMOs to main memory regions that do not cross a + naturally-aligned 16-byte boundary are atomic. + + [NOTE] Zama16b is a new RVA23 profile-defined extension that represents + the presence of the new Misaligned Atomicity Granule feature added in + Sm1p13. The extension will be added to the PMA section of the + privileged architecture manual. + +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zcmop.yaml b/arch/ext/Zcmop.yaml new file mode 100644 index 000000000..70e8fbfa0 --- /dev/null +++ b/arch/ext/Zcmop.yaml @@ -0,0 +1,53 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zcmop +long_name: 16-bit May-be Operations +description: | + The "Zcmop" extension, which defines eight 16-bit MOP + instructions named C.MOP.__n__, where __n__ is an odd integer between 1 and + 15, inclusive. C.MOP.__n__ is encoded in the reserved encoding space + corresponding to C.LUI x__n__, 0, as shown in <>. + Unlike the MOPs defined in the Zimop extension, the C.MOP.__n__ instructions + are defined to _not_ write any register. + Their encoding allows future extensions to define them to read register + `x[__n__]`. + + The Zcmop extension depends upon the Zca extension. + + NOTE: Very few suitable 16-bit encoding spaces exist. This space was chosen + because it already has unusual behavior with respect to the `rd`/`rs1` + field--it encodes `c.addi16sp` when the field contains `x2`--and is + therefore of lower value for most purposes. + + [[tab:c-mop]] + .C.MOP.__n__ instruction encoding. + + |=== + |Mnemonic | Encoding | Redefinable to read register + + |C.MOP.1 | `0110000010000001` | `x1` + |C.MOP.3 | `0110000110000001` | `x3` + |C.MOP.5 | `0110001010000001` | `x5` + |C.MOP.7 | `0110001110000001` | `x7` + |C.MOP.9 | `0110010010000001` | `x9` + |C.MOP.11 | `0110010110000001` | `x11` + |C.MOP.13 | `0110011010000001` | `x13` + |C.MOP.15 | `0110011110000001` | `x15` + |=== + + NOTE: The recommended assembly syntax for C.MOP.__n__ is simply the nullary + C.MOP.__n__. The possibly accessed register is implicitly `x__n__`. + + NOTE: The expectation is that each Zcmop instruction is equivalent to some + Zimop instruction, but the choice of expansion (if any) is left to the + extension that redefines the MOP. + Note, a Zcmop instruction that does not write a value can expand into a write + to `x0`. +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + requires: C diff --git a/arch/ext/Ziccamoc.yaml b/arch/ext/Ziccamoc.yaml new file mode 100644 index 000000000..684c150b5 --- /dev/null +++ b/arch/ext/Ziccamoc.yaml @@ -0,0 +1,18 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Ziccamoc +long_name: Cacheable and coherent PMAs provide `AMOCASQ` level PMA support +description: | + Main memory regions with both the cacheability and coherence PMAs + must provide `AMOCASQ` level PMA support. + + [NOTE] Ziccamoc is a new RVA23 profile-defined extension that ensures + Compare and Swap instructions are properly supported in main memory + regions. The extension will be added to the PMA section of the + privileged architecture manual. +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zihintntl.yaml b/arch/ext/Zihintntl.yaml new file mode 100644 index 000000000..8df21228f --- /dev/null +++ b/arch/ext/Zihintntl.yaml @@ -0,0 +1,197 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zihintntl +long_name: NTL (Non-Temporal Locality) Hint Instructions +description: | + The NTL instructions are HINTs that indicate that the explicit memory + accesses of the immediately subsequent instruction (henceforth "target + instruction") exhibit poor temporal locality of reference. The NTL + instructions do not change architectural state, nor do they alter the + architecturally visible effects of the target instruction. Four variants + are provided: + + The NTL.P1 instruction indicates that the target instruction does not + exhibit temporal locality within the capacity of the innermost level of + private cache in the memory hierarchy. NTL.P1 is encoded as + ADD _x0, x0, x2_. + + The NTL.PALL instruction indicates that the target instruction does not + exhibit temporal locality within the capacity of any level of private + cache in the memory hierarchy. NTL.PALL is encoded as ADD _x0, x0, x3_. + + The NTL.S1 instruction indicates that the target instruction does not + exhibit temporal locality within the capacity of the innermost level of + shared cache in the memory hierarchy. NTL.S1 is encoded as + ADD _x0, x0, x4_. + + The NTL.ALL instruction indicates that the target instruction does not + exhibit temporal locality within the capacity of any level of cache in + the memory hierarchy. NTL.ALL is encoded as ADD _x0, x0, x5_. + + [NOTE] + ==== + The NTL instructions can be used to avoid cache pollution when streaming + data or traversing large data structures, or to reduce latency in + producer-consumer interactions. + + A microarchitecture might use the NTL instructions to inform the cache + replacement policy, or to decide which cache to allocate into, or to + avoid cache allocation altogether. For example, NTL.P1 might indicate + that an implementation should not allocate a line in a private L1 cache, + but should allocate in L2 (whether private or shared). In another + implementation, NTL.P1 might allocate the line in L1, but in the + least-recently used state. + + NTL.ALL will typically inform implementations not to allocate anywhere + in the cache hierarchy. Programmers should use NTL.ALL for accesses that + have no exploitable temporal locality. + + Like any HINTs, these instructions may be freely ignored. Hence, + although they are described in terms of cache-based memory hierarchies, + they do not mandate the provision of caches. + + Some implementations might respect these HINTs for some memory accesses + but not others: e.g., implementations that implement LR/SC by acquiring + a cache line in the exclusive state in L1 might ignore NTL instructions + on LR and SC, but might respect NTL instructions for AMOs and regular + loads and stores. + ==== + + <> lists several software use cases and the recommended NTL variant that _portable_ software—i.e., software not tuned for any specific implementation's memory hierarchy—should use in each case. + + [[ntl-portable]] + .Recommended NTL variant for portable software to employ in various scenarios. + [%autowidth,float="center",align="center",cols="<,<",options="header",] + |=== + |Scenario |Recommended NTL variant + |Access to a working set between and in size |NTL.P1 + |Access to a working set between and in size |NTL.PALL + |Access to a working set greater than in size |NTL.S1 + |Access with no exploitable temporal locality (e.g., streaming) |NTL.ALL + |Access to a contended synchronization variable |NTL.PALL + |=== + + [NOTE] + ==== + The working-set sizes listed in <> are not meant to + constrain implementers' cache-sizing decisions. + Cache sizes will obviously vary between implementations, and so software + writers should only take these working-set sizes as rough guidelines. + ==== + + <> lists several sample memory hierarchies and + recommends how each NTL variant maps onto each cache level. The table + also recommends which NTL variant that implementation-tuned software + should use to avoid allocating in a particular cache level. For example, + for a system with a private L1 and a shared L2, it is recommended that + NTL.P1 and NTL.PALL indicate that temporal locality cannot be exploited + by the L1, and that NTL.S1 and NTL.ALL indicate that temporal locality + cannot be exploited by the L2. Furthermore, software tuned for such a + system should use NTL.P1 to indicate a lack of temporal locality + exploitable by the L1, or should use NTL.ALL indicate a lack of temporal + locality exploitable by the L2. + + If the C extension is provided, compressed variants of these HINTs are + also provided: C.NTL.P1 is encoded as C.ADD _x0, x2_; C.NTL.PALL is + encoded as C.ADD _x0, x3_; C.NTL.S1 is encoded as C.ADD _x0, x4_; and + C.NTL.ALL is encoded as C.ADD _x0, x5_. + + The NTL instructions affect all memory-access instructions except the + cache-management instructions in the Zicbom extension. + + [NOTE] + ==== + As of this writing, there are no other exceptions to this rule, and so + the NTL instructions affect all memory-access instructions defined in + the base ISAs and the A, F, D, Q, C, and V standard extensions, as well + as those defined within the hypervisor extension in Volume II. + + The NTL instructions can affect cache-management operations other than + those in the Zicbom extension. For example, NTL.PALL followed by + CBO.ZERO might indicate that the line should be allocated in L3 and + zeroed, but not allocated in L1 or L2. + ==== + + <<< + + [[ntl]] + [%autowidth,float="center",align="center",cols="<,^,^,^,^,^,^,^,^",options="header"] + .Mapping of NTL variants to various memory hierarchies. + |=== + | Memory hierarchy 4+| Recommended mapping of NTL + + variant to actual cache level 4+| Recommended NTL variant for + + explicit cache management + | + |P1 |PALL |S1 |ALL + |L1 |L2 |L3 |L4/L5 + 9+^| Common Scenarios + | No caches 4+|--- 4+|none + |Private L1 only |L1 |L1 |L1 |L1| ALL |--- |--- |--- + |Private L1; shared L2 |L1 |L1 |L2 |L2 |P1|ALL|---|--- + |Private L1; shared L2/L3 |L1 | L1 | L2 | L3 |P1 |S1 |ALL |--- + |Private L1/L2 |L1 |L2 |L2 |L2 | P1 |ALL |--- |--- + |Private L1/L2; shared L3 |L1 | L2 | L3 | L3 | P1 | PALL| ALL |--- + |Private L1/L2; shared L3/L4 | L1 | L2| L3 | L4 | P1 | PALL | S1 | ALL + 9+^| Uncommon Scenarios + |Private L1/L2/L3; shared L4 | L1 | L3 |L4 |L4 |P1 |P1 |PALL |ALL + |Private L1; shared L2/L3/L4 |L1 | L1 |L2 |L4 |P1 |S1 |ALL |ALL + |Private L1/L2; shared L3/L4/L5 |L1 | L2 | L3 | L5 |P1 | PALL |S1 |ALL + |Private L1/L2/L3; shared L4/L5 |L1 |L3 |L4 |L5 |P1 |P1 |PALL |ALL + |=== + + When an NTL instruction is applied to a prefetch hint in the Zicbop + extension, it indicates that a cache line should be prefetched into a + cache that is _outer_ from the level specified by the NTL. + + [NOTE] + ==== + For example, in a system with a private L1 and shared L2, NTL.P1 + followed by PREFETCH.R might prefetch into L2 with read intent. + + To prefetch into the innermost level of cache, do not prefix the + prefetch instruction with an NTL instruction. + + In some systems, NTL.ALL followed by a prefetch instruction might + prefetch into a cache or prefetch buffer internal to a memory + controller. + ==== + + Software is discouraged from following an NTL instruction with an + instruction that does not explicitly access memory. Nonadherence to this + recommendation might reduce performance but otherwise has no + architecturally visible effect. + + In the event that a trap is taken on the target instruction, + implementations are discouraged from applying the NTL to the first + instruction in the trap handler. Instead, implementations are + recommended to ignore the HINT in this case. + + [NOTE] + ==== + If an interrupt occurs between the execution of an NTL instruction and + its target instruction, execution will normally resume at the target + instruction. That the NTL instruction is not reexecuted does not change + the semantics of the program. + + Some implementations might prefer not to process the NTL instruction + until the target instruction is seen (e.g., so that the NTL can be fused + with the memory access it modifies). Such implementations might + preferentially take the interrupt before the NTL, rather than between + the NTL and the memory access. + ==== + ''' + [NOTE] + ==== + Since the NTL instructions are encoded as ADDs, they can be used within + LR/SC loops without voiding the forward-progress guarantee. But, since + using other loads and stores within an LR/SC loop _does_ void the + forward-progress guarantee, the only reason to use an NTL within such a + loop is to modify the LR or the SC. + ==== +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zimop.yaml b/arch/ext/Zimop.yaml index f67973291..7a6a57180 100644 --- a/arch/ext/Zimop.yaml +++ b/arch/ext/Zimop.yaml @@ -5,10 +5,61 @@ kind: extension name: Zimop long_name: May-be Operations description: | - Instructions that may be operations (MOPs). - MOPs are initially defined to simply write zero to x[rd], but are designed to be redefined by - later extensions to perform some other action. + The "Zimop" extension introduces the concept of + instructions that _may be operations_ (MOPs). MOPs are initially defined to + simply write zero to `x[rd]`, but are designed to be redefined by later + extensions to perform some other action. The Zimop extension defines an encoding space for 40 MOPs. + + [NOTE] + ==== + It is sometimes desirable to define instruction-set extensions whose + instructions, rather than raising illegal-instruction exceptions when the extension is + not implemented, take no useful action (beyond writing `x[rd]`). + For example, programs with control-flow integrity checks can + execute correctly on implementations without the corresponding extension, + provided the checks are simply ignored. Implementing these checks as MOPs + allows the same programs to run on implementations with or without the + corresponding extension. + + Although similar in some respects to HINTs, MOPs cannot be encoded as HINTs, + because unlike HINTs, MOPs are allowed to alter architectural state. + + Because MOPs may be redefined by later extensions, standard software should + not execute a MOP unless it is deliberately targeting an extension that has + redefined that MOP. + ==== + + The Zimop extension defines 32 MOP instructions named MOP.R.__n__, where + __n__ is an integer between 0 and 31, inclusive. + Unless redefined by another extension, these instructions simply write 0 to + `x[rd]`. Their encoding allows future extensions to define them to read `x[rs1]`, + as well as write `x[rd]`. + + The Zimop extension additionally defines 8 MOP instructions named + MOP.RR.__n__, where __n__ is an integer between 0 and 7, inclusive. + Unless redefined by another extension, these instructions simply + write 0 to `x[rd]`. Their encoding allows future extensions to define them to + read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`. + + NOTE: The recommended assembly syntax for MOP.R.__n__ is MOP.R.__n__ rd, rs1, + with any `x`-register specifier being valid for either argument. Similarly for + MOP.RR.__n__, the recommended syntax is MOP.RR.__n__ rd, rs1, rs2. + The extension that redefines a MOP may define an alternate assembly mnemonic. + + NOTE: These MOPs are encoded in the SYSTEM major opcode in part because it is + expected their behavior will be modulated by privileged CSR state. + + NOTE: These MOPs are defined to write zero to `x[rd]`, rather than performing + no operation, to simplify instruction decoding and to allow testing the + presence of features by branching on the zeroness of the result. + + The MOPs defined in the Zimop extension do not carry a syntactic dependency + from `x[rs1]` or `x[rs2]` to `x[rd]`, though an extension that redefines the + MOP may impose such a requirement. + + NOTE: Not carrying a syntactic dependency relieves straightforward + implementations of reading `x[rs1]` and `x[rs2]`. type: unprivileged versions: - version: "1.0.0" diff --git a/arch/ext/Zvfh.yaml b/arch/ext/Zvfh.yaml new file mode 100644 index 000000000..1870543c1 --- /dev/null +++ b/arch/ext/Zvfh.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvfh +long_name: Vector Extension for Half-Precision Floating-Point +description: | + This extension provides support for vectors of IEEE 754-2008 + binary16 values. + When the Zvfh extension is implemented, all instructions in Sections + <>, <>, + <>, <>, + <>, and <> + become defined when SEW=16. + The EEW=16 floating-point operands of these instructions use the binary16 + format. + + Additionally, conversions between 8-bit integers and binary16 values are + provided. The floating-point-to-integer narrowing conversions + (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point + widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8. + + The Zvfh extension depends on the Zve32f and Zfhmin extensions. + + [NOTE] Requiring basic scalar half-precision support makes Zvfh's + vector-scalar instructions substantially more useful. + We considered requiring more complete scalar half-precision support, but we + reasoned that, for many half-precision vector workloads, performing the scalar + computation in single-precision will suffice. +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + requires: + allOf: + - Zve32f + - Zfhmin diff --git a/arch/ext/Zvfhmin.yaml b/arch/ext/Zvfhmin.yaml new file mode 100644 index 000000000..36985e525 --- /dev/null +++ b/arch/ext/Zvfhmin.yaml @@ -0,0 +1,21 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvfhmin +long_name: Vector Extension for Minimal Half-Precision Floating-Point +description: | + This extension provides minimal support for vectors of IEEE 754-2008 + binary16 values, adding conversions to and from binary32. + When the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and + `vfncvt.f.f.w` instructions become defined when SEW=16. + The EEW=16 floating-point operands of these instructions use the binary16 + format. + + This extension depends on the Zve32f extension. +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + requires: Zve32f diff --git a/arch/ext/Zvknc.yaml b/arch/ext/Zvknc.yaml new file mode 100644 index 000000000..2e9ce11dc --- /dev/null +++ b/arch/ext/Zvknc.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvknc +long_name: NIST Algorithm Suite with carryless multiply +description: | + This extension is shorthand for the following set of other extensions: + + * `Zvkn` + * `Zvbc` + +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + implies: + - [Zvkn, "1.0.0"] + - [Zvbc, "1.0.0"] diff --git a/arch/ext/Zvkng.yaml b/arch/ext/Zvkng.yaml new file mode 100644 index 000000000..5cae63706 --- /dev/null +++ b/arch/ext/Zvkng.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvkng +long_name: NIST Algorithm Suite with GCM +description: | + This extension is shorthand for the following set of other extensions: + + * `Zvkn` + * `Zvkg` + +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + implies: + - [Zvkn, "1.0.0"] + - [Zvkg, "1.0.0"] diff --git a/arch/ext/Zvksc.yaml b/arch/ext/Zvksc.yaml new file mode 100644 index 000000000..2e272745a --- /dev/null +++ b/arch/ext/Zvksc.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvksc +long_name: ShangMi Algorithm Suite with carryless multiplication +description: | + This extension is shorthand for the following set of other extensions: + + * `Zvks` + * `Zvbc` + +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + implies: + - [Zvks, "1.0.0"] + - [Zvbc, "1.0.0"] diff --git a/arch/ext/Zvksg.yaml b/arch/ext/Zvksg.yaml new file mode 100644 index 000000000..4577e0957 --- /dev/null +++ b/arch/ext/Zvksg.yaml @@ -0,0 +1,20 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zvksg +long_name: ShangMi Algorithm Suite with GCM +description: | + This extension is shorthand for the following set of other extensions: + + * `Zvks` + * `Zvkg` + +type: unprivileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null + implies: + - [Zvks, "1.0.0"] + - [Zvkg, "1.0.0"] diff --git a/arch/profile/RVA23S64.yaml b/arch/profile/RVA23S64.yaml new file mode 100644 index 000000000..2484cafa9 --- /dev/null +++ b/arch/profile/RVA23S64.yaml @@ -0,0 +1,29 @@ +$schema: profile_schema.json# +kind: profile +name: RVA23S64 +marketing_name: RVA23S64 +mode: S +base: 64 +release: { $ref: profile_release/RVA23.yaml# } +introduction: | + The RVA23S64 profile specifies the ISA features available to supervisor-mode + execution environments in 64-bit applications processors. + An ECALL in user mode causes a contained trap to supervisor mode. + An ECALL in supervisor mode causes a requested trap to the execution environment. +extensions: + ######################################################################### + # imported from RVB23U64 + ######################################################################### + $inherits: "profile/RVB23S64.yaml#/extensions" + + ######################################################################### + # MANDATORY extensions in RVA23S64 (that were optional in RVB23S64) + ######################################################################### + + Ssnpm: + presence: mandatory + # Pointer masking, with *senvcfg*.PME supporting, at minimum + + Sha: + presence: mandatory + # collection of Hypervisor extensions diff --git a/arch/profile/RVA23U64.yaml b/arch/profile/RVA23U64.yaml new file mode 100644 index 000000000..00c9206bc --- /dev/null +++ b/arch/profile/RVA23U64.yaml @@ -0,0 +1,64 @@ +$schema: profile_schema.json# +kind: profile +name: RVA23U64 +marketing_name: RVA23U64 +mode: Unpriv +base: 64 +release: { $ref: profile_release/RVA23.yaml# } +introduction: | + The RVA23U64 profile specifies the ISA features available to user-mode + execution environments in 64-bit applications processors. This is the + most important profile within application processors in + terms of the amount of software that targets this profile. +extensions: + ######################################################################### + # imported from RVB23U64 + ######################################################################### + $inherits: "profile/RVB23U64.yaml#/extensions" + $remove: + - Zvkg + - Zvknc + - Zvksc + - Zkn + - Zks + + ######################################################################### + # MANDATORY extensions in RVA23U64 (that were optional in RVB23U64) + ######################################################################### + + Zfhmin: + presence: mandatory + + V: + presence: mandatory + + Zvfhmin: + presence: mandatory + + Zvbb: + presence: mandatory + + Zvkt: + presence: mandatory + + Supm: + presence: mandatory + + #-------------------------------------------- + # Zvbc is an expansion option in RVB23U64 + # (but is not intended to be made mandatory in future RVB Profiles) + # + # It is listed in RVA23U64 as a *development* option, + # as it *is* intended to become mandatory in future RVA Profiles. + #-------------------------------------------- + Zvbc: + presence: + optional: development + + ######################################################################### + # TRANSITORY EXPANSION extensions in RVA23U64 + ######################################################################### + + #-------------------------------------------- + # (there are no Transitory expansion options in RVA23U64) + #-------------------------------------------- diff --git a/arch/profile/RVB23S64.yaml b/arch/profile/RVB23S64.yaml new file mode 100644 index 000000000..036c0e1db --- /dev/null +++ b/arch/profile/RVB23S64.yaml @@ -0,0 +1,268 @@ +$schema: profile_schema.json# +kind: profile +name: RVB23S64 +marketing_name: RVB23S64 +mode: S +base: 64 +release: { $ref: profile_release/RVB23.yaml# } +introduction: | + The RVB23S64 profile specifies the ISA features available to supervisor-mode + execution environments in 64-bit applications processors. + An ECALL in user mode causes a contained trap to supervisor mode. + An ECALL in supervisor mode causes a requested trap to the execution environment. +extensions: + ######################################################################### + # imported from RVA22S64 + ######################################################################### + $inherits: "profile/RVA22S64.yaml#/extensions" + + ######################################################################### + # MANDATORY extensions in RVB23 (and RVA23) + ######################################################################### + Zifencei: + presence: mandatory + version: "~>1.0" + note: | + Instruction-Fetch fence instruction. + + Zifencei is mandated as it is the only standard way to support + instruction-cache coherence in RVB23 application processors. + A new instruction-cache coherence mechanism is under development + (tentatively named Zjid), which might be added as an option in the future. + + S: + presence: mandatory + version: "~>1.13" + note: | + Supervisor version 1.13 + + Svnapot: + presence: mandatory + version: "~>1.0" + note: | + NAPOT translation contiguity. + Svnapot is very low cost to provide, so is made mandatory even in RVB. + + Svbare: + presence: mandatory + version: "~>1.0" + note: | + The *satp* mode Bare must be supported + + Sv39: + presence: mandatory + version: "~>1.0" + note: | + Page-Based 39-bit Virtual-Memory System + + Svade: + presence: mandatory + version: "~>1.0" + note: | + A page-fault exception is raised when a page is accessed when A bit = 0 , + or when a page is written when D bit = 0 + + Ssccptr: + presence: mandatory + version: "~>1.0" + note: | + Main memory regions with both the cacheability and coherence PMAs must + support hardware page-table reads + + Sstvecd: + presence: mandatory + version: "~>1.0" + note: | + *stvec*.MODE must be capable of holding the value 0 (Direct). + When *stvec*.MODE=Direct, + *stvec*.BASE must be capable of holding any valid four-byte-aligned address + + Sstvala: + presence: mandatory + version: "~>1.0" + note: | + *stval* must be written with the faulting virtual address for load, store, + and instruction page-fault, access-fault, and misaligned exceptions, + and for breakpoint exceptions other than those caused by execution of + the EBREAK or C.EBREAK instructions. + For virtual-instruction and illegal instruction exceptions, + *stval* must be written with the faulting instruction . + + Sscounterenw: + presence: mandatory + version: "~>1.0" + note: | + For any *hpmcounter* that is not read-only zero, + the corresponding bit in *scounteren* must be writable. + + Svpbmt: + presence: mandatory + version: "~>1.0" + note: | + Page-based memory types + + Svinval: + presence: mandatory + version: "~>1.0" + note: | + Fine-grained address-translation cache invalidation + + Sstc: + presence: mandatory + version: "~>1.0" + note: | + Supervisor-mode timer interrupts. + + NOTE: Sstc was not made mandatory in RVB23S64 as it is a more + disruptive change affecting system-level architecture, and will take + longer for implementations to adopt. It is expected to be made + mandatory in the next profile release. + + Sscofpmf: + presence: mandatory + version: "~>1.0" + note: | + Count overflow and mode-based filtering. + Platforms may choose to mandate the presence of Sscofpmf. + + Ssu64xl: + presence: mandatory + version: "~>1.0" + note: | + *sstatus*.UXL must be capable of holding the value 2 + (that is, UXLEN=64 must be supported) + + ######################################################################### + # OPTIONAL LOCALIZED extensions in RVB23S64 + ######################################################################### + + # there are no Optional Localized extensions in RVB23S64 + + ######################################################################### + # OPTIONAL DEVELOPMENT extensions in RVB23S64 + ######################################################################### + + # there are no Optional Development extensions in RVB23S64 + + ######################################################################### + # OPTIONAL EXPANSION extensions in RVB23S64 (mandatory in RVA23S64) + ######################################################################### + + Ssnpm: + presence: + optional: expansion + version: "~>1.0" + note: | + Pointer masking, with *senvcfg*.PME supporting, at minimum, + settings PMLEN=0 and PMLEN=7 + + Sha: + presence: + optional: expansion + version: "~>1.0" + note: | + The set of augmented hypervisor extensions: H, Ssstateen, + Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa + + __NEED_AN_EXTENSION_NAME_HERE__: + presence: + optional: expansion + version: "~>1.0" + when: + allOf: + - implemented: H + - implemented: Ssnpm + note: | + If the hypervisor extension is implemented + and pointer masking (Ssnpm) is supported + then *henvcfg*.PME must support at minimum, settings PMLEN=0 and PMLEN=7 + + ######################################################################### + # OPTIONAL EXPANSION extensions in both RVB23S64 and RVA23S64 + ######################################################################### + + Sv48: + presence: + optional: expansion + version: "~>1.0" + note: | + Page-based 48-bit virtual-memory system + + Sv57: + presence: + optional: expansion + version: "~>1.0" + note: | + Page-based 57-bit virtual-memory system + + Svadu: + presence: + optional: expansion + version: "~>1.0" + note: | + Hardware A/D bit updates + + Zkr: + presence: + optional: expansion + version: "~>1.0" + note: | + Entropy CSR + + NOTE: Technically, Zk is also a privileged-mode option, capturing that + Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less + descriptive than specifying the individual extensions explicitly. + + Sdtrig: + presence: + optional: expansion + version: "~>1.0" + note: | + Debug triggers + + Ssstrict: + presence: + optional: expansion + version: "~>1.0" + note: | + No non-conforming extensions are present. + Attempts to execute unimplemented opcodes or access unimplemented CSRs in the + standard or reserved encoding spaces raises an illegal instruction exception + that results in a contained trap to the supervisor-mode trap handler + + NOTE: Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs. + + NOTE: Ssstrict definition applies to the execution environment claiming to be + RVB23-compatible, which must have the hypervisor extension. + That execution environment will take a contained trap to supervisor-mode + (however that trap is implemented, including, but not limited to, + emulation/delegation in the outer execution environment). + Ssstrict (and all the other RVB23 mandates and options) do not apply to + any guest VMs run by a hypervisor. + An RVB23 hypervisor can provide guest VMs that are also RVB23-compatible + but with an expanded set of emulated standard instructions. + An RVB23 hypervisor can also choose to implement guest VMs that are not + RVB23 compatible (for example, only RVA20 or only RVA22) + # that last parenthesized phrase for the RVA23 Profile would change to: + # (for example, lacking H, or only RVA20) + + Svvptc: + presence: + optional: expansion + version: "~>1.0" + note: | + Transitions from invalid to valid PTEs will be visible in bounded time + without an explicit memory-management fence. + + Sspm: + presence: + optional: expansion + version: "~>1.0" + note: | + Supervisor-mode pointer masking, with the supervisor execution environment + providing a means to select PMLEN=0 and PMLEN=7 (at minimum). + +recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. diff --git a/arch/profile/RVB23U64.yaml b/arch/profile/RVB23U64.yaml new file mode 100644 index 000000000..b133ce78a --- /dev/null +++ b/arch/profile/RVB23U64.yaml @@ -0,0 +1,288 @@ +$schema: profile_schema.json# +kind: profile +name: RVB23U64 +marketing_name: RVB23U64 +mode: Unpriv +base: 64 +release: { $ref: profile_release/RVB23.yaml# } +introduction: | + The RVB23U64 profile specifies the ISA features available to user-mode + execution environments in 64-bit applications processors. This is the + most important profile within application processors in + terms of the amount of software that targets this profile. +extensions: + ######################################################################### + # imported from RVA22U64 + ######################################################################### + $inherits: "profile/RVA22U64.yaml#/extensions" + $remove: Za128rs + + ######################################################################### + # MANDATORY extensions in RVB23 (and RVA23) + ######################################################################### + Zihintntl: + presence: mandatory + version: "~>1.0" + note: | + Non-temporal memory-access locality hints + Zicond: + presence: mandatory + version: "~>1.0" + note: | + Integer conditional operations + Zimop: + presence: mandatory + version: "~>1.0" + note: | + May-be operations + Zcmop: + presence: mandatory + version: "~>1.0" + note: | + Commpressed (16-bit) may-be operations + Zcb: + presence: mandatory + version: "~>1.0" + note: | + Additional compressed (16-bit) instructions + Zfa: + presence: mandatory + version: "~>1.0" + note: | + Additional floating-point instructions + Zawrs: + presence: mandatory + version: "~>1.0" + note: | + Wait-on-reservation-set (WRS) instructions + Za64rs: + presence: mandatory + version: "~>1.0" + note: | + Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes + + ######################################################################### + # OPTIONAL LOCALIZED extensions + ######################################################################### + + #--------------------------------- + # In RVB23 (and RVA23) + #--------------------------------- + Zvkng: + presence: + optional: localized + version: "~>1.0" + note: | + Vector crypto NIST Algorithms with GCM + Zvksg: + presence: + optional: localized + version: "~>1.0" + note: | + Vector crypto Shang-Mi Algorithms with GCM + + #--------------------------------- + # In RVB23 (but not in RVA23) + #--------------------------------- + Zvkg: + presence: + optional: localized + version: "~>1.0" + note: | + Vector GCM/GMAC instructions + + Zvknc: + presence: + optional: localized + version: "~>1.0" + note: | + Vector crypto NIST algorithms with carryless multiply. + To reduce implementation cost, RVB profiles allow this carryless multiply option to + implement GCM efficiently, with GHASH available as a separate option. + # RVA23 does not include Zvknc because it mandates the higher-performing + # but more expensive GHASH options when adding vector crypto. + Zvksc: + presence: + optional: localized + version: "~>1.0" + note: | + Vector crypto Shang-Mi algorithms with carryless multiply. + To reduce implementation cost, RVB profiles allow this carryless multiply option to + implement GCM efficiently, with GHASH available as a separate option. + # RVA23 does not include Zvksc because it mandates the higher-performing + # but more expensive GHASH options when adding vector crypto. + + Zkn: + presence: + optional: localized + version: "~>1.0" + note: | + Scalar crypto NIST algorithms + Zks: + presence: + optional: localized + version: "~>1.0" + note: | + Scalar crypto Shang-Mi algorithms + # RVA23 profiles drop support for the above scalar crypto as an option, as the vector + # extension is now mandatory in RVA23. + # RVB23 profiles do support scalar crypto as an option, as the vector extension is optional in RVB23. + + ######################################################################### + # OPTIONAL DEVELOPMENT extensions in RVB23 + ######################################################################### + # The following are new development options, intended to become mandatory in a later RVB profile: + Zabha: + presence: + optional: development + version: "~>1.0" + note: | + Byte and halfword atomic memory operations + Zacas: + presence: + optional: development + version: "~>1.0" + note: | + Compare-and-Swap instructions + Ziccamoc: + presence: + optional: development + version: "~>1.0" + note: | + Main memory regions with both the cacheability and coherence PMAs + must provide AMOCASQ-level PMA support + Zama16b: + presence: + optional: development + version: "~>1.0" + note: | + Misaligned loads, stores, and AMOs to main memory regions that do not cross + Daaaa naturally aligned 16-byte boundary are atomic + + ######################################################################### + # OPTIONAL EXPANSION extensions in RVB23 + ######################################################################### + + #--------------------------------- + # Optional in RVB23U64 (but Mandatory in RVA23U64) + #--------------------------------- + Zfhmin: + presence: + optional: expansion + version: "~> 1.0" + note: | + Zfhmin is a small extension that adds support to load/store and convert + IEEE 754 half-precision numbers to and from the IEEE 754 single-precision + format. The hardware cost for this extension is low, and mandating the + extension avoids adding an option to the profile. + V: + presence: + optional: expansion + version: "~> 1.0" + note: | + The Vector extension + # Note: it is unclear if other Zve* extensions should also be supported in RVB + Zvfhmin: + presence: + optional: expansion + version: "~>1.0" + note: | + Vector minimal half-precision floating-point + Zvbb: + presence: + optional: expansion + version: "~>1.0" + note: | + Vector basic bit-manipulation instructions + Zvkt: + presence: + optional: expansion + version: "~>1.0" + note: | + Vector basic bit-manipulation instructions + Supm: + presence: + optional: expansion + version: "~>1.0" + note: | + Pointer masking, with the execution environment providing + a means to select PMLEN=0 and PMLEN=7 at minimum + + #-------------------------------------------- + # Expansion options in RVB23 (and also RVA23) + #-------------------------------------------- + Zfh: + presence: + optional: expansion + version: "~>1.0" + note: A future RVB profile might mandate V. + Zbc: + presence: + optional: expansion + version: "~>1.0" + note: Scalar carryless multiplication + Zicfilp: + presence: + optional: expansion + version: "~>1.0" + note: Landing Pads + Zicfiss: + presence: + optional: expansion + version: "~>1.0" + note: Shadow Stack + Zvfh: + presence: + optional: expansion + version: "~>1.0" + note: Vector half-precision floating-point + Zfbfmin: + presence: + optional: expansion + version: "~>1.0" + note: Scalar BF16 conversion instructions + Zvfbfmin: + presence: + optional: expansion + version: "~>1.0" + note: Vector BF16 conversion instructions + Zvfbfwma: + presence: + optional: expansion + version: "~>1.0" + note: Vector BF16 widening mul-add instruction + + #-------------------------------------------- + # Zvbc is an expansion option in RVB23U64 + # (but is not intended to be made mandatory in future RVB Profiles) + # It will be listed in RVA23U64 as a *development* option, + # as it is intended to become mandatory in future RVA Profiles. + #-------------------------------------------- + Zvbc: + presence: + optional: expansion + version: "~>1.0" + note: Vector carryless multiplication + + #-------------------------------------------- + # Ssstrict is an expansion option in RVB2U64 and RVA23U64 + # (but is not intended to be made mandatory in future RVB or RVA Profiles) + #-------------------------------------------- + Ssstrict: + presence: + optional: expansion + version: "~>1.0" + note: | + all opcodes in the Standard and Reserved opcode spaces (SROS), + other than those identified in a Profile as Mandatory or Optional, + cause a trap. + # should the above say "current or subsequent Profile" rather than just "Profile"? + # (where is the official definition of Ssstrict?) + + ######################################################################### + # TRANSITORY EXPANSION extensions in RVB23 + ######################################################################### + + #-------------------------------------------- + # (there are no Transitory expansion options in RVB23) + #-------------------------------------------- diff --git a/arch/profile_release/RVA23.yaml b/arch/profile_release/RVA23.yaml index 49305dec0..102ad13b3 100644 --- a/arch/profile_release/RVA23.yaml +++ b/arch/profile_release/RVA23.yaml @@ -4,11 +4,11 @@ name: RVA23 marketing_name: RVA23 class: RVA release: 23 -state: ratified # current status ["ratified", "development"] +state: ratified # current status ["ratified", "development"] ratification_date: "2023-04-03" # Semantic versions within the release -versions: -- version: "1.0.0" +versions: + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -29,95 +29,5 @@ description: | It would be possible to also define very similar XLEN=32 variants. profiles: - RVA23U64: - marketing_name: RVA23U64 - mode: Unpriv - base: 64 - release: RVA23 - introduction: | - The RVA23U64 profile specifies the ISA features available to user-mode - execution environments in 64-bit applications processors. This is the - most important profile within application processors in - terms of the amount of software that targets this profile. - extensions: - ######################################################################### - # imported from RVB23U64 - ######################################################################### - $inherits: "RVB23.yaml#/profiles/RVB23U64/extensions" - $remove: Zvkg - $remove: Zvknc - $remove: Zvksc - $remove: Zkn - $remove: Zks - - ######################################################################### - # MANDATORY extensions in RVA23U64 (that were optional in RVB23U64) - ######################################################################### - - Zfhmin: - presence: mandatory - - V: - presence: mandatory - - Zvfhmin: - presence: mandatory - - Zvbb: - presence: mandatory - - Zvkt: - presence: mandatory - - Supm: - presence: mandatory - - #-------------------------------------------- - # Zvbc is an expansion option in RVB23U64 - # (but is not intended to be made mandatory in future RVB Profiles) - # - # It is listed in RVA23U64 as a *development* option, - # as it *is* intended to become mandatory in future RVA Profiles. - #-------------------------------------------- - Zvbc: - presence: - optional: development - - - ######################################################################### - # TRANSITORY EXPANSION extensions in RVA23U64 - ######################################################################### - - #-------------------------------------------- - # (there are no Transitory expansion options in RVA23U64) - #-------------------------------------------- - - - - RVA23S64: - marketing_name: RVA23S64 - mode: S - base: 64 - release: RVA23 - introduction: | - The RVA23S64 profile specifies the ISA features available to supervisor-mode - execution environments in 64-bit applications processors. - An ECALL in user mode causes a contained trap to supervisor mode. - An ECALL in supervisor mode causes a requested trap to the execution environment. - extensions: - ######################################################################### - # imported from RVB23U64 - ######################################################################### - $inherits: "RVB23.yaml#/profiles/RVB23S64/extensions" - - ######################################################################### - # MANDATORY extensions in RVA23S64 (that were optional in RVB23S64) - ######################################################################### - - Ssnpm: - presence: mandatory - # Pointer masking, with *senvcfg*.PME supporting, at minimum - - Sha: - presence: mandatory - # collection of Hypervisor extensions \ No newline at end of file + - { $ref: profile/RVA23U64.yaml# } + - { $ref: profile/RVA23S64.yaml# } diff --git a/arch/profile_release/RVB23.yaml b/arch/profile_release/RVB23.yaml index 26eff9336..98e453eac 100644 --- a/arch/profile_release/RVB23.yaml +++ b/arch/profile_release/RVB23.yaml @@ -1,14 +1,14 @@ -$schema: profile_schema.json# -kind: profile +$schema: profile_schema.json# +kind: profile name: RVB23 -marketing_name: RVB23 +marketing_name: RVB23 class: RVB release: 23 -state: ratified # current status ["ratified", "development"] +state: ratified # current status ["ratified", "development"] ratification_date: "2023-04-03" # Semantic versions within the release -versions: -- version: "1.0.0" +versions: + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -29,564 +29,5 @@ description: | It would be possible to also define very similar XLEN=32 variants. profiles: - RVB23U64: - marketing_name: RVB23U64 - mode: Unpriv - base: 64 - release: RVB23 - introduction: | - The RVB23U64 profile specifies the ISA features available to user-mode - execution environments in 64-bit applications processors. This is the - most important profile within application processors in - terms of the amount of software that targets this profile. - extensions: - ######################################################################### - # imported from RVA22 - ######################################################################### - $inherits: "RVA22.yaml#/RVA22/profiles/RVA22U64/extensions" - $remove: Za128rs - - ######################################################################### - # MANDATORY extensions in RVB23 (and RVA23) - ######################################################################### - Zihintntl: - presence: mandatory - version: "~>1.0" - note: | - Non-temporal memory-access locality hints - Zicond: - presence: mandatory - version: "~>1.0" - note: | - Integer conditional operations - Zimop: - presence: mandatory - version: "~>1.0" - note: | - May-be operations - Zcmop: - presence: mandatory - version: "~>1.0" - note: | - Commpressed (16-bit) may-be operations - Zcb: - presence: mandatory - version: "~>1.0" - note: | - Additional compressed (16-bit) instructions - Zfa: - presence: mandatory - version: "~>1.0" - note: | - Additional floating-point instructions - Zawrs: - presence: mandatory - version: "~>1.0" - note: | - Wait-on-reservation-set (WRS) instructions - Za64rs: - presence: mandatory - version: "~>1.0" - note: | - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes - - ######################################################################### - # OPTIONAL LOCALIZED extensions - ######################################################################### - - #--------------------------------- - # In RVB23 (and RVA23) - #--------------------------------- - Zvkng: - presence: - optional: localized - version: "~>1.0" - note: | - Vector crypto NIST Algorithms with GCM - Zvksg: - presence: - optional: localized - version: "~>1.0" - note: | - Vector crypto Shang-Mi Algorithms with GCM - - #--------------------------------- - # In RVB23 (but not in RVA23) - #--------------------------------- - Zvkg: - presence: - optional: localized - version: "~>1.0" - note: | - Vector GCM/GMAC instructions - - Zvknc: - presence: - optional: localized - version: "~>1.0" - note: | - Vector crypto NIST algorithms with carryless multiply. - To reduce implementation cost, RVB profiles allow this carryless multiply option to - implement GCM efficiently, with GHASH available as a separate option. - # RVA23 does not include Zvknc because it mandates the higher-performing - # but more expensive GHASH options when adding vector crypto. - Zvksc: - presence: - optional: localized - version: "~>1.0" - note: | - Vector crypto Shang-Mi algorithms with carryless multiply. - To reduce implementation cost, RVB profiles allow this carryless multiply option to - implement GCM efficiently, with GHASH available as a separate option. - # RVA23 does not include Zvksc because it mandates the higher-performing - # but more expensive GHASH options when adding vector crypto. - - Zkn: - presence: - optional: localized - version: "~>1.0" - note: | - Scalar crypto NIST algorithms - Zks: - presence: - optional: localized - version: "~>1.0" - note: | - Scalar crypto Shang-Mi algorithms - # RVA23 profiles drop support for the above scalar crypto as an option, as the vector - # extension is now mandatory in RVA23. - # RVB23 profiles do support scalar crypto as an option, as the vector extension is optional in RVB23. - - ######################################################################### - # OPTIONAL DEVELOPMENT extensions in RVB23 - ######################################################################### - # The following are new development options, intended to become mandatory in a later RVB profile: - Zabha: - presence: - optional: development - version: "~>1.0" - note: | - Byte and halfword atomic memory operations - Zacas: - presence: - optional: development - version: "~>1.0" - note: | - Compare-and-Swap instructions - Ziccamoc: - presence: - optional: development - version: "~>1.0" - note: | - Main memory regions with both the cacheability and coherence PMAs - must provide AMOCASQ-level PMA support - Zama16b: - presence: - optional: development - version: "~>1.0" - note: | - Misaligned loads, stores, and AMOs to main memory regions that do not cross - Daaaa naturally aligned 16-byte boundary are atomic - - ######################################################################### - # OPTIONAL EXPANSION extensions in RVB23 - ######################################################################### - - #--------------------------------- - # Optional in RVB23U64 (but Mandatory in RVA23U64) - #--------------------------------- - Zfhmin: - presence: - optional: expansion - version: "~> 1.0" - note: | - Zfhmin is a small extension that adds support to load/store and convert - IEEE 754 half-precision numbers to and from the IEEE 754 single-precision - format. The hardware cost for this extension is low, and mandating the - extension avoids adding an option to the profile. - V: - presence: - optional: expansion - version: "~> 1.0" - note: | - The Vector extension - # Note: it is unclear if other Zve* extensions should also be supported in RVB - - Zvfhmin: - presence: - optional: expansion - version: "~>1.0" - note: | - Vector minimal half-precision floating-point - Zvbb: - presence: - optional: expansion - version: "~>1.0" - note: | - Vector basic bit-manipulation instructions - Zvkt: - presence: - optional: expansion - version: "~>1.0" - note: | - Vector basic bit-manipulation instructions - Supm: - presence: - optional: expansion - version: "~>1.0" - note: | - Pointer masking, with the execution environment providing - a means to select PMLEN=0 and PMLEN=7 at minimum - - #-------------------------------------------- - # Expansion options in RVB23 (and also RVA23) - #-------------------------------------------- - Zfh: - presence: - optional: expansion - version: "~>1.0" - note: A future RVB profile might mandate V. - Zbc: - presence: - optional: expansion - version: "~>1.0" - note: Scalar carryless multiplication - Zicfilp: - presence: - optional: expansion - version: "~>1.0" - note: Landing Pads - Zicfiss: - presence: - optional: expansion - version: "~>1.0" - note: Shadow Stack - Zvfh: - presence: - optional: expansion - version: "~>1.0" - note: Vector half-precision floating-point - Zfbfmin: - presence: - optional: expansion - version: "~>1.0" - note: Scalar BF16 conversion instructions - Zvfbfmin: - presence: - optional: expansion - version: "~>1.0" - note: Vector BF16 conversion instructions - Zvfbfwma: - presence: - optional: expansion - version: "~>1.0" - note: Vector BF16 widening mul-add instruction - - #-------------------------------------------- - # Zvbc is an expansion option in RVB23U64 - # (but is not intended to be made mandatory in future RVB Profiles) - # It will be listed in RVA23U64 as a *development* option, - # as it is intended to become mandatory in future RVA Profiles. - #-------------------------------------------- - Zvbc: - presence: - optional: expansion - version: "~>1.0" - note: Vector carryless multiplication - - #-------------------------------------------- - # Ssstrict is an expansion option in RVB2U64 and RVA23U64 - # (but is not intended to be made mandatory in future RVB or RVA Profiles) - #-------------------------------------------- - Sstrict: - presence: - optional: expansion - version: "~>1.0" - note: | - all opcodes in the Standard and Reserved opcode spaces (SROS), - other than those identified in a Profile as Mandatory or Optional, - cause a trap. - # should the above say "current or subsequent Profile" rather than just "Profile"? - # (where is the official definition of Ssstrict?) - - - ######################################################################### - # TRANSITORY EXPANSION extensions in RVB23 - ######################################################################### - - #-------------------------------------------- - # (there are no Transitory expansion options in RVB23) - #-------------------------------------------- - - - - RVB23S64: - marketing_name: RVB23S64 - mode: S - base: 64 - release: RVB23 - introduction: | - The RVB23S64 profile specifies the ISA features available to supervisor-mode - execution environments in 64-bit applications processors. - An ECALL in user mode causes a contained trap to supervisor mode. - An ECALL in supervisor mode causes a requested trap to the execution environment. - extensions: - ######################################################################### - # imported from RVA23U64 - ######################################################################### - $inherits: "RVA22.yaml#/RVA22/profiles/RVA22S64/extensions" - - ######################################################################### - # MANDATORY extensions in RVB23 (and RVA23) - ######################################################################### - Zifencei: - presence: mandatory - version: "~>1.0" - note: | - Instruction-Fetch fence instruction. - - Zifencei is mandated as it is the only standard way to support - instruction-cache coherence in RVB23 application processors. - A new instruction-cache coherence mechanism is under development - (tentatively named Zjid), which might be added as an option in the future. - - Ss1p13: - presence: mandatory - version: "~>1.0" - note: | - Privileged architecture version 1.13 - - Svnapot: - presence: mandatory - version: "~>1.0" - note: | - NAPOT translation contiguity. - Svnapot is very low cost to provide, so is made mandatory even in RVB. - - Svbare: - presence: mandatory - version: "~>1.0" - note: | - The *satp* mode Bare must be supported - - Sv39: - presence: mandatory - version: "~>1.0" - note: | - Page-Based 39-bit Virtual-Memory System - - Svade: - presence: mandatory - version: "~>1.0" - note: | - A page-fault exception is raised when a page is accessed when A bit = 0 , - or when a page is written when D bit = 0 - - Ssccptr: - presence: mandatory - version: "~>1.0" - note: | - Main memory regions with both the cacheability and coherence PMAs must - support hardware page-table reads - - Sstvecd: - presence: mandatory - version: "~>1.0" - note: | - *stvec*.MODE must be capable of holding the value 0 (Direct). - When *stvec*.MODE=Direct, - *stvec*.BASE must be capable of holding any valid four-byte-aligned address - - Sstvala: - presence: mandatory - version: "~>1.0" - note: | - *stval* must be written with the faulting virtual address for load, store, - and instruction page-fault, access-fault, and misaligned exceptions, - and for breakpoint exceptions other than those caused by execution of - the EBREAK or C.EBREAK instructions. - For virtual-instruction and illegal instruction exceptions, - *stval* must be written with the faulting instruction . - - Sscounterenw: - presence: mandatory - version: "~>1.0" - note: | - For any *hpmcounter* that is not read-only zero, - the corresponding bit in *scounteren* must be writable. - - Svpbmt: - presence: mandatory - version: "~>1.0" - note: | - Page-based memory types - - Svinval: - presence: mandatory - version: "~>1.0" - note: | - Fine-grained address-translation cache invalidation - - Sstc: - presence: mandatory - version: "~>1.0" - note: | - Supervisor-mode timer interrupts. - - NOTE: Sstc was not made mandatory in RVB23S64 as it is a more - disruptive change affecting system-level architecture, and will take - longer for implementations to adopt. It is expected to be made - mandatory in the next profile release. - - Sscofpmf: - presence: mandatory - version: "~>1.0" - note: | - Count overflow and mode-based filtering. - Platforms may choose to mandate the presence of Sscofpmf. - - Ssu64xl: - presence: mandatory - version: "~>1.0" - note: | - *sstatus*.UXL must be capable of holding the value 2 - (that is, UXLEN=64 must be supported) - - - - ######################################################################### - # OPTIONAL LOCALIZED extensions in RVB23S64 - ######################################################################### - - # there are no Optional Localized extensions in RVB23S64 - - ######################################################################### - # OPTIONAL DEVELOPMENT extensions in RVB23S64 - ######################################################################### - - # there are no Optional Development extensions in RVB23S64 - - - ######################################################################### - # OPTIONAL EXPANSION extensions in RVB23S64 (mandatory in RVA23S64) - ######################################################################### - - Ssnpm: - presence: - optional: expansion - version: "~>1.0" - note: | - Pointer masking, with *senvcfg*.PME supporting, at minimum, - settings PMLEN=0 and PMLEN=7 - - Sha: - presence: - optional: expansion - version: "~>1.0" - note: | - The set of augmented hypervisor extensions: H, Ssstateen, - Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa - - __NEED_AN_EXTENSION_NAME_HERE__: - presence: - optional: expansion - version: "~>1.0" - when: - allOf: - - implemented: H - - implemented: Ssnpm - note: | - If the hypervisor extension is implemented - and pointer masking (Ssnpm) is supported - then *henvcfg*.PME must support at minimum, settings PMLEN=0 and PMLEN=7 - - - ######################################################################### - # OPTIONAL EXPANSION extensions in both RVB23S64 and RVA23S64 - ######################################################################### - - Sv48: - presence: - optional: expansion - version: "~>1.0" - note: | - Page-based 48-bit virtual-memory system - - Sv57: - presence: - optional: expansion - version: "~>1.0" - note: | - Page-based 57-bit virtual-memory system - - Svadu: - presence: - optional: expansion - version: "~>1.0" - note: | - Hardware A/D bit updates - - Zkr: - presence: - optional: expansion - version: "~>1.0" - note: | - Entropy CSR - - NOTE: Technically, Zk is also a privileged-mode option, capturing that - Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less - descriptive than specifying the individual extensions explicitly. - - Sdtrig: - presence: - optional: expansion - version: "~>1.0" - note: | - Debug triggers - - Ssstrict: - presence: - optional: expansion - version: "~>1.0" - note: | - No non-conforming extensions are present. - Attempts to execute unimplemented opcodes or access unimplemented CSRs in the - standard or reserved encoding spaces raises an illegal instruction exception - that results in a contained trap to the supervisor-mode trap handler - - NOTE: Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs. - - NOTE: Ssstrict definition applies to the execution environment claiming to be - RVB23-compatible, which must have the hypervisor extension. - That execution environment will take a contained trap to supervisor-mode - (however that trap is implemented, including, but not limited to, - emulation/delegation in the outer execution environment). - Ssstrict (and all the other RVB23 mandates and options) do not apply to - any guest VMs run by a hypervisor. - An RVB23 hypervisor can provide guest VMs that are also RVB23-compatible - but with an expanded set of emulated standard instructions. - An RVB23 hypervisor can also choose to implement guest VMs that are not - RVB23 compatible (for example, only RVA20 or only RVA22) - # that last parenthesized phrase for the RVA23 Profile would change to: - # (for example, lacking H, or only RVA20) - - Svvptc: - presence: - optional: expansion - version: "~>1.0" - note: | - Transitions from invalid to valid PTEs will be visible in bounded time - without an explicit memory-management fence. - - Sspm: - presence: - optional: expansion - version: "~>1.0" - note: | - Supervisor-mode pointer masking, with the supervisor execution environment - providing a means to select PMLEN=0 and PMLEN=7 (at minimum). - - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. \ No newline at end of file + - { $ref: profile/RVB23U64.yaml# } + - { $ref: profile/RVB23S64.yaml# } diff --git a/lib/arch_obj_models/portfolio.rb b/lib/arch_obj_models/portfolio.rb index 4f392465f..f741ebe4b 100644 --- a/lib/arch_obj_models/portfolio.rb +++ b/lib/arch_obj_models/portfolio.rb @@ -138,38 +138,36 @@ def in_scope_ext_reqs(desired_presence = nil) if ext.nil? puts "Extension #{ext_name} for #{name} not found in database" missing_ext = true - end - - actual_presence = ext_data["presence"] # Could be a String or Hash - raise "Missing extension presence for extension #{ext_name}" if actual_presence.nil? - - # Convert presence String or Hash to object. - actual_presence_obj = ExtensionPresence.new(actual_presence) + else + actual_presence = ext_data["presence"] # Could be a String or Hash + raise "Missing extension presence for extension #{ext_name}" if actual_presence.nil? - match = - if desired_presence.nil? - true # Always match - else - actual_presence_obj == desired_presence_converted - end + # Convert presence String or Hash to object. + actual_presence_obj = ExtensionPresence.new(actual_presence) - if match - in_scope_ext_reqs << - if ext_data.key?("version") - ExtensionRequirement.new( - ext_name, ext_data["version"], cfg_arch: @cfg_arch, - presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-#{ext_name}") + match = + if desired_presence.nil? + true # Always match else - ExtensionRequirement.new( - ext_name, cfg_arch: @cfg_arch, - presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-#{ext_name}") + actual_presence_obj == desired_presence_converted end + + if match + in_scope_ext_reqs << + if ext_data.key?("version") + ExtensionRequirement.new( + ext_name, ext_data["version"], cfg_arch: @cfg_arch, + presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-#{ext_name}") + else + ExtensionRequirement.new( + ext_name, cfg_arch: @cfg_arch, + presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-#{ext_name}") + end + end end end - # TODO: Change to "raise" when missing extensions added to database so we can make progress until then. - # See https://github.com/riscv-software-src/riscv-unified-db/issues/320 - puts "One or more extensions referenced by #{name} missing in database" if missing_ext + raise "One or more extensions referenced by #{name} missing in database" if missing_ext in_scope_ext_reqs end