From 28082d3da9f10eca7ac4e1f9f1253f275282fe19 Mon Sep 17 00:00:00 2001 From: Jennifer Dupaquier <11723765+jmawet@users.noreply.github.com> Date: Tue, 11 Feb 2025 09:49:10 -0800 Subject: [PATCH] Update Zicond instructions * Complete czero instructions * Syntax and style change * Fix Sail code in `czero.eqz` --- arch/inst/Zicond/czero.eqz.yaml | 10 +++++++--- arch/inst/Zicond/czero.nez.yaml | 8 ++++++-- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml index 63e65aa53..63bdc5a6b 100644 --- a/arch/inst/Zicond/czero.eqz.yaml +++ b/arch/inst/Zicond/czero.eqz.yaml @@ -3,9 +3,12 @@ $schema: "inst_schema.json#" kind: instruction name: czero.eqz -long_name: No synopsis available. +long_name: Conditional zero, if condition is equal to zero. description: | - No description available. + If rs2 contains the value zero, this instruction writes the value zero to rd. Otherwise, this instruction + copies the contents of rs1 to rd. + This instruction carries a syntactic dependency from both rs1 and rs2 to rd. Furthermore, if the Zkt + extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2. definedBy: Zicond assembly: xd, xs1, xs2 encoding: @@ -24,12 +27,13 @@ access: vu: always data_independent_timing: false operation(): | + X[rd] = (X[rs2] == 0) ? 0 : X[rs1]; sail(): | { let value = X(rs1); let condition = X(rs2); - let result : xlenbits = if (condition != zeros()) then zeros() + let result : xlenbits = if (condition == zeros()) then zeros() else value; X(rd) = result; RETIRE_SUCCESS diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml index f3824848a..1e969a605 100644 --- a/arch/inst/Zicond/czero.nez.yaml +++ b/arch/inst/Zicond/czero.nez.yaml @@ -3,9 +3,12 @@ $schema: "inst_schema.json#" kind: instruction name: czero.nez -long_name: No synopsis available. +long_name: Conditional zero, if condition is nonzero. description: | - No description available. + If rs2 contains a nonzero value, this instruction writes the value zero to rd. Otherwise, this + instruction copies the contents of rs1 to rd. + This instruction carries a syntactic dependency from both rs1 and rs2 to rd. Furthermore, if the Zkt + extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2. definedBy: Zicond assembly: xd, xs1, xs2 encoding: @@ -24,6 +27,7 @@ access: vu: always data_independent_timing: false operation(): | + X[rd] = (X[rs2] != 0) ? 0 : X[rs1]; sail(): | {