From db0d1cb39ebb14c837023e725d3fc01336bc386c Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 22 Nov 2024 08:07:32 -0800 Subject: [PATCH 01/11] Create smoke,regress,nightly tests; Add nightly GitHub workflow --- .github/workflows/nightly.yml | 54 ++++++++++ .github/workflows/regress.yml | 2 +- README.adoc | 4 +- Rakefile | 188 ++++++++++++++++++++-------------- backends/arch_gen/tasks.rake | 17 +-- 5 files changed, 175 insertions(+), 90 deletions(-) create mode 100644 .github/workflows/nightly.yml diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml new file mode 100644 index 000000000..084687ad4 --- /dev/null +++ b/.github/workflows/nightly.yml @@ -0,0 +1,54 @@ +name: Regression test + +on: + schedule: + - cron: '30 2 * * *' + workflow_dispatch: + +jobs: + # check_date from: https://stackoverflow.com/questions/63014786/how-to-schedule-a-github-actions-nightly-build-but-run-it-only-when-there-where + check_date: + runs-on: ubuntu-latest + name: Check latest commit + outputs: + should_run: ${{ steps.should_run.outputs.should_run }} + steps: + - uses: actions/checkout@v2 + - name: print latest_commit + run: echo ${{ github.sha }} + + - id: should_run + continue-on-error: true + name: check latest commit is less than a day + if: ${{ github.event_name == 'schedule' }} + run: test -z $(git rev-list --after="24 hours" ${{ github.sha }}) && echo "::set-output name=should_run::false" + nightly: + needs: check_date + if: ${{ needs.check_date.outputs.should_run != 'false' }} + runs-on: ubuntu-latest + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Run regression + run: ./do test:nightly diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index 742d918b6..fac7e3df9 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -32,4 +32,4 @@ jobs: - name: Setup project run: ./bin/setup - name: Run regression - run: ./do regress + run: ./do test:regress diff --git a/README.adoc b/README.adoc index 1aeb1753d..816a2fc4f 100644 --- a/README.adoc +++ b/README.adoc @@ -105,8 +105,8 @@ Quick start: ## examples -# validate against the schema -./do validate +# run smoke tests +./do test:smoke # generate all versions of ISA manual, as an Antora static website ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all diff --git a/Rakefile b/Rakefile index 0b2a9f9a5..ec59a4b28 100644 --- a/Rakefile +++ b/Rakefile @@ -55,20 +55,22 @@ namespace :serve do end end -desc "Run the IDL compiler test suite" -task :idl_test do - t = Minitest::TestTask.new(:lib_test) - t.test_globs = ["#{$root}/lib/idl/tests/test_*.rb"] - t.process_env - ruby t.make_test_cmd -end +namespace :test do + # "Run the IDL compiler test suite" + task :idl_compiler do + t = Minitest::TestTask.new(:lib_test) + t.test_globs = ["#{$root}/lib/idl/tests/test_*.rb"] + t.process_env + ruby t.make_test_cmd + end -desc "Run the Ruby library test suite" -task :lib_test do - t = Minitest::TestTask.new(:lib_test) - t.test_globs = ["#{$root}/lib/test/test_*.rb"] - t.process_env - ruby t.make_test_cmd + # "Run the Ruby library test suite" + task :lib do + t = Minitest::TestTask.new(:lib_test) + t.test_globs = ["#{$root}/lib/test/test_*.rb"] + t.process_env + ruby t.make_test_cmd + end end desc "Clean up all generated files" @@ -77,7 +79,7 @@ task :clean do FileUtils.rm_rf $root / ".stamps" end -namespace :validate do +namespace :test do task :insts do puts "Checking instruction encodings..." inst_paths = Dir.glob("#{$root}/arch/inst/**/*.yaml").map { |f| Pathname.new(f) } @@ -95,9 +97,10 @@ namespace :validate do progressbar.increment validator.validate(f) end + Rake::Task["test:insts"].invoke puts "All files validate against their schema" end - task idl: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"] do + task idl_model: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"] do print "Parsing IDL code for RV32..." arch_def_32 = arch_def_for("_32") puts "done" @@ -114,9 +117,6 @@ namespace :validate do end end -desc "Validate the arch docs" -task validate: ["validate:schema", "validate:idl", "validate:insts"] - def insert_warning(str, from) # insert a warning on the second line lines = str.lines @@ -274,67 +274,97 @@ namespace :gen do end end -desc <<~DESC - Run the regression tests - - These tests must pass before a commit will be allowed in the main branch on GitHub -DESC -task :regress do - Rake::Task["idl_test"].invoke - Rake::Task["lib_test"].invoke - Rake::Task["validate"].invoke - ENV["MANUAL_NAME"] = "isa" - ENV["VERSIONS"] = "all" - Rake::Task["gen:html_manual"].invoke - Rake::Task["gen:html"].invoke("generic_rv64") - Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke - Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke - Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke - Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke - Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke - Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke - - puts - puts "Regression test PASSED" +namespace :test do + desc <<~DESC + Run smoke tests + + These are basic but fast-running tests to check the database and tools + DESC + task :smoke do + Rake::Task["test:idl_compiler"].invoke + Rake::Task["test:lib"].invoke + Rake::Task["test:schema"].invoke + Rake::Task["test:idl_model"].invoke + end + + desc <<~DESC + Run the regression tests + + These tests must pass before a commit will be allowed in the main branch on GitHub + DESC + task :regress do + Rake::Task["test:smoke"].invoke + + ENV["MANUAL_NAME"] = "isa" + ENV["VERSIONS"] = "all" + Rake::Task["gen:html_manual"].invoke + + Rake::Task["gen:html"].invoke("generic_rv64") + + Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke + + puts + puts "Regression test PASSED" + end + + desc <<~DESC + Run the nightly regression tests + + Generally, this tries to build all artifacts + DESC + task :nightly do + Rake::Task["regress"].invoke + + Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke + + puts + puts "Nightly regression test PASSED" + end end -desc <<~DESC - Generate all certificates and profile PDFs. -DESC -task :cert_profile_pdfs do - puts "===================================" - puts "cert_profile_pdfs: Generating MC100" - puts " 1st target" - puts "===================================" - Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke - - puts "==================================================" - puts "cert_profile_pdfs: Generating MockCertificateModel" - puts " 2nd target" - puts "==================================================" - Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke - - puts "===================================" - puts "cert_profile_pdfs: Generating RVA20" - puts " 3rd target" - puts "===================================" - Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke - - puts "===================================" - puts "cert_profile_pdfs: Generating RVA22" - puts " 4th target" - puts "===================================" - Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke - - puts "===================================" - puts "cert_profile_pdfs: Generating RVI20" - puts " 5th target" - puts "===================================" - Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke - - puts "===================================" - puts "cert_profile_pdfs: Generating MockProfileRelease" - puts " 6th target" - puts "===================================" - Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke +namespace :gen do + desc <<~DESC + Generate all certificates and profile PDFs. + DESC + task :cert_profile_pdfs do + puts "===================================" + puts "cert_profile_pdfs: Generating MC100" + puts " 1st target" + puts "===================================" + Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke + + puts "==================================================" + puts "cert_profile_pdfs: Generating MockCertificateModel" + puts " 2nd target" + puts "==================================================" + Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVA20" + puts " 3rd target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVA22" + puts " 4th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVI20" + puts " 5th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating MockProfileRelease" + puts " 6th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke + end end \ No newline at end of file diff --git a/backends/arch_gen/tasks.rake b/backends/arch_gen/tasks.rake index 6515e54f5..e8ebbf40d 100644 --- a/backends/arch_gen/tasks.rake +++ b/backends/arch_gen/tasks.rake @@ -168,13 +168,14 @@ namespace :gen do end end -namespace :validate do - desc "Validate that a configuration folder valid for the list of extensions it claims to implement" - task :cfg, [:config_name] do |_t, args| - raise "No config '#{args[:config_name]}' found in cfgs/" unless ($root / "cfgs" / args[:config_name]).directory? +# TODO: Add this back once we settle on the config file format +# namespace :validate do +# desc "Validate that a configuration folder valid for the list of extensions it claims to implement" +# task :cfg, [:config_name] do |_t, args| +# raise "No config '#{args[:config_name]}' found in cfgs/" unless ($root / "cfgs" / args[:config_name]).directory? - ArchGen.new(args[:config_name]).validate_params +# ArchGen.new(args[:config_name]).validate_params - puts "Success! The '#{args[:config_name]}' configuration passes validation checks" - end -end +# puts "Success! The '#{args[:config_name]}' configuration passes validation checks" +# end +# end From 57fda0bb9447b2dd72bb5780cab43132adc7768a Mon Sep 17 00:00:00 2001 From: james-ball-qualcomm Date: Fri, 22 Nov 2024 19:29:52 +0000 Subject: [PATCH 02/11] Just need to add to RVA22 (already in RVA20). Also changed to bullet list for each separate recommendation. --- arch/profile_release/RVA22.yaml | 10 +++++++++- backends/profile_doc/templates/profile.adoc.erb | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 327ff31aa..f89d406e2 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -156,6 +156,10 @@ RVA22: text: | The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible with the profile mandates to support the F and D extensions. + recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVA22S64: marketing_name: RVA22S64 mode: S @@ -257,4 +261,8 @@ RVA22: * Shvstvala * Shtvala * Shvstvecd - * Shgatpa \ No newline at end of file + * Shgatpa + recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. \ No newline at end of file diff --git a/backends/profile_doc/templates/profile.adoc.erb b/backends/profile_doc/templates/profile.adoc.erb index 5a5d48411..838ca78d9 100644 --- a/backends/profile_doc/templates/profile.adoc.erb +++ b/backends/profile_doc/templates/profile.adoc.erb @@ -390,7 +390,7 @@ associated implementation-defined parameters across all its defined profiles. Recommendations are not strictly mandated but are included to guide implementers making design choices. <% profile.recommendations.each do |recommendation| -%> -<%= recommendation.text %> +* <%= recommendation.text %> <% end # each recommendation -%> <% end # unless recommendations empty -%> From 30cb418b32993b49353aa3d4fe6b855d3f488c96 Mon Sep 17 00:00:00 2001 From: james-ball-qualcomm Date: Fri, 22 Nov 2024 20:02:46 +0000 Subject: [PATCH 03/11] Changed all = to ~> versions I found. --- arch/profile_release/MockProfileRelease.yaml | 10 +++---- arch/profile_release/RVA20.yaml | 28 ++++++++++---------- arch/profile_release/RVA22.yaml | 10 +++---- arch/profile_release/RVI20.yaml | 14 +++++----- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 562af1c53..45104cdec 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -27,7 +27,7 @@ MockProfileRelease: extensions: A: presence: optional - version: "= 2.1" + version: "~> 2.1" I: presence: mandatory version: "~> 2.1" @@ -52,21 +52,21 @@ MockProfileRelease: S: presence: optional: localized - version: "= 1.12" + version: "~> 1.12" Zifencei: presence: optional: development - version: "= 2.0" + version: "~> 2.0" note: Zihpm: presence: optional: expansion - version: "= 2.0" + version: "~> 2.0" note: Made this a expansion option Sv48: presence: optional: transitory - version: "= 1.11" + version: "~> 1.11" note: Made this a transitory option extra_notes: - presence: mandatory diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index 6be79e41d..279024c2c 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -66,29 +66,29 @@ RVA20: presence: mandatory Ziccif: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Ziccif is a profile-defined extension introduced with RVA20. The fetch atomicity requirement facilitates runtime patching of aligned instructions. Ziccrse: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: Ziccrse is a profile-defined extension introduced with RVA20. Ziccamoa: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: Ziccamo is a profile-defined extension introduced with RVA20. Za128rs: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Za128rs is a profile-defined extension introduced with RVA20. The minimum reservation set size is effectively determined by the size of atomic accesses in the `A` extension. Zicclsm: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Zicclsm is a profile-defined extension introduced with RVA20. This requires misaligned support for all regular load and store @@ -140,10 +140,10 @@ RVA20: extensions: S: presence: mandatory - version: "= 1.11" + version: "~> 1.11" Zifencei: presence: mandatory - version: "= 2.0" + version: "~> 2.0" note: | Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA20 application processors. A new @@ -151,12 +151,12 @@ RVA20: be added as an option in the future. Svbare: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Svbare is a new extension name introduced with RVA20. Sv39: presence: mandatory - version: "= 1.11" + version: "~> 1.11" Svade: presence: mandatory version: "~> 1.0" @@ -167,24 +167,24 @@ RVA20: `Svadu`. Ssccptr: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Ssccptr is a new extension name introduced with RVA20. Sstvecd: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Sstvecd is a new extension name introduced with RVA20. Sstvala: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Sstvala is a new extension name introduced with RVA20. Sv48: presence: optional - version: "= 1.11" + version: "~> 1.11" Ssu64xl: presence: optional - version: "= 1.0" + version: "~> 1.0" note: | Ssu64xl is a new extension name introduced with RVA20. \ No newline at end of file diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 327ff31aa..7bcb16dc7 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -46,10 +46,10 @@ RVA22: $inherits: "profile_release/RVA20.yaml#/RVA20/profiles/RVA20U64/extensions" Zihpm: presence: mandatory - version: "= 2.0" + version: "~> 2.0" Zihintpause: presence: mandatory - version: "= 2.0" + version: "~> 2.0" note: | While the `pause` instruction is a HINT can be implemented as a NOP and hence trivially supported by hardware implementers, its @@ -68,7 +68,7 @@ RVA22: version: "~> 1.0" Zic64b: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | This is a new extension name for this feature. While the general RISC-V specifications are agnostic to cache block size, selecting a @@ -170,10 +170,10 @@ RVA22: $inherits: "profile_release/RVA20.yaml#/RVA20/profiles/RVA20S64/extensions" S: presence: mandatory - version: "= 1.12" + version: "~> 1.12" Sscounterenw: presence: mandatory - version: "= 1.0" + version: "~> 1.0" note: | Sstvala is a new extension name introduced with RVA22. Svpbmt: diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 759619cae..07e8e1081 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -50,13 +50,13 @@ RVI20: correctly indicate that `fence.tso` is mandatory. A: presence: optional - version: "= 2.1" + version: "~> 2.1" C: presence: optional - version: "= 2.2" + version: "~> 2.2" D: presence: optional - version: "= 2.2" + version: "~> 2.2" note: | NOTE: The rationale to not include Q as a profile option is that quad-precision floating-point is unlikely to be implemented in @@ -64,21 +64,21 @@ RVI20: optimizing use of Q instructions in case they are present. F: presence: optional - version: "= 2.2" + version: "~> 2.2" M: presence: optional - version: "= 2.0" + version: "~> 2.0" Zicntr: presence: optional version: " = 2.0" Zihpm: presence: optional - version: "= 2.0" + version: "~> 2.0" note: | The number of counters is platform-specific. Zifencei: presence: optional - version: "= 2.0" + version: "~> 2.0" recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction From 67554d914d4afa67daa20d1f73246f813b8c299f Mon Sep 17 00:00:00 2001 From: Kevin Broch Date: Fri, 22 Nov 2024 19:22:27 -0800 Subject: [PATCH 04/11] restrict date regex to only valid months; fixes #310 --- schemas/ext_schema.json | 3 ++- schemas/schema_defs.json | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/schemas/ext_schema.json b/schemas/ext_schema.json index 8c281c4e6..724e93128 100644 --- a/schemas/ext_schema.json +++ b/schemas/ext_schema.json @@ -147,7 +147,8 @@ }, "ratification_date": { "oneOf": [ - {"type": "string", "pattern": "^20[0-9][0-9]-[0-9][0-9]$", "$comment": "When ratification date is known" }, + {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", + "description": "A specific year and month in YYYY-MM format", "examples": ["2019-01", "2024-12"] }, {"type": "string", "pattern": "^unknown$", "$comment": "When ratification date is unknown" }, {"type": "null", "$comment": "When version isn't ratified" } ] diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 57c886132..1b954ba32 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -80,7 +80,8 @@ "date": { "type": "string", "format": "date", - "description": "A specific day in YYYY-MM-DD format, for example 2018-11-13" + "description": "A specific day in YYYY-MM-DD format", + "examples": ["2018-11-13", "2024-12-31"] }, "extension_name": { "type": "string", @@ -91,7 +92,7 @@ }, "requirement_string": { "type": "string", - "pattern": "^((>=)|(>)|(~>)|(<)|(<=)|(=))\\s*[0-9]+(\\.[0-9]+(\\.[0-9]+(-[a-fA-F0-9]+)?)?)?$" + "pattern": "^((>=)|(>)|(~>)|(<)|(<=)|(=))?\\s*[0-9]+(\\.[0-9]+(\\.[0-9]+(-[a-fA-F0-9]+)?)?)?$" }, "version_requirements": { "description": "A (set of) version requirements", From 2a079630bd0675e0a75195790987459de5d010cd Mon Sep 17 00:00:00 2001 From: Afonso Oliveira Date: Tue, 26 Nov 2024 21:12:55 +0000 Subject: [PATCH 05/11] Add V extension missing isntructions Signed-off-by: Afonso Oliveira --- arch/inst/V/vloxseg2ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg2ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg2ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg2ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg3ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg3ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg3ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg3ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg4ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg4ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg4ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg4ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg5ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg5ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg5ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg5ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg6ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg6ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg6ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg6ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg7ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg7ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg7ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg7ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg8ei16.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg8ei32.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg8ei64.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vloxseg8ei8.v.yaml | 29 +++++++++++++++++++++++++++++ arch/inst/V/vlseg2e16.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e16ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e32.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e32ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e64.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e64ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e8.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg2e8ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e16.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e16ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e32.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e32ff.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e64.v.yaml | 27 +++++++++++++++++++++++++++ arch/inst/V/vlseg3e64ff.v.yaml | 27 +++++++++++++++++++++++++++ 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arch/inst/V/vlsseg2e16.v.yaml create mode 100644 arch/inst/V/vlsseg2e32.v.yaml create mode 100644 arch/inst/V/vlsseg2e64.v.yaml create mode 100644 arch/inst/V/vlsseg2e8.v.yaml create mode 100644 arch/inst/V/vlsseg3e16.v.yaml create mode 100644 arch/inst/V/vlsseg3e32.v.yaml create mode 100644 arch/inst/V/vlsseg3e64.v.yaml create mode 100644 arch/inst/V/vlsseg3e8.v.yaml create mode 100644 arch/inst/V/vlsseg4e16.v.yaml create mode 100644 arch/inst/V/vlsseg4e32.v.yaml create mode 100644 arch/inst/V/vlsseg4e64.v.yaml create mode 100644 arch/inst/V/vlsseg4e8.v.yaml create mode 100644 arch/inst/V/vlsseg5e16.v.yaml create mode 100644 arch/inst/V/vlsseg5e32.v.yaml create mode 100644 arch/inst/V/vlsseg5e64.v.yaml create mode 100644 arch/inst/V/vlsseg5e8.v.yaml create mode 100644 arch/inst/V/vlsseg6e16.v.yaml create mode 100644 arch/inst/V/vlsseg6e32.v.yaml create mode 100644 arch/inst/V/vlsseg6e64.v.yaml create mode 100644 arch/inst/V/vlsseg6e8.v.yaml create mode 100644 arch/inst/V/vlsseg7e16.v.yaml create mode 100644 arch/inst/V/vlsseg7e32.v.yaml create mode 100644 arch/inst/V/vlsseg7e64.v.yaml create mode 100644 arch/inst/V/vlsseg7e8.v.yaml create mode 100644 arch/inst/V/vlsseg8e16.v.yaml create mode 100644 arch/inst/V/vlsseg8e32.v.yaml create mode 100644 arch/inst/V/vlsseg8e64.v.yaml create mode 100644 arch/inst/V/vlsseg8e8.v.yaml create mode 100644 arch/inst/V/vluxseg2ei16.v.yaml create mode 100644 arch/inst/V/vluxseg2ei32.v.yaml create mode 100644 arch/inst/V/vluxseg2ei64.v.yaml create mode 100644 arch/inst/V/vluxseg2ei8.v.yaml create mode 100644 arch/inst/V/vluxseg3ei16.v.yaml create mode 100644 arch/inst/V/vluxseg3ei32.v.yaml create mode 100644 arch/inst/V/vluxseg3ei64.v.yaml create mode 100644 arch/inst/V/vluxseg3ei8.v.yaml create mode 100644 arch/inst/V/vluxseg4ei16.v.yaml create mode 100644 arch/inst/V/vluxseg4ei32.v.yaml create mode 100644 arch/inst/V/vluxseg4ei64.v.yaml create mode 100644 arch/inst/V/vluxseg4ei8.v.yaml create mode 100644 arch/inst/V/vluxseg5ei16.v.yaml create mode 100644 arch/inst/V/vluxseg5ei32.v.yaml create mode 100644 arch/inst/V/vluxseg5ei64.v.yaml create mode 100644 arch/inst/V/vluxseg5ei8.v.yaml create mode 100644 arch/inst/V/vluxseg6ei16.v.yaml create mode 100644 arch/inst/V/vluxseg6ei32.v.yaml create mode 100644 arch/inst/V/vluxseg6ei64.v.yaml create mode 100644 arch/inst/V/vluxseg6ei8.v.yaml create mode 100644 arch/inst/V/vluxseg7ei16.v.yaml create mode 100644 arch/inst/V/vluxseg7ei32.v.yaml create mode 100644 arch/inst/V/vluxseg7ei64.v.yaml create mode 100644 arch/inst/V/vluxseg7ei8.v.yaml create mode 100644 arch/inst/V/vluxseg8ei16.v.yaml create mode 100644 arch/inst/V/vluxseg8ei32.v.yaml create mode 100644 arch/inst/V/vluxseg8ei64.v.yaml create mode 100644 arch/inst/V/vluxseg8ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg2ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg2ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg2ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg2ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg3ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg3ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg3ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg3ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg4ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg4ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg4ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg4ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg5ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg5ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg5ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg5ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg6ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg6ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg6ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg6ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg7ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg7ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg7ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg7ei8.v.yaml create mode 100644 arch/inst/V/vsoxseg8ei16.v.yaml create mode 100644 arch/inst/V/vsoxseg8ei32.v.yaml create mode 100644 arch/inst/V/vsoxseg8ei64.v.yaml create mode 100644 arch/inst/V/vsoxseg8ei8.v.yaml create mode 100644 arch/inst/V/vsseg2e16.v.yaml create mode 100644 arch/inst/V/vsseg2e32.v.yaml create mode 100644 arch/inst/V/vsseg2e64.v.yaml create mode 100644 arch/inst/V/vsseg2e8.v.yaml create mode 100644 arch/inst/V/vsseg3e16.v.yaml create mode 100644 arch/inst/V/vsseg3e32.v.yaml create mode 100644 arch/inst/V/vsseg3e64.v.yaml create mode 100644 arch/inst/V/vsseg3e8.v.yaml create mode 100644 arch/inst/V/vsseg4e16.v.yaml create mode 100644 arch/inst/V/vsseg4e32.v.yaml create mode 100644 arch/inst/V/vsseg4e64.v.yaml create mode 100644 arch/inst/V/vsseg4e8.v.yaml create mode 100644 arch/inst/V/vsseg5e16.v.yaml create mode 100644 arch/inst/V/vsseg5e32.v.yaml create mode 100644 arch/inst/V/vsseg5e64.v.yaml create mode 100644 arch/inst/V/vsseg5e8.v.yaml create mode 100644 arch/inst/V/vsseg6e16.v.yaml create mode 100644 arch/inst/V/vsseg6e32.v.yaml create mode 100644 arch/inst/V/vsseg6e64.v.yaml create mode 100644 arch/inst/V/vsseg6e8.v.yaml create mode 100644 arch/inst/V/vsseg7e16.v.yaml create mode 100644 arch/inst/V/vsseg7e32.v.yaml create mode 100644 arch/inst/V/vsseg7e64.v.yaml create mode 100644 arch/inst/V/vsseg7e8.v.yaml create mode 100644 arch/inst/V/vsseg8e16.v.yaml create mode 100644 arch/inst/V/vsseg8e32.v.yaml create mode 100644 arch/inst/V/vsseg8e64.v.yaml create mode 100644 arch/inst/V/vsseg8e8.v.yaml create mode 100644 arch/inst/V/vssseg2e16.v.yaml create mode 100644 arch/inst/V/vssseg2e32.v.yaml create mode 100644 arch/inst/V/vssseg2e64.v.yaml create mode 100644 arch/inst/V/vssseg2e8.v.yaml create mode 100644 arch/inst/V/vssseg3e16.v.yaml create mode 100644 arch/inst/V/vssseg3e32.v.yaml create mode 100644 arch/inst/V/vssseg3e64.v.yaml create mode 100644 arch/inst/V/vssseg3e8.v.yaml create mode 100644 arch/inst/V/vssseg4e16.v.yaml create mode 100644 arch/inst/V/vssseg4e32.v.yaml create mode 100644 arch/inst/V/vssseg4e64.v.yaml create mode 100644 arch/inst/V/vssseg4e8.v.yaml create mode 100644 arch/inst/V/vssseg5e16.v.yaml create mode 100644 arch/inst/V/vssseg5e32.v.yaml create mode 100644 arch/inst/V/vssseg5e64.v.yaml create mode 100644 arch/inst/V/vssseg5e8.v.yaml create mode 100644 arch/inst/V/vssseg6e16.v.yaml create mode 100644 arch/inst/V/vssseg6e32.v.yaml create mode 100644 arch/inst/V/vssseg6e64.v.yaml create mode 100644 arch/inst/V/vssseg6e8.v.yaml create mode 100644 arch/inst/V/vssseg7e16.v.yaml create mode 100644 arch/inst/V/vssseg7e32.v.yaml create mode 100644 arch/inst/V/vssseg7e64.v.yaml create mode 100644 arch/inst/V/vssseg7e8.v.yaml create mode 100644 arch/inst/V/vssseg8e16.v.yaml create mode 100644 arch/inst/V/vssseg8e32.v.yaml create mode 100644 arch/inst/V/vssseg8e64.v.yaml create mode 100644 arch/inst/V/vssseg8e8.v.yaml create mode 100644 arch/inst/V/vsuxseg2ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg2ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg2ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg2ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg3ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg3ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg3ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg3ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg4ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg4ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg4ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg4ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg5ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg5ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg5ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg5ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg6ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg6ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg6ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg6ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg7ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg7ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg7ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg7ei8.v.yaml create mode 100644 arch/inst/V/vsuxseg8ei16.v.yaml create mode 100644 arch/inst/V/vsuxseg8ei32.v.yaml create mode 100644 arch/inst/V/vsuxseg8ei64.v.yaml create mode 100644 arch/inst/V/vsuxseg8ei8.v.yaml diff --git a/arch/inst/V/vloxseg2ei16.v.yaml b/arch/inst/V/vloxseg2ei16.v.yaml new file mode 100644 index 000000000..5aeb4b87b --- /dev/null +++ b/arch/inst/V/vloxseg2ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg2ei32.v.yaml b/arch/inst/V/vloxseg2ei32.v.yaml new file mode 100644 index 000000000..5300087df --- /dev/null +++ b/arch/inst/V/vloxseg2ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg2ei64.v.yaml b/arch/inst/V/vloxseg2ei64.v.yaml new file mode 100644 index 000000000..31f4736c5 --- /dev/null +++ b/arch/inst/V/vloxseg2ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg2ei8.v.yaml b/arch/inst/V/vloxseg2ei8.v.yaml new file mode 100644 index 000000000..fdbb69faf --- /dev/null +++ b/arch/inst/V/vloxseg2ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg3ei16.v.yaml b/arch/inst/V/vloxseg3ei16.v.yaml new file mode 100644 index 000000000..7564e9cbb --- /dev/null +++ b/arch/inst/V/vloxseg3ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg3ei32.v.yaml b/arch/inst/V/vloxseg3ei32.v.yaml new file mode 100644 index 000000000..c6519f8a4 --- /dev/null +++ b/arch/inst/V/vloxseg3ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg3ei64.v.yaml b/arch/inst/V/vloxseg3ei64.v.yaml new file mode 100644 index 000000000..fb86e732d --- /dev/null +++ b/arch/inst/V/vloxseg3ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg3ei8.v.yaml b/arch/inst/V/vloxseg3ei8.v.yaml new file mode 100644 index 000000000..5ca294825 --- /dev/null +++ b/arch/inst/V/vloxseg3ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg4ei16.v.yaml b/arch/inst/V/vloxseg4ei16.v.yaml new file mode 100644 index 000000000..1960fce8d --- /dev/null +++ b/arch/inst/V/vloxseg4ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg4ei32.v.yaml b/arch/inst/V/vloxseg4ei32.v.yaml new file mode 100644 index 000000000..d136ebbc1 --- /dev/null +++ b/arch/inst/V/vloxseg4ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg4ei64.v.yaml b/arch/inst/V/vloxseg4ei64.v.yaml new file mode 100644 index 000000000..296266ecc --- /dev/null +++ b/arch/inst/V/vloxseg4ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg4ei8.v.yaml b/arch/inst/V/vloxseg4ei8.v.yaml new file mode 100644 index 000000000..f59d7f753 --- /dev/null +++ b/arch/inst/V/vloxseg4ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg5ei16.v.yaml b/arch/inst/V/vloxseg5ei16.v.yaml new file mode 100644 index 000000000..3485edbd2 --- /dev/null +++ b/arch/inst/V/vloxseg5ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg5ei32.v.yaml b/arch/inst/V/vloxseg5ei32.v.yaml new file mode 100644 index 000000000..18afff163 --- /dev/null +++ b/arch/inst/V/vloxseg5ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg5ei64.v.yaml b/arch/inst/V/vloxseg5ei64.v.yaml new file mode 100644 index 000000000..dbd68647c --- /dev/null +++ b/arch/inst/V/vloxseg5ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg5ei8.v.yaml b/arch/inst/V/vloxseg5ei8.v.yaml new file mode 100644 index 000000000..c7014818a --- /dev/null +++ b/arch/inst/V/vloxseg5ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg6ei16.v.yaml b/arch/inst/V/vloxseg6ei16.v.yaml new file mode 100644 index 000000000..1657012d3 --- /dev/null +++ b/arch/inst/V/vloxseg6ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg6ei32.v.yaml b/arch/inst/V/vloxseg6ei32.v.yaml new file mode 100644 index 000000000..c6ac3fc24 --- /dev/null +++ b/arch/inst/V/vloxseg6ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg6ei64.v.yaml b/arch/inst/V/vloxseg6ei64.v.yaml new file mode 100644 index 000000000..2c0fc1603 --- /dev/null +++ b/arch/inst/V/vloxseg6ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg6ei8.v.yaml b/arch/inst/V/vloxseg6ei8.v.yaml new file mode 100644 index 000000000..5685617fa --- /dev/null +++ b/arch/inst/V/vloxseg6ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg7ei16.v.yaml b/arch/inst/V/vloxseg7ei16.v.yaml new file mode 100644 index 000000000..d250dad20 --- /dev/null +++ b/arch/inst/V/vloxseg7ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg7ei32.v.yaml b/arch/inst/V/vloxseg7ei32.v.yaml new file mode 100644 index 000000000..5013d140a --- /dev/null +++ b/arch/inst/V/vloxseg7ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg7ei64.v.yaml b/arch/inst/V/vloxseg7ei64.v.yaml new file mode 100644 index 000000000..7fe0ced84 --- /dev/null +++ b/arch/inst/V/vloxseg7ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg7ei8.v.yaml b/arch/inst/V/vloxseg7ei8.v.yaml new file mode 100644 index 000000000..e1c2ead11 --- /dev/null +++ b/arch/inst/V/vloxseg7ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg8ei16.v.yaml b/arch/inst/V/vloxseg8ei16.v.yaml new file mode 100644 index 000000000..df6f5db25 --- /dev/null +++ b/arch/inst/V/vloxseg8ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg8ei32.v.yaml b/arch/inst/V/vloxseg8ei32.v.yaml new file mode 100644 index 000000000..195c6ea1a --- /dev/null +++ b/arch/inst/V/vloxseg8ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg8ei64.v.yaml b/arch/inst/V/vloxseg8ei64.v.yaml new file mode 100644 index 000000000..f2747cd5b --- /dev/null +++ b/arch/inst/V/vloxseg8ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vloxseg8ei8.v.yaml b/arch/inst/V/vloxseg8ei8.v.yaml new file mode 100644 index 000000000..f0d5ec5f7 --- /dev/null +++ b/arch/inst/V/vloxseg8ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e16.v.yaml b/arch/inst/V/vlseg2e16.v.yaml new file mode 100644 index 000000000..a2cab4bab --- /dev/null +++ b/arch/inst/V/vlseg2e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e16ff.v.yaml b/arch/inst/V/vlseg2e16ff.v.yaml new file mode 100644 index 000000000..a4014b189 --- /dev/null +++ b/arch/inst/V/vlseg2e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e32.v.yaml b/arch/inst/V/vlseg2e32.v.yaml new file mode 100644 index 000000000..e5d3ae3c0 --- /dev/null +++ b/arch/inst/V/vlseg2e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e32ff.v.yaml b/arch/inst/V/vlseg2e32ff.v.yaml new file mode 100644 index 000000000..815814027 --- /dev/null +++ b/arch/inst/V/vlseg2e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e64.v.yaml b/arch/inst/V/vlseg2e64.v.yaml new file mode 100644 index 000000000..bfacab114 --- /dev/null +++ b/arch/inst/V/vlseg2e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e64ff.v.yaml b/arch/inst/V/vlseg2e64ff.v.yaml new file mode 100644 index 000000000..ed5c70bbe --- /dev/null +++ b/arch/inst/V/vlseg2e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e8.v.yaml b/arch/inst/V/vlseg2e8.v.yaml new file mode 100644 index 000000000..734ecbca9 --- /dev/null +++ b/arch/inst/V/vlseg2e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg2e8ff.v.yaml b/arch/inst/V/vlseg2e8ff.v.yaml new file mode 100644 index 000000000..848b4e8f7 --- /dev/null +++ b/arch/inst/V/vlseg2e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 001000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e16.v.yaml b/arch/inst/V/vlseg3e16.v.yaml new file mode 100644 index 000000000..0a8c6870a --- /dev/null +++ b/arch/inst/V/vlseg3e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e16ff.v.yaml b/arch/inst/V/vlseg3e16ff.v.yaml new file mode 100644 index 000000000..44472d70e --- /dev/null +++ b/arch/inst/V/vlseg3e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e32.v.yaml b/arch/inst/V/vlseg3e32.v.yaml new file mode 100644 index 000000000..080f21018 --- /dev/null +++ b/arch/inst/V/vlseg3e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e32ff.v.yaml b/arch/inst/V/vlseg3e32ff.v.yaml new file mode 100644 index 000000000..08bc7cb9d --- /dev/null +++ b/arch/inst/V/vlseg3e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e64.v.yaml b/arch/inst/V/vlseg3e64.v.yaml new file mode 100644 index 000000000..a73c8cab7 --- /dev/null +++ b/arch/inst/V/vlseg3e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e64ff.v.yaml b/arch/inst/V/vlseg3e64ff.v.yaml new file mode 100644 index 000000000..f6a23acb4 --- /dev/null +++ b/arch/inst/V/vlseg3e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e8.v.yaml b/arch/inst/V/vlseg3e8.v.yaml new file mode 100644 index 000000000..4679966e0 --- /dev/null +++ b/arch/inst/V/vlseg3e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg3e8ff.v.yaml b/arch/inst/V/vlseg3e8ff.v.yaml new file mode 100644 index 000000000..0474c4bb9 --- /dev/null +++ b/arch/inst/V/vlseg3e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 010000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e16.v.yaml b/arch/inst/V/vlseg4e16.v.yaml new file mode 100644 index 000000000..ad493e689 --- /dev/null +++ b/arch/inst/V/vlseg4e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e16ff.v.yaml b/arch/inst/V/vlseg4e16ff.v.yaml new file mode 100644 index 000000000..31acfb5a8 --- /dev/null +++ b/arch/inst/V/vlseg4e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e32.v.yaml b/arch/inst/V/vlseg4e32.v.yaml new file mode 100644 index 000000000..ac08fa060 --- /dev/null +++ b/arch/inst/V/vlseg4e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e32ff.v.yaml b/arch/inst/V/vlseg4e32ff.v.yaml new file mode 100644 index 000000000..03a02f42e --- /dev/null +++ b/arch/inst/V/vlseg4e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e64.v.yaml b/arch/inst/V/vlseg4e64.v.yaml new file mode 100644 index 000000000..8915697f5 --- /dev/null +++ b/arch/inst/V/vlseg4e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e64ff.v.yaml b/arch/inst/V/vlseg4e64ff.v.yaml new file mode 100644 index 000000000..8190586ee --- /dev/null +++ b/arch/inst/V/vlseg4e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e8.v.yaml b/arch/inst/V/vlseg4e8.v.yaml new file mode 100644 index 000000000..91c8f4b8a --- /dev/null +++ b/arch/inst/V/vlseg4e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg4e8ff.v.yaml b/arch/inst/V/vlseg4e8ff.v.yaml new file mode 100644 index 000000000..df6e6831e --- /dev/null +++ b/arch/inst/V/vlseg4e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 011000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e16.v.yaml b/arch/inst/V/vlseg5e16.v.yaml new file mode 100644 index 000000000..30f713959 --- /dev/null +++ b/arch/inst/V/vlseg5e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e16ff.v.yaml b/arch/inst/V/vlseg5e16ff.v.yaml new file mode 100644 index 000000000..15c3a245a --- /dev/null +++ b/arch/inst/V/vlseg5e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e32.v.yaml b/arch/inst/V/vlseg5e32.v.yaml new file mode 100644 index 000000000..13966d00b --- /dev/null +++ b/arch/inst/V/vlseg5e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e32ff.v.yaml b/arch/inst/V/vlseg5e32ff.v.yaml new file mode 100644 index 000000000..5bae35876 --- /dev/null +++ b/arch/inst/V/vlseg5e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e64.v.yaml b/arch/inst/V/vlseg5e64.v.yaml new file mode 100644 index 000000000..d87028734 --- /dev/null +++ b/arch/inst/V/vlseg5e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e64ff.v.yaml b/arch/inst/V/vlseg5e64ff.v.yaml new file mode 100644 index 000000000..7be6eb177 --- /dev/null +++ b/arch/inst/V/vlseg5e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e8.v.yaml b/arch/inst/V/vlseg5e8.v.yaml new file mode 100644 index 000000000..b0ed00bd0 --- /dev/null +++ b/arch/inst/V/vlseg5e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg5e8ff.v.yaml b/arch/inst/V/vlseg5e8ff.v.yaml new file mode 100644 index 000000000..80e2df81a --- /dev/null +++ b/arch/inst/V/vlseg5e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 100000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e16.v.yaml b/arch/inst/V/vlseg6e16.v.yaml new file mode 100644 index 000000000..0c051a999 --- /dev/null +++ b/arch/inst/V/vlseg6e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e16ff.v.yaml b/arch/inst/V/vlseg6e16ff.v.yaml new file mode 100644 index 000000000..54cc9196b --- /dev/null +++ b/arch/inst/V/vlseg6e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e32.v.yaml b/arch/inst/V/vlseg6e32.v.yaml new file mode 100644 index 000000000..888a5c837 --- /dev/null +++ b/arch/inst/V/vlseg6e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e32ff.v.yaml b/arch/inst/V/vlseg6e32ff.v.yaml new file mode 100644 index 000000000..a0637baed --- /dev/null +++ b/arch/inst/V/vlseg6e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e64.v.yaml b/arch/inst/V/vlseg6e64.v.yaml new file mode 100644 index 000000000..602d9974a --- /dev/null +++ b/arch/inst/V/vlseg6e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e64ff.v.yaml b/arch/inst/V/vlseg6e64ff.v.yaml new file mode 100644 index 000000000..f2629c19e --- /dev/null +++ b/arch/inst/V/vlseg6e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e8.v.yaml b/arch/inst/V/vlseg6e8.v.yaml new file mode 100644 index 000000000..a0180b971 --- /dev/null +++ b/arch/inst/V/vlseg6e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg6e8ff.v.yaml b/arch/inst/V/vlseg6e8ff.v.yaml new file mode 100644 index 000000000..b56808326 --- /dev/null +++ b/arch/inst/V/vlseg6e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 101000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e16.v.yaml b/arch/inst/V/vlseg7e16.v.yaml new file mode 100644 index 000000000..5851806e6 --- /dev/null +++ b/arch/inst/V/vlseg7e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e16ff.v.yaml b/arch/inst/V/vlseg7e16ff.v.yaml new file mode 100644 index 000000000..20954ba6c --- /dev/null +++ b/arch/inst/V/vlseg7e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e32.v.yaml b/arch/inst/V/vlseg7e32.v.yaml new file mode 100644 index 000000000..1cf2c3373 --- /dev/null +++ b/arch/inst/V/vlseg7e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e32ff.v.yaml b/arch/inst/V/vlseg7e32ff.v.yaml new file mode 100644 index 000000000..e395b063e --- /dev/null +++ b/arch/inst/V/vlseg7e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e64.v.yaml b/arch/inst/V/vlseg7e64.v.yaml new file mode 100644 index 000000000..05e162830 --- /dev/null +++ b/arch/inst/V/vlseg7e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e64ff.v.yaml b/arch/inst/V/vlseg7e64ff.v.yaml new file mode 100644 index 000000000..565aacb90 --- /dev/null +++ b/arch/inst/V/vlseg7e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e8.v.yaml b/arch/inst/V/vlseg7e8.v.yaml new file mode 100644 index 000000000..21de27f84 --- /dev/null +++ b/arch/inst/V/vlseg7e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg7e8ff.v.yaml b/arch/inst/V/vlseg7e8ff.v.yaml new file mode 100644 index 000000000..8eec8031c --- /dev/null +++ b/arch/inst/V/vlseg7e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 110000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e16.v.yaml b/arch/inst/V/vlseg8e16.v.yaml new file mode 100644 index 000000000..ec175bb37 --- /dev/null +++ b/arch/inst/V/vlseg8e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e16ff.v.yaml b/arch/inst/V/vlseg8e16ff.v.yaml new file mode 100644 index 000000000..7a99d2402 --- /dev/null +++ b/arch/inst/V/vlseg8e16ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e16ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e32.v.yaml b/arch/inst/V/vlseg8e32.v.yaml new file mode 100644 index 000000000..79372ae84 --- /dev/null +++ b/arch/inst/V/vlseg8e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e32ff.v.yaml b/arch/inst/V/vlseg8e32ff.v.yaml new file mode 100644 index 000000000..9bd0906b5 --- /dev/null +++ b/arch/inst/V/vlseg8e32ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e32ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e64.v.yaml b/arch/inst/V/vlseg8e64.v.yaml new file mode 100644 index 000000000..ed5befa23 --- /dev/null +++ b/arch/inst/V/vlseg8e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e64ff.v.yaml b/arch/inst/V/vlseg8e64ff.v.yaml new file mode 100644 index 000000000..af4e15d51 --- /dev/null +++ b/arch/inst/V/vlseg8e64ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e64ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e8.v.yaml b/arch/inst/V/vlseg8e8.v.yaml new file mode 100644 index 000000000..e1937c9ac --- /dev/null +++ b/arch/inst/V/vlseg8e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlseg8e8ff.v.yaml b/arch/inst/V/vlseg8e8ff.v.yaml new file mode 100644 index 000000000..cb825c00e --- /dev/null +++ b/arch/inst/V/vlseg8e8ff.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e8ff.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vd +encoding: + match: 111000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg2e16.v.yaml b/arch/inst/V/vlsseg2e16.v.yaml new file mode 100644 index 000000000..691eb363b --- /dev/null +++ b/arch/inst/V/vlsseg2e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 001010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg2e32.v.yaml b/arch/inst/V/vlsseg2e32.v.yaml new file mode 100644 index 000000000..8f89e7887 --- /dev/null +++ b/arch/inst/V/vlsseg2e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 001010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg2e64.v.yaml b/arch/inst/V/vlsseg2e64.v.yaml new file mode 100644 index 000000000..fdce27802 --- /dev/null +++ b/arch/inst/V/vlsseg2e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 001010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg2e8.v.yaml b/arch/inst/V/vlsseg2e8.v.yaml new file mode 100644 index 000000000..7edea0e2a --- /dev/null +++ b/arch/inst/V/vlsseg2e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 001010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg3e16.v.yaml b/arch/inst/V/vlsseg3e16.v.yaml new file mode 100644 index 000000000..7f381ef3b --- /dev/null +++ b/arch/inst/V/vlsseg3e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 010010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg3e32.v.yaml b/arch/inst/V/vlsseg3e32.v.yaml new file mode 100644 index 000000000..ecb434806 --- /dev/null +++ b/arch/inst/V/vlsseg3e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 010010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg3e64.v.yaml b/arch/inst/V/vlsseg3e64.v.yaml new file mode 100644 index 000000000..94d3ad2f3 --- /dev/null +++ b/arch/inst/V/vlsseg3e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 010010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg3e8.v.yaml b/arch/inst/V/vlsseg3e8.v.yaml new file mode 100644 index 000000000..e9569dba2 --- /dev/null +++ b/arch/inst/V/vlsseg3e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 010010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg4e16.v.yaml b/arch/inst/V/vlsseg4e16.v.yaml new file mode 100644 index 000000000..3bb9ee4a7 --- /dev/null +++ b/arch/inst/V/vlsseg4e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 011010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg4e32.v.yaml b/arch/inst/V/vlsseg4e32.v.yaml new file mode 100644 index 000000000..e63f5c9e2 --- /dev/null +++ b/arch/inst/V/vlsseg4e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 011010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg4e64.v.yaml b/arch/inst/V/vlsseg4e64.v.yaml new file mode 100644 index 000000000..66f4af48a --- /dev/null +++ b/arch/inst/V/vlsseg4e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 011010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg4e8.v.yaml b/arch/inst/V/vlsseg4e8.v.yaml new file mode 100644 index 000000000..6e213656e --- /dev/null +++ b/arch/inst/V/vlsseg4e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 011010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg5e16.v.yaml b/arch/inst/V/vlsseg5e16.v.yaml new file mode 100644 index 000000000..9276507db --- /dev/null +++ b/arch/inst/V/vlsseg5e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 100010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg5e32.v.yaml b/arch/inst/V/vlsseg5e32.v.yaml new file mode 100644 index 000000000..2b41e5682 --- /dev/null +++ b/arch/inst/V/vlsseg5e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 100010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg5e64.v.yaml b/arch/inst/V/vlsseg5e64.v.yaml new file mode 100644 index 000000000..de46f05e9 --- /dev/null +++ b/arch/inst/V/vlsseg5e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 100010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg5e8.v.yaml b/arch/inst/V/vlsseg5e8.v.yaml new file mode 100644 index 000000000..c69373c6b --- /dev/null +++ b/arch/inst/V/vlsseg5e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 100010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg6e16.v.yaml b/arch/inst/V/vlsseg6e16.v.yaml new file mode 100644 index 000000000..f3773952c --- /dev/null +++ b/arch/inst/V/vlsseg6e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 101010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg6e32.v.yaml b/arch/inst/V/vlsseg6e32.v.yaml new file mode 100644 index 000000000..b610b0ff5 --- /dev/null +++ b/arch/inst/V/vlsseg6e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 101010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg6e64.v.yaml b/arch/inst/V/vlsseg6e64.v.yaml new file mode 100644 index 000000000..2db70cc53 --- /dev/null +++ b/arch/inst/V/vlsseg6e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 101010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg6e8.v.yaml b/arch/inst/V/vlsseg6e8.v.yaml new file mode 100644 index 000000000..0b849f331 --- /dev/null +++ b/arch/inst/V/vlsseg6e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 101010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg7e16.v.yaml b/arch/inst/V/vlsseg7e16.v.yaml new file mode 100644 index 000000000..ced663fe5 --- /dev/null +++ b/arch/inst/V/vlsseg7e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 110010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg7e32.v.yaml b/arch/inst/V/vlsseg7e32.v.yaml new file mode 100644 index 000000000..3b8367b12 --- /dev/null +++ b/arch/inst/V/vlsseg7e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 110010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg7e64.v.yaml b/arch/inst/V/vlsseg7e64.v.yaml new file mode 100644 index 000000000..658ed6a20 --- /dev/null +++ b/arch/inst/V/vlsseg7e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 110010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg7e8.v.yaml b/arch/inst/V/vlsseg7e8.v.yaml new file mode 100644 index 000000000..1884be49c --- /dev/null +++ b/arch/inst/V/vlsseg7e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 110010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg8e16.v.yaml b/arch/inst/V/vlsseg8e16.v.yaml new file mode 100644 index 000000000..3f9c32777 --- /dev/null +++ b/arch/inst/V/vlsseg8e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 111010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg8e32.v.yaml b/arch/inst/V/vlsseg8e32.v.yaml new file mode 100644 index 000000000..895b19938 --- /dev/null +++ b/arch/inst/V/vlsseg8e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 111010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg8e64.v.yaml b/arch/inst/V/vlsseg8e64.v.yaml new file mode 100644 index 000000000..74fbb37b1 --- /dev/null +++ b/arch/inst/V/vlsseg8e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 111010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vlsseg8e8.v.yaml b/arch/inst/V/vlsseg8e8.v.yaml new file mode 100644 index 000000000..a04abb0a9 --- /dev/null +++ b/arch/inst/V/vlsseg8e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vd +encoding: + match: 111010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg2ei16.v.yaml b/arch/inst/V/vluxseg2ei16.v.yaml new file mode 100644 index 000000000..0cedd4919 --- /dev/null +++ b/arch/inst/V/vluxseg2ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg2ei32.v.yaml b/arch/inst/V/vluxseg2ei32.v.yaml new file mode 100644 index 000000000..248a6014d --- /dev/null +++ b/arch/inst/V/vluxseg2ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg2ei64.v.yaml b/arch/inst/V/vluxseg2ei64.v.yaml new file mode 100644 index 000000000..aa44de53f --- /dev/null +++ b/arch/inst/V/vluxseg2ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg2ei8.v.yaml b/arch/inst/V/vluxseg2ei8.v.yaml new file mode 100644 index 000000000..47d086f24 --- /dev/null +++ b/arch/inst/V/vluxseg2ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 001001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg3ei16.v.yaml b/arch/inst/V/vluxseg3ei16.v.yaml new file mode 100644 index 000000000..63ead2f0b --- /dev/null +++ b/arch/inst/V/vluxseg3ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg3ei32.v.yaml b/arch/inst/V/vluxseg3ei32.v.yaml new file mode 100644 index 000000000..093273266 --- /dev/null +++ b/arch/inst/V/vluxseg3ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg3ei64.v.yaml b/arch/inst/V/vluxseg3ei64.v.yaml new file mode 100644 index 000000000..b5b036c66 --- /dev/null +++ b/arch/inst/V/vluxseg3ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg3ei8.v.yaml b/arch/inst/V/vluxseg3ei8.v.yaml new file mode 100644 index 000000000..d12058ae9 --- /dev/null +++ b/arch/inst/V/vluxseg3ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 010001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg4ei16.v.yaml b/arch/inst/V/vluxseg4ei16.v.yaml new file mode 100644 index 000000000..868d2bbe2 --- /dev/null +++ b/arch/inst/V/vluxseg4ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg4ei32.v.yaml b/arch/inst/V/vluxseg4ei32.v.yaml new file mode 100644 index 000000000..ebcbe075b --- /dev/null +++ b/arch/inst/V/vluxseg4ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg4ei64.v.yaml b/arch/inst/V/vluxseg4ei64.v.yaml new file mode 100644 index 000000000..91c3d60c5 --- /dev/null +++ b/arch/inst/V/vluxseg4ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg4ei8.v.yaml b/arch/inst/V/vluxseg4ei8.v.yaml new file mode 100644 index 000000000..fe4afd3e9 --- /dev/null +++ b/arch/inst/V/vluxseg4ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 011001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg5ei16.v.yaml b/arch/inst/V/vluxseg5ei16.v.yaml new file mode 100644 index 000000000..4a8948b02 --- /dev/null +++ b/arch/inst/V/vluxseg5ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg5ei32.v.yaml b/arch/inst/V/vluxseg5ei32.v.yaml new file mode 100644 index 000000000..c061b297a --- /dev/null +++ b/arch/inst/V/vluxseg5ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg5ei64.v.yaml b/arch/inst/V/vluxseg5ei64.v.yaml new file mode 100644 index 000000000..6cc02268a --- /dev/null +++ b/arch/inst/V/vluxseg5ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg5ei8.v.yaml b/arch/inst/V/vluxseg5ei8.v.yaml new file mode 100644 index 000000000..29c178c47 --- /dev/null +++ b/arch/inst/V/vluxseg5ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 100001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg6ei16.v.yaml b/arch/inst/V/vluxseg6ei16.v.yaml new file mode 100644 index 000000000..4d652a37f --- /dev/null +++ b/arch/inst/V/vluxseg6ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg6ei32.v.yaml b/arch/inst/V/vluxseg6ei32.v.yaml new file mode 100644 index 000000000..84ba75c8d --- /dev/null +++ b/arch/inst/V/vluxseg6ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg6ei64.v.yaml b/arch/inst/V/vluxseg6ei64.v.yaml new file mode 100644 index 000000000..69446e214 --- /dev/null +++ b/arch/inst/V/vluxseg6ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg6ei8.v.yaml b/arch/inst/V/vluxseg6ei8.v.yaml new file mode 100644 index 000000000..599231bca --- /dev/null +++ b/arch/inst/V/vluxseg6ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 101001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg7ei16.v.yaml b/arch/inst/V/vluxseg7ei16.v.yaml new file mode 100644 index 000000000..8bc62c8fa --- /dev/null +++ b/arch/inst/V/vluxseg7ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg7ei32.v.yaml b/arch/inst/V/vluxseg7ei32.v.yaml new file mode 100644 index 000000000..39b46639d --- /dev/null +++ b/arch/inst/V/vluxseg7ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg7ei64.v.yaml b/arch/inst/V/vluxseg7ei64.v.yaml new file mode 100644 index 000000000..83c4e97dd --- /dev/null +++ b/arch/inst/V/vluxseg7ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg7ei8.v.yaml b/arch/inst/V/vluxseg7ei8.v.yaml new file mode 100644 index 000000000..aebfab4e8 --- /dev/null +++ b/arch/inst/V/vluxseg7ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 110001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg8ei16.v.yaml b/arch/inst/V/vluxseg8ei16.v.yaml new file mode 100644 index 000000000..644010288 --- /dev/null +++ b/arch/inst/V/vluxseg8ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg8ei32.v.yaml b/arch/inst/V/vluxseg8ei32.v.yaml new file mode 100644 index 000000000..68b490bee --- /dev/null +++ b/arch/inst/V/vluxseg8ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg8ei64.v.yaml b/arch/inst/V/vluxseg8ei64.v.yaml new file mode 100644 index 000000000..d1b1bc738 --- /dev/null +++ b/arch/inst/V/vluxseg8ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vluxseg8ei8.v.yaml b/arch/inst/V/vluxseg8ei8.v.yaml new file mode 100644 index 000000000..2cce23a75 --- /dev/null +++ b/arch/inst/V/vluxseg8ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vd +encoding: + match: 111001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg2ei16.v.yaml b/arch/inst/V/vsoxseg2ei16.v.yaml new file mode 100644 index 000000000..ac714ab24 --- /dev/null +++ b/arch/inst/V/vsoxseg2ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg2ei32.v.yaml b/arch/inst/V/vsoxseg2ei32.v.yaml new file mode 100644 index 000000000..28784077e --- /dev/null +++ b/arch/inst/V/vsoxseg2ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg2ei64.v.yaml b/arch/inst/V/vsoxseg2ei64.v.yaml new file mode 100644 index 000000000..5ff3e3093 --- /dev/null +++ b/arch/inst/V/vsoxseg2ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg2ei8.v.yaml b/arch/inst/V/vsoxseg2ei8.v.yaml new file mode 100644 index 000000000..f1e6c2b46 --- /dev/null +++ b/arch/inst/V/vsoxseg2ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg3ei16.v.yaml b/arch/inst/V/vsoxseg3ei16.v.yaml new file mode 100644 index 000000000..779e5b3ff --- /dev/null +++ b/arch/inst/V/vsoxseg3ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg3ei32.v.yaml b/arch/inst/V/vsoxseg3ei32.v.yaml new file mode 100644 index 000000000..ea66ccc72 --- /dev/null +++ b/arch/inst/V/vsoxseg3ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg3ei64.v.yaml b/arch/inst/V/vsoxseg3ei64.v.yaml new file mode 100644 index 000000000..bfd680779 --- /dev/null +++ b/arch/inst/V/vsoxseg3ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg3ei8.v.yaml b/arch/inst/V/vsoxseg3ei8.v.yaml new file mode 100644 index 000000000..f2ed7f223 --- /dev/null +++ b/arch/inst/V/vsoxseg3ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg4ei16.v.yaml b/arch/inst/V/vsoxseg4ei16.v.yaml new file mode 100644 index 000000000..5621b133a --- /dev/null +++ b/arch/inst/V/vsoxseg4ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg4ei32.v.yaml b/arch/inst/V/vsoxseg4ei32.v.yaml new file mode 100644 index 000000000..16968f060 --- /dev/null +++ b/arch/inst/V/vsoxseg4ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg4ei64.v.yaml b/arch/inst/V/vsoxseg4ei64.v.yaml new file mode 100644 index 000000000..04f00844d --- /dev/null +++ b/arch/inst/V/vsoxseg4ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg4ei8.v.yaml b/arch/inst/V/vsoxseg4ei8.v.yaml new file mode 100644 index 000000000..eff793012 --- /dev/null +++ b/arch/inst/V/vsoxseg4ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg5ei16.v.yaml b/arch/inst/V/vsoxseg5ei16.v.yaml new file mode 100644 index 000000000..3b5d82c7e --- /dev/null +++ b/arch/inst/V/vsoxseg5ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg5ei32.v.yaml b/arch/inst/V/vsoxseg5ei32.v.yaml new file mode 100644 index 000000000..6956fd4b8 --- /dev/null +++ b/arch/inst/V/vsoxseg5ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg5ei64.v.yaml b/arch/inst/V/vsoxseg5ei64.v.yaml new file mode 100644 index 000000000..ad4248d04 --- /dev/null +++ b/arch/inst/V/vsoxseg5ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg5ei8.v.yaml b/arch/inst/V/vsoxseg5ei8.v.yaml new file mode 100644 index 000000000..d0aec1c02 --- /dev/null +++ b/arch/inst/V/vsoxseg5ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg6ei16.v.yaml b/arch/inst/V/vsoxseg6ei16.v.yaml new file mode 100644 index 000000000..28ee6c458 --- /dev/null +++ b/arch/inst/V/vsoxseg6ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg6ei32.v.yaml b/arch/inst/V/vsoxseg6ei32.v.yaml new file mode 100644 index 000000000..c5ba2071a --- /dev/null +++ b/arch/inst/V/vsoxseg6ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg6ei64.v.yaml b/arch/inst/V/vsoxseg6ei64.v.yaml new file mode 100644 index 000000000..0b10f9133 --- /dev/null +++ b/arch/inst/V/vsoxseg6ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg6ei8.v.yaml b/arch/inst/V/vsoxseg6ei8.v.yaml new file mode 100644 index 000000000..17d875acc --- /dev/null +++ b/arch/inst/V/vsoxseg6ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg7ei16.v.yaml b/arch/inst/V/vsoxseg7ei16.v.yaml new file mode 100644 index 000000000..0206c3b38 --- /dev/null +++ b/arch/inst/V/vsoxseg7ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg7ei32.v.yaml b/arch/inst/V/vsoxseg7ei32.v.yaml new file mode 100644 index 000000000..5e338157e --- /dev/null +++ b/arch/inst/V/vsoxseg7ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg7ei64.v.yaml b/arch/inst/V/vsoxseg7ei64.v.yaml new file mode 100644 index 000000000..c0e2ef20d --- /dev/null +++ b/arch/inst/V/vsoxseg7ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg7ei8.v.yaml b/arch/inst/V/vsoxseg7ei8.v.yaml new file mode 100644 index 000000000..b12c9a079 --- /dev/null +++ b/arch/inst/V/vsoxseg7ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg8ei16.v.yaml b/arch/inst/V/vsoxseg8ei16.v.yaml new file mode 100644 index 000000000..9dc37142d --- /dev/null +++ b/arch/inst/V/vsoxseg8ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg8ei32.v.yaml b/arch/inst/V/vsoxseg8ei32.v.yaml new file mode 100644 index 000000000..4aa50321d --- /dev/null +++ b/arch/inst/V/vsoxseg8ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg8ei64.v.yaml b/arch/inst/V/vsoxseg8ei64.v.yaml new file mode 100644 index 000000000..404ff34a7 --- /dev/null +++ b/arch/inst/V/vsoxseg8ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsoxseg8ei8.v.yaml b/arch/inst/V/vsoxseg8ei8.v.yaml new file mode 100644 index 000000000..e27be1e85 --- /dev/null +++ b/arch/inst/V/vsoxseg8ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg2e16.v.yaml b/arch/inst/V/vsseg2e16.v.yaml new file mode 100644 index 000000000..6fcf05567 --- /dev/null +++ b/arch/inst/V/vsseg2e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 001000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg2e32.v.yaml b/arch/inst/V/vsseg2e32.v.yaml new file mode 100644 index 000000000..857a1c32c --- /dev/null +++ b/arch/inst/V/vsseg2e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 001000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg2e64.v.yaml b/arch/inst/V/vsseg2e64.v.yaml new file mode 100644 index 000000000..ed0d637b3 --- /dev/null +++ b/arch/inst/V/vsseg2e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 001000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg2e8.v.yaml b/arch/inst/V/vsseg2e8.v.yaml new file mode 100644 index 000000000..6e6b74761 --- /dev/null +++ b/arch/inst/V/vsseg2e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 001000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg3e16.v.yaml b/arch/inst/V/vsseg3e16.v.yaml new file mode 100644 index 000000000..9c6596610 --- /dev/null +++ b/arch/inst/V/vsseg3e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 010000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg3e32.v.yaml b/arch/inst/V/vsseg3e32.v.yaml new file mode 100644 index 000000000..d67eeb0eb --- /dev/null +++ b/arch/inst/V/vsseg3e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 010000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg3e64.v.yaml b/arch/inst/V/vsseg3e64.v.yaml new file mode 100644 index 000000000..4d0506f00 --- /dev/null +++ b/arch/inst/V/vsseg3e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 010000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg3e8.v.yaml b/arch/inst/V/vsseg3e8.v.yaml new file mode 100644 index 000000000..b2c604e67 --- /dev/null +++ b/arch/inst/V/vsseg3e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 010000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg4e16.v.yaml b/arch/inst/V/vsseg4e16.v.yaml new file mode 100644 index 000000000..aaa25044d --- /dev/null +++ b/arch/inst/V/vsseg4e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 011000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg4e32.v.yaml b/arch/inst/V/vsseg4e32.v.yaml new file mode 100644 index 000000000..b1c3ca1a9 --- /dev/null +++ b/arch/inst/V/vsseg4e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 011000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg4e64.v.yaml b/arch/inst/V/vsseg4e64.v.yaml new file mode 100644 index 000000000..d15d70a4f --- /dev/null +++ b/arch/inst/V/vsseg4e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 011000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg4e8.v.yaml b/arch/inst/V/vsseg4e8.v.yaml new file mode 100644 index 000000000..2daa99250 --- /dev/null +++ b/arch/inst/V/vsseg4e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 011000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg5e16.v.yaml b/arch/inst/V/vsseg5e16.v.yaml new file mode 100644 index 000000000..cc5f8611f --- /dev/null +++ b/arch/inst/V/vsseg5e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 100000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg5e32.v.yaml b/arch/inst/V/vsseg5e32.v.yaml new file mode 100644 index 000000000..a9e9df1c0 --- /dev/null +++ b/arch/inst/V/vsseg5e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 100000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg5e64.v.yaml b/arch/inst/V/vsseg5e64.v.yaml new file mode 100644 index 000000000..7f43ce73e --- /dev/null +++ b/arch/inst/V/vsseg5e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 100000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg5e8.v.yaml b/arch/inst/V/vsseg5e8.v.yaml new file mode 100644 index 000000000..aa3a30a97 --- /dev/null +++ b/arch/inst/V/vsseg5e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 100000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg6e16.v.yaml b/arch/inst/V/vsseg6e16.v.yaml new file mode 100644 index 000000000..a4b52768a --- /dev/null +++ b/arch/inst/V/vsseg6e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 101000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg6e32.v.yaml b/arch/inst/V/vsseg6e32.v.yaml new file mode 100644 index 000000000..c52e48bd0 --- /dev/null +++ b/arch/inst/V/vsseg6e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 101000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg6e64.v.yaml b/arch/inst/V/vsseg6e64.v.yaml new file mode 100644 index 000000000..3b8da0914 --- /dev/null +++ b/arch/inst/V/vsseg6e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 101000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg6e8.v.yaml b/arch/inst/V/vsseg6e8.v.yaml new file mode 100644 index 000000000..b9ba9d472 --- /dev/null +++ b/arch/inst/V/vsseg6e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 101000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg7e16.v.yaml b/arch/inst/V/vsseg7e16.v.yaml new file mode 100644 index 000000000..9c10d52f6 --- /dev/null +++ b/arch/inst/V/vsseg7e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 110000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg7e32.v.yaml b/arch/inst/V/vsseg7e32.v.yaml new file mode 100644 index 000000000..7167a70dc --- /dev/null +++ b/arch/inst/V/vsseg7e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 110000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg7e64.v.yaml b/arch/inst/V/vsseg7e64.v.yaml new file mode 100644 index 000000000..6872cf1e3 --- /dev/null +++ b/arch/inst/V/vsseg7e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 110000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg7e8.v.yaml b/arch/inst/V/vsseg7e8.v.yaml new file mode 100644 index 000000000..30772c55b --- /dev/null +++ b/arch/inst/V/vsseg7e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 110000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg8e16.v.yaml b/arch/inst/V/vsseg8e16.v.yaml new file mode 100644 index 000000000..84a60a143 --- /dev/null +++ b/arch/inst/V/vsseg8e16.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 111000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg8e32.v.yaml b/arch/inst/V/vsseg8e32.v.yaml new file mode 100644 index 000000000..82924389f --- /dev/null +++ b/arch/inst/V/vsseg8e32.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 111000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg8e64.v.yaml b/arch/inst/V/vsseg8e64.v.yaml new file mode 100644 index 000000000..84df8f104 --- /dev/null +++ b/arch/inst/V/vsseg8e64.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 111000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsseg8e8.v.yaml b/arch/inst/V/vsseg8e8.v.yaml new file mode 100644 index 000000000..86947bdb8 --- /dev/null +++ b/arch/inst/V/vsseg8e8.v.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs1, vs3 +encoding: + match: 111000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg2e16.v.yaml b/arch/inst/V/vssseg2e16.v.yaml new file mode 100644 index 000000000..3b1e6560c --- /dev/null +++ b/arch/inst/V/vssseg2e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 001010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg2e32.v.yaml b/arch/inst/V/vssseg2e32.v.yaml new file mode 100644 index 000000000..068297931 --- /dev/null +++ b/arch/inst/V/vssseg2e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 001010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg2e64.v.yaml b/arch/inst/V/vssseg2e64.v.yaml new file mode 100644 index 000000000..17af81de8 --- /dev/null +++ b/arch/inst/V/vssseg2e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 001010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg2e8.v.yaml b/arch/inst/V/vssseg2e8.v.yaml new file mode 100644 index 000000000..3f0c872a9 --- /dev/null +++ b/arch/inst/V/vssseg2e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 001010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg3e16.v.yaml b/arch/inst/V/vssseg3e16.v.yaml new file mode 100644 index 000000000..a2be5743f --- /dev/null +++ b/arch/inst/V/vssseg3e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 010010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg3e32.v.yaml b/arch/inst/V/vssseg3e32.v.yaml new file mode 100644 index 000000000..c23e342ee --- /dev/null +++ b/arch/inst/V/vssseg3e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 010010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg3e64.v.yaml b/arch/inst/V/vssseg3e64.v.yaml new file mode 100644 index 000000000..e42be34ad --- /dev/null +++ b/arch/inst/V/vssseg3e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 010010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg3e8.v.yaml b/arch/inst/V/vssseg3e8.v.yaml new file mode 100644 index 000000000..5ba1cabdd --- /dev/null +++ b/arch/inst/V/vssseg3e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 010010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg4e16.v.yaml b/arch/inst/V/vssseg4e16.v.yaml new file mode 100644 index 000000000..2dcf2c097 --- /dev/null +++ b/arch/inst/V/vssseg4e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 011010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg4e32.v.yaml b/arch/inst/V/vssseg4e32.v.yaml new file mode 100644 index 000000000..9152f5384 --- /dev/null +++ b/arch/inst/V/vssseg4e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 011010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg4e64.v.yaml b/arch/inst/V/vssseg4e64.v.yaml new file mode 100644 index 000000000..4f109fc9a --- /dev/null +++ b/arch/inst/V/vssseg4e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 011010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg4e8.v.yaml b/arch/inst/V/vssseg4e8.v.yaml new file mode 100644 index 000000000..73145dbdb --- /dev/null +++ b/arch/inst/V/vssseg4e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 011010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg5e16.v.yaml b/arch/inst/V/vssseg5e16.v.yaml new file mode 100644 index 000000000..e050b894f --- /dev/null +++ b/arch/inst/V/vssseg5e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 100010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg5e32.v.yaml b/arch/inst/V/vssseg5e32.v.yaml new file mode 100644 index 000000000..c380333f8 --- /dev/null +++ b/arch/inst/V/vssseg5e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 100010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg5e64.v.yaml b/arch/inst/V/vssseg5e64.v.yaml new file mode 100644 index 000000000..9c0013b3f --- /dev/null +++ b/arch/inst/V/vssseg5e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 100010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg5e8.v.yaml b/arch/inst/V/vssseg5e8.v.yaml new file mode 100644 index 000000000..368b767df --- /dev/null +++ b/arch/inst/V/vssseg5e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 100010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg6e16.v.yaml b/arch/inst/V/vssseg6e16.v.yaml new file mode 100644 index 000000000..88d3e887d --- /dev/null +++ b/arch/inst/V/vssseg6e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 101010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg6e32.v.yaml b/arch/inst/V/vssseg6e32.v.yaml new file mode 100644 index 000000000..443a44bb6 --- /dev/null +++ b/arch/inst/V/vssseg6e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 101010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg6e64.v.yaml b/arch/inst/V/vssseg6e64.v.yaml new file mode 100644 index 000000000..316883eff --- /dev/null +++ b/arch/inst/V/vssseg6e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 101010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg6e8.v.yaml b/arch/inst/V/vssseg6e8.v.yaml new file mode 100644 index 000000000..6421447d9 --- /dev/null +++ b/arch/inst/V/vssseg6e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 101010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg7e16.v.yaml b/arch/inst/V/vssseg7e16.v.yaml new file mode 100644 index 000000000..377909800 --- /dev/null +++ b/arch/inst/V/vssseg7e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 110010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg7e32.v.yaml b/arch/inst/V/vssseg7e32.v.yaml new file mode 100644 index 000000000..faaa0b21d --- /dev/null +++ b/arch/inst/V/vssseg7e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 110010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg7e64.v.yaml b/arch/inst/V/vssseg7e64.v.yaml new file mode 100644 index 000000000..5721de1cc --- /dev/null +++ b/arch/inst/V/vssseg7e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 110010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg7e8.v.yaml b/arch/inst/V/vssseg7e8.v.yaml new file mode 100644 index 000000000..466148402 --- /dev/null +++ b/arch/inst/V/vssseg7e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 110010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg8e16.v.yaml b/arch/inst/V/vssseg8e16.v.yaml new file mode 100644 index 000000000..fe68e03f6 --- /dev/null +++ b/arch/inst/V/vssseg8e16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 111010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg8e32.v.yaml b/arch/inst/V/vssseg8e32.v.yaml new file mode 100644 index 000000000..41ced6eef --- /dev/null +++ b/arch/inst/V/vssseg8e32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 111010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg8e64.v.yaml b/arch/inst/V/vssseg8e64.v.yaml new file mode 100644 index 000000000..3792410a3 --- /dev/null +++ b/arch/inst/V/vssseg8e64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 111010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vssseg8e8.v.yaml b/arch/inst/V/vssseg8e8.v.yaml new file mode 100644 index 000000000..c938f6444 --- /dev/null +++ b/arch/inst/V/vssseg8e8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, xs2, xs1, vs3 +encoding: + match: 111010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg2ei16.v.yaml b/arch/inst/V/vsuxseg2ei16.v.yaml new file mode 100644 index 000000000..c87cde860 --- /dev/null +++ b/arch/inst/V/vsuxseg2ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg2ei32.v.yaml b/arch/inst/V/vsuxseg2ei32.v.yaml new file mode 100644 index 000000000..6a4aabb4d --- /dev/null +++ b/arch/inst/V/vsuxseg2ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg2ei64.v.yaml b/arch/inst/V/vsuxseg2ei64.v.yaml new file mode 100644 index 000000000..5e08c3e73 --- /dev/null +++ b/arch/inst/V/vsuxseg2ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg2ei8.v.yaml b/arch/inst/V/vsuxseg2ei8.v.yaml new file mode 100644 index 000000000..de8bb5551 --- /dev/null +++ b/arch/inst/V/vsuxseg2ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 001001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg3ei16.v.yaml b/arch/inst/V/vsuxseg3ei16.v.yaml new file mode 100644 index 000000000..160f074ea --- /dev/null +++ b/arch/inst/V/vsuxseg3ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg3ei32.v.yaml b/arch/inst/V/vsuxseg3ei32.v.yaml new file mode 100644 index 000000000..3c951c9c2 --- /dev/null +++ b/arch/inst/V/vsuxseg3ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg3ei64.v.yaml b/arch/inst/V/vsuxseg3ei64.v.yaml new file mode 100644 index 000000000..44e633dfd --- /dev/null +++ b/arch/inst/V/vsuxseg3ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg3ei8.v.yaml b/arch/inst/V/vsuxseg3ei8.v.yaml new file mode 100644 index 000000000..d4131bea1 --- /dev/null +++ b/arch/inst/V/vsuxseg3ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 010001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg4ei16.v.yaml b/arch/inst/V/vsuxseg4ei16.v.yaml new file mode 100644 index 000000000..5a2391424 --- /dev/null +++ b/arch/inst/V/vsuxseg4ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg4ei32.v.yaml b/arch/inst/V/vsuxseg4ei32.v.yaml new file mode 100644 index 000000000..de1b0e820 --- /dev/null +++ b/arch/inst/V/vsuxseg4ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg4ei64.v.yaml b/arch/inst/V/vsuxseg4ei64.v.yaml new file mode 100644 index 000000000..c1c358f12 --- /dev/null +++ b/arch/inst/V/vsuxseg4ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg4ei8.v.yaml b/arch/inst/V/vsuxseg4ei8.v.yaml new file mode 100644 index 000000000..a69f3e9e4 --- /dev/null +++ b/arch/inst/V/vsuxseg4ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 011001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg5ei16.v.yaml b/arch/inst/V/vsuxseg5ei16.v.yaml new file mode 100644 index 000000000..d151e28a4 --- /dev/null +++ b/arch/inst/V/vsuxseg5ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg5ei32.v.yaml b/arch/inst/V/vsuxseg5ei32.v.yaml new file mode 100644 index 000000000..81abe68b2 --- /dev/null +++ b/arch/inst/V/vsuxseg5ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg5ei64.v.yaml b/arch/inst/V/vsuxseg5ei64.v.yaml new file mode 100644 index 000000000..266d10512 --- /dev/null +++ b/arch/inst/V/vsuxseg5ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg5ei8.v.yaml b/arch/inst/V/vsuxseg5ei8.v.yaml new file mode 100644 index 000000000..522b019a4 --- /dev/null +++ b/arch/inst/V/vsuxseg5ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 100001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg6ei16.v.yaml b/arch/inst/V/vsuxseg6ei16.v.yaml new file mode 100644 index 000000000..2d29c3d2d --- /dev/null +++ b/arch/inst/V/vsuxseg6ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg6ei32.v.yaml b/arch/inst/V/vsuxseg6ei32.v.yaml new file mode 100644 index 000000000..3f52d6f71 --- /dev/null +++ b/arch/inst/V/vsuxseg6ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg6ei64.v.yaml b/arch/inst/V/vsuxseg6ei64.v.yaml new file mode 100644 index 000000000..9da3f96c5 --- /dev/null +++ b/arch/inst/V/vsuxseg6ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg6ei8.v.yaml b/arch/inst/V/vsuxseg6ei8.v.yaml new file mode 100644 index 000000000..a2d74f76c --- /dev/null +++ b/arch/inst/V/vsuxseg6ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 101001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg7ei16.v.yaml b/arch/inst/V/vsuxseg7ei16.v.yaml new file mode 100644 index 000000000..aaf2ae980 --- /dev/null +++ b/arch/inst/V/vsuxseg7ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg7ei32.v.yaml b/arch/inst/V/vsuxseg7ei32.v.yaml new file mode 100644 index 000000000..0aa35c109 --- /dev/null +++ b/arch/inst/V/vsuxseg7ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg7ei64.v.yaml b/arch/inst/V/vsuxseg7ei64.v.yaml new file mode 100644 index 000000000..da607c1c3 --- /dev/null +++ b/arch/inst/V/vsuxseg7ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg7ei8.v.yaml b/arch/inst/V/vsuxseg7ei8.v.yaml new file mode 100644 index 000000000..003994175 --- /dev/null +++ b/arch/inst/V/vsuxseg7ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 110001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg8ei16.v.yaml b/arch/inst/V/vsuxseg8ei16.v.yaml new file mode 100644 index 000000000..d9894ceb2 --- /dev/null +++ b/arch/inst/V/vsuxseg8ei16.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei16.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg8ei32.v.yaml b/arch/inst/V/vsuxseg8ei32.v.yaml new file mode 100644 index 000000000..bfbe6a963 --- /dev/null +++ b/arch/inst/V/vsuxseg8ei32.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei32.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg8ei64.v.yaml b/arch/inst/V/vsuxseg8ei64.v.yaml new file mode 100644 index 000000000..c7e171677 --- /dev/null +++ b/arch/inst/V/vsuxseg8ei64.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei64.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + diff --git a/arch/inst/V/vsuxseg8ei8.v.yaml b/arch/inst/V/vsuxseg8ei8.v.yaml new file mode 100644 index 000000000..225b9ce8b --- /dev/null +++ b/arch/inst/V/vsuxseg8ei8.v.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei8.v +long_name: No synopsis available. +description: | + No description available. +definedBy: V +assembly: vm, vs2, xs1, vs3 +encoding: + match: 111001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + From 69d381d3faccaae875e82b14e18409618ecac834 Mon Sep 17 00:00:00 2001 From: "Paul A. Clarke" Date: Wed, 27 Nov 2024 14:49:05 -0600 Subject: [PATCH 06/11] Fix spelling of "specific" in a few places --- arch/csr/H/htinst.yaml | 2 +- arch/csr/H/htval.yaml | 2 +- arch/csr/H/mtinst.yaml | 2 +- arch/csr/H/mtval2.yaml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/csr/H/htinst.yaml b/arch/csr/H/htinst.yaml index 770bb92ec..f4a9df9e4 100644 --- a/arch/csr/H/htinst.yaml +++ b/arch/csr/H/htinst.yaml @@ -40,5 +40,5 @@ fields: return CsrFieldType::RO; } description: | - Exception-speicific information for a trap into HS-mode. + Exception-specific information for a trap into HS-mode. reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/H/htval.yaml b/arch/csr/H/htval.yaml index ab6082082..39631dcfc 100644 --- a/arch/csr/H/htval.yaml +++ b/arch/csr/H/htval.yaml @@ -32,5 +32,5 @@ fields: return CsrFieldType::RO; } description: | - Exception-speicific information for a trap into M-mode. + Exception-specific information for a trap into M-mode. reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/H/mtinst.yaml b/arch/csr/H/mtinst.yaml index 64a6af0a0..bbfff0cd3 100644 --- a/arch/csr/H/mtinst.yaml +++ b/arch/csr/H/mtinst.yaml @@ -40,5 +40,5 @@ fields: return CsrFieldType::RO; } description: | - Exception-speicific information for a trap into M-mode. + Exception-specific information for a trap into M-mode. reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/H/mtval2.yaml b/arch/csr/H/mtval2.yaml index eb51a7bb4..03d5db862 100644 --- a/arch/csr/H/mtval2.yaml +++ b/arch/csr/H/mtval2.yaml @@ -33,5 +33,5 @@ fields: return CsrFieldType::RO; } description: | - Exception-speicific information for a trap into M-mode. + Exception-specific information for a trap into M-mode. reset_value: UNDEFINED_LEGAL From c6b2cf209e9f140ee64821131cc7163acbf4483c Mon Sep 17 00:00:00 2001 From: Brian Date: Thu, 28 Nov 2024 23:19:47 -0700 Subject: [PATCH 07/11] fixed rori.yaml encoding --- arch/inst/B/rori.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index d6d41f042..1feba8327 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -12,7 +12,7 @@ definedBy: assembly: xd, xs1, shamt encoding: RV32: - match: 0110000----------101-----0110011 + match: 0110000----------101-----0010011 variables: - name: shamt location: 24-20 @@ -21,7 +21,7 @@ encoding: - name: rd location: 11-7 RV64: - match: 011000-----------101-----0110011 + match: 011000-----------101-----0010011 variables: - name: shamt location: 25-20 From 8bbbd302e51ad4e1e9a8e2e20bcf3b451d63df0b Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Sun, 1 Dec 2024 18:22:36 +0200 Subject: [PATCH 08/11] Zcb spec support initial add Signed-off-by: Albert Yosher --- arch/ext/Zcb.yaml | 42 +++++++++++++++++++++++ arch/inst/Zcb/c.lbu.yaml | 65 ++++++++++++++++++++++++++++++++++++ arch/inst/Zcb/c.lh.yaml | 66 +++++++++++++++++++++++++++++++++++++ arch/inst/Zcb/c.lhu.yaml | 66 +++++++++++++++++++++++++++++++++++++ arch/inst/Zcb/c.mul.yaml | 48 +++++++++++++++++++++++++++ arch/inst/Zcb/c.not.yaml | 42 +++++++++++++++++++++++ arch/inst/Zcb/c.sb.yaml | 37 +++++++++++++++++++++ arch/inst/Zcb/c.sext.b.yaml | 55 +++++++++++++++++++++++++++++++ arch/inst/Zcb/c.sext.h.yaml | 55 +++++++++++++++++++++++++++++++ arch/inst/Zcb/c.sh.yaml | 38 +++++++++++++++++++++ arch/inst/Zcb/c.zext.b.yaml | 55 +++++++++++++++++++++++++++++++ arch/inst/Zcb/c.zext.h.yaml | 55 +++++++++++++++++++++++++++++++ arch/inst/Zcb/c.zext.w.yaml | 55 +++++++++++++++++++++++++++++++ 13 files changed, 679 insertions(+) create mode 100644 arch/ext/Zcb.yaml create mode 100644 arch/inst/Zcb/c.lbu.yaml create mode 100644 arch/inst/Zcb/c.lh.yaml create mode 100644 arch/inst/Zcb/c.lhu.yaml create mode 100644 arch/inst/Zcb/c.mul.yaml create mode 100644 arch/inst/Zcb/c.not.yaml create mode 100644 arch/inst/Zcb/c.sb.yaml create mode 100644 arch/inst/Zcb/c.sext.b.yaml create mode 100644 arch/inst/Zcb/c.sext.h.yaml create mode 100644 arch/inst/Zcb/c.sh.yaml create mode 100644 arch/inst/Zcb/c.zext.b.yaml create mode 100644 arch/inst/Zcb/c.zext.h.yaml create mode 100644 arch/inst/Zcb/c.zext.w.yaml diff --git a/arch/ext/Zcb.yaml b/arch/ext/Zcb.yaml new file mode 100644 index 000000000..53fb28e66 --- /dev/null +++ b/arch/ext/Zcb.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Zcb +long_name: Simple code-size saving instructions +description: | + Zcb has simple code-size saving instructions which are easy to implement on all CPUs. + All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions. + + The Zcb extension depends on the Zca extension. + + As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. + For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented. + +type: unprivileged +company: + name: RISC-V International + url: https://riscv.org +versions: +- version: "1.0.0" + state: ratified + ratification_date: 2023-04 + repositories: + - url: https://github.com/riscv/riscv-code-size-reduction + branch: main + contributors: + - name: Tariq Kurd + - name: Ibrahim Abu Kharmeh + - name: Torbjørn Viem Ness + - name: Matteo Perotti + - name: Nidal Faour + - name: Bill Traynor + - name: Rafael Sene + - name: Xinlong Wu + - name: sinan + - name: Jeremy Bennett + - name: Heda Chen + - name: Alasdair Armstrong + - name: Graeme Smecher + - name: Nicolas Brunie + - name: Jiawei diff --git a/arch/inst/Zcb/c.lbu.yaml b/arch/inst/Zcb/c.lbu.yaml new file mode 100644 index 000000000..b521eb886 --- /dev/null +++ b/arch/inst/Zcb/c.lbu.yaml @@ -0,0 +1,65 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lbu +long_name: Load unsigned byte, 16-bit encoding +description: | + Loads a 8-bit value from memory into register rd. + It computes an effective address by adding the zero-extended offset, to the base address in register rs1. + It expands to `lbu` `rd, offset(rs1)`. +definedBy: + anyOf: + - Zcb + - Zce +assembly: xd, imm(xs1) +encoding: + match: 100000--------00 + variables: + - name: imm + location: 5|6 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[rs1+8] + imm; + + X[rd+8] = zext(read_memory<8>(virtual_address, $encoding), 8); + +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } diff --git a/arch/inst/Zcb/c.lh.yaml b/arch/inst/Zcb/c.lh.yaml new file mode 100644 index 000000000..938bf6936 --- /dev/null +++ b/arch/inst/Zcb/c.lh.yaml @@ -0,0 +1,66 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lh +long_name: Load signed halfword, 16-bit encoding +description: | + Loads a 16-bit value from memory into register rd. + It computes an effective address by adding the zero-extended offset, to the base address in register rs1. + It expands to `lh` `rd, offset(rs1)`. +definedBy: + anyOf: + - Zcb + - Zce +assembly: xd, imm(xs1) +encoding: + match: 100001---1----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[rs1+8] + imm; + + X[rd+8] = sext(read_memory<16>(virtual_address, $encoding), 16); + +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } diff --git a/arch/inst/Zcb/c.lhu.yaml b/arch/inst/Zcb/c.lhu.yaml new file mode 100644 index 000000000..e4567e26e --- /dev/null +++ b/arch/inst/Zcb/c.lhu.yaml @@ -0,0 +1,66 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lhu +long_name: Load unsigned halfword, 16-bit encoding +description: | + Loads a 16-bit value from memory into register rd. + It computes an effective address by adding the zero-extended offset, to the base address in register rs1. + It expands to `lhu` `rd, offset(rs1)`. +definedBy: + anyOf: + - Zcb + - Zce +assembly: xd, imm(xs1) +encoding: + match: 100001---0----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[rs1+8] + imm; + + X[rd+8] = zext(read_memory<16>(virtual_address, $encoding), 16); + +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } diff --git a/arch/inst/Zcb/c.mul.yaml b/arch/inst/Zcb/c.mul.yaml new file mode 100644 index 000000000..60f22a711 --- /dev/null +++ b/arch/inst/Zcb/c.mul.yaml @@ -0,0 +1,48 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.mul +long_name: Multiply, 16-bit encoding +description: | + This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'. + +definedBy: + allOf: + - Zcb + - Zmmul +assembly: xd, xs2 +encoding: + match: 100111---10---01 + variables: + - name: rd + location: 9-7 + - name: rs2 + location: 4-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = X[rd+8] * X[rs2+8]; + +sail(): | + { + let result_wide = to_bits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c))); + X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0]; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.not.yaml b/arch/inst/Zcb/c.not.yaml new file mode 100644 index 000000000..2b1ac3651 --- /dev/null +++ b/arch/inst/Zcb/c.not.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.not +long_name: Bitwise not, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. + +definedBy: + anyOf: + - Zcb + - Zce +assembly: xd +encoding: + match: 100111---1110101 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = ~X[rd+8]; + +sail(): | + { + X(rsdc) = X(rsdc) XOR -1; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.sb.yaml b/arch/inst/Zcb/c.sb.yaml new file mode 100644 index 000000000..95512638b --- /dev/null +++ b/arch/inst/Zcb/c.sb.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sb +long_name: Store unsigned byte, 16-bit encoding +description: | + Stores a 8-bit value from register rs2 into memory. + It computes an effective address by adding the zero-extended offset, to the base address in register rs1. + It expands to `sb` `rs2, offset(rs1)`. +definedBy: + anyOf: + - Zcb + - Zce +assembly: xs2, imm(xs1) +encoding: + match: 100010--------00 + variables: + - name: imm + location: 5|6 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[rs1+8] + imm; + + write_memory<8>(virtual_address, X[rs2+8][7:0], $encoding); diff --git a/arch/inst/Zcb/c.sext.b.yaml b/arch/inst/Zcb/c.sext.b.yaml new file mode 100644 index 000000000..f7d368af7 --- /dev/null +++ b/arch/inst/Zcb/c.sext.b.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sext.b +long_name: Sign-extend byte, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant byte of the source to XLEN by copying + the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. + +definedBy: + allOf: + - Zcb + - Zbb +assembly: xd +encoding: + match: 100111---1100101 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = sext(X[rd+8][15:0],8); + +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.sext.h.yaml b/arch/inst/Zcb/c.sext.h.yaml new file mode 100644 index 000000000..23e181f5f --- /dev/null +++ b/arch/inst/Zcb/c.sext.h.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sext.h +long_name: Sign-extend halfword, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant halfword of the source to XLEN by copying + the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. + +definedBy: + allOf: + - Zcb + - Zbb +assembly: xd +encoding: + match: 100111---1101101 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = sext(X[rd+8][15:0],16); + +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.sh.yaml b/arch/inst/Zcb/c.sh.yaml new file mode 100644 index 000000000..eeb0d9511 --- /dev/null +++ b/arch/inst/Zcb/c.sh.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sh +long_name: Store unsigned halfword, 16-bit encoding +description: | + Stores a 16-bit value from register rs2 into memory. + It computes an effective address by adding the zero-extended offset, to the base address in register rs1. + It expands to `sh` `rs2, offset(rs1)`. +definedBy: + anyOf: + - Zcb + - Zce +assembly: xs2, imm(xs1) +encoding: + match: 100011---0----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[rs1+8] + imm; + + write_memory<16>(virtual_address, X[rs2+8][15:0], $encoding); diff --git a/arch/inst/Zcb/c.zext.b.yaml b/arch/inst/Zcb/c.zext.b.yaml new file mode 100644 index 000000000..a59b37ac6 --- /dev/null +++ b/arch/inst/Zcb/c.zext.b.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.b +long_name: Zero-extend byte, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + This instruction zero-extends the least-significant byte of the source to XLEN by inserting + 0's into all of the bits more significant than 7. + +definedBy: + allOf: + - Zcb + - Zbb +assembly: xd +encoding: + match: 100111---1100001 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = X[rd+8][7:0]; + +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.zext.h.yaml b/arch/inst/Zcb/c.zext.h.yaml new file mode 100644 index 000000000..2be0b9bf3 --- /dev/null +++ b/arch/inst/Zcb/c.zext.h.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.h +long_name: Zero-extend halfword, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + This instruction zero-extends the least-significant halfword of the source to XLEN by inserting + 0's into all of the bits more significant than 15. + +definedBy: + allOf: + - Zcb + - Zbb +assembly: xd +encoding: + match: 100111---1101001 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = X[rd+8][15:0]; + +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + + + + diff --git a/arch/inst/Zcb/c.zext.w.yaml b/arch/inst/Zcb/c.zext.w.yaml new file mode 100644 index 000000000..fc892c6bf --- /dev/null +++ b/arch/inst/Zcb/c.zext.w.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.w +long_name: Zero-extend word, 16-bit encoding +description: | + This instruction takes a single source/destination operand. + It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31. + +definedBy: + allOf: + - Zcb + - Zbb +assembly: xd +base: 64 +encoding: + match: 100111---1110001 + variables: + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[rd+8] = X[rd+8][31:0]; + +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + + + + From d27f011e22075e5ecc1b3f3a0ed6edc766c354b4 Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Mon, 2 Dec 2024 11:05:09 -0500 Subject: [PATCH 09/11] Make regression test parallel for generation steps Signed-off-by: Derek Hower <134728312+dhower-qc@users.noreply.github.com> --- .github/workflows/regress.yml | 124 ++++++++++++++++++++++++++++++++-- 1 file changed, 119 insertions(+), 5 deletions(-) diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index fac7e3df9..da856aa81 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -5,8 +5,124 @@ on: - main workflow_dispatch: jobs: - regress: + regress-smoke: runs-on: ubuntu-latest + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Run smoke + run: ./do smoke + regress-gen-isa-manual: + runs-on: ubuntu-latest + needs: regress-smoke + env: + MANUAL_NAME: isa + VERSIONS: all + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate HTML ISA manual + run: ./do gen:html_manual + regress-gen-ext-pdf: + runs-on: ubuntu-latest + needs: regress-smoke + env: + EXT: B + VERSION: latest + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate extension PDF + run: ./do gen:ext_pdf + regress-gen-certificate: + runs-on: ubuntu-latest + needs: regress-smoke + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate extension PDF + run: ./do gen:cert_model_pdf[MockCertificateModel] + regress-gen-profile: + runs-on: ubuntu-latest + needs: regress-smoke steps: - name: Clone Github Repo Action uses: actions/checkout@v4 @@ -29,7 +145,5 @@ jobs: - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} name: Build container run: ./bin/build_container - - name: Setup project - run: ./bin/setup - - name: Run regression - run: ./do test:regress + - name: Generate extension PDF + run: ./do gen:profile[MockProfileRelease] From 85758c2f9200f7e1561c9eac960488456bce44cf Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Mon, 2 Dec 2024 11:07:28 -0500 Subject: [PATCH 10/11] Fix smoke task name Signed-off-by: Derek Hower <134728312+dhower-qc@users.noreply.github.com> --- .github/workflows/regress.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index da856aa81..9f3fa519c 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -32,7 +32,7 @@ jobs: - name: Setup project run: ./bin/setup - name: Run smoke - run: ./do smoke + run: ./do test:smoke regress-gen-isa-manual: runs-on: ubuntu-latest needs: regress-smoke From a05bbe04cf54467eade12c4edbff8dbbe3bbc04a Mon Sep 17 00:00:00 2001 From: Kevin Broch Date: Wed, 13 Nov 2024 14:08:43 -0800 Subject: [PATCH 11/11] initial pre-commit config relates to #260 --- .devcontainer/onCreateCommand.sh | 2 +- .pre-commit-config.yaml | 14 +++++ LICENSE | 2 +- Rakefile | 6 +-- arch/README.adoc | 2 +- arch/certificate_class/MC.yaml | 6 +-- arch/certificate_model/MC100.yaml | 4 +- .../MockCertificateModel.yaml | 4 +- arch/csr/F/fcsr.yaml | 6 +-- arch/csr/H/henvcfg.yaml | 20 +++---- arch/csr/H/henvcfgh.yaml | 16 +++--- arch/csr/H/hgatp.yaml | 4 +- arch/csr/H/vsatp.yaml | 2 +- arch/csr/I/pmpaddrN.layout | 2 +- arch/csr/I/pmpcfg0.yaml | 32 ++++++------ arch/csr/I/pmpcfg1.yaml | 16 +++--- arch/csr/I/pmpcfg10.yaml | 32 ++++++------ arch/csr/I/pmpcfg11.yaml | 16 +++--- arch/csr/I/pmpcfg12.yaml | 32 ++++++------ arch/csr/I/pmpcfg13.yaml | 16 +++--- arch/csr/I/pmpcfg14.yaml | 32 ++++++------ arch/csr/I/pmpcfg15.yaml | 16 +++--- arch/csr/I/pmpcfg2.yaml | 32 ++++++------ arch/csr/I/pmpcfg3.yaml | 16 +++--- arch/csr/I/pmpcfg4.yaml | 32 ++++++------ arch/csr/I/pmpcfg5.yaml | 16 +++--- arch/csr/I/pmpcfg6.yaml | 32 ++++++------ arch/csr/I/pmpcfg7.yaml | 16 +++--- arch/csr/I/pmpcfg8.yaml | 32 ++++++------ arch/csr/I/pmpcfg9.yaml | 16 +++--- arch/csr/I/pmpcfgN.layout | 4 +- arch/csr/Zicntr/mcountinhibit.layout | 2 +- arch/csr/Zihpm/hpmcounter10.yaml | 8 +-- arch/csr/Zihpm/hpmcounter10h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter11.yaml | 8 +-- arch/csr/Zihpm/hpmcounter11h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter12.yaml | 8 +-- arch/csr/Zihpm/hpmcounter12h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter13.yaml | 8 +-- arch/csr/Zihpm/hpmcounter13h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter14.yaml | 8 +-- arch/csr/Zihpm/hpmcounter14h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter15.yaml | 8 +-- arch/csr/Zihpm/hpmcounter15h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter16.yaml | 8 +-- arch/csr/Zihpm/hpmcounter16h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter17.yaml | 8 +-- arch/csr/Zihpm/hpmcounter17h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter18.yaml | 8 +-- arch/csr/Zihpm/hpmcounter18h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter19.yaml | 8 +-- arch/csr/Zihpm/hpmcounter19h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter20.yaml | 8 +-- arch/csr/Zihpm/hpmcounter20h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter21.yaml | 8 +-- arch/csr/Zihpm/hpmcounter21h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter22.yaml | 8 +-- arch/csr/Zihpm/hpmcounter22h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter23.yaml | 8 +-- arch/csr/Zihpm/hpmcounter23h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter24.yaml | 8 +-- arch/csr/Zihpm/hpmcounter24h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter25.yaml | 8 +-- arch/csr/Zihpm/hpmcounter25h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter26.yaml | 8 +-- arch/csr/Zihpm/hpmcounter26h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter27.yaml | 8 +-- arch/csr/Zihpm/hpmcounter27h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter28.yaml | 8 +-- arch/csr/Zihpm/hpmcounter28h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter29.yaml | 8 +-- arch/csr/Zihpm/hpmcounter29h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter3.yaml | 8 +-- arch/csr/Zihpm/hpmcounter30.yaml | 8 +-- arch/csr/Zihpm/hpmcounter30h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter31.yaml | 8 +-- arch/csr/Zihpm/hpmcounter31h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter3h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter4.yaml | 8 +-- arch/csr/Zihpm/hpmcounter4h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter5.yaml | 8 +-- arch/csr/Zihpm/hpmcounter5h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter6.yaml | 8 +-- arch/csr/Zihpm/hpmcounter6h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter7.yaml | 8 +-- arch/csr/Zihpm/hpmcounter7h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter8.yaml | 8 +-- arch/csr/Zihpm/hpmcounter8h.yaml | 6 +-- arch/csr/Zihpm/hpmcounter9.yaml | 8 +-- arch/csr/Zihpm/hpmcounter9h.yaml | 6 +-- arch/csr/Zihpm/hpmcounterN.layout | 8 +-- arch/csr/Zihpm/hpmcounterNh.layout | 6 +-- arch/csr/Zihpm/mhpmcounter10h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter11h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter12h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter13h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter14h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter15h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter16h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter17h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter18h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter19h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter20h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter21h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter22h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter23h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter24h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter25h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter26h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter27h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter28h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter29h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter30h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter31h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter3h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter4h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter5h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter6h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter7h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter8h.yaml | 2 +- arch/csr/Zihpm/mhpmcounter9h.yaml | 2 +- arch/csr/Zihpm/mhpmcounterNh.layout | 2 +- arch/csr/cycle.yaml | 6 +-- arch/csr/cycleh.yaml | 6 +-- arch/csr/hstatus.yaml | 4 +- arch/csr/instret.yaml | 8 +-- arch/csr/instreth.yaml | 8 +-- arch/csr/mcause.yaml | 2 +- arch/csr/medeleg.yaml | 50 +++++++++--------- arch/csr/menvcfg.yaml | 2 +- arch/csr/menvcfgh.yaml | 4 +- arch/csr/mepc.yaml | 2 +- arch/csr/mhartid.yaml | 2 +- arch/csr/mideleg.yaml | 18 +++---- arch/csr/mie.yaml | 4 +- arch/csr/mimpid.yaml | 2 +- arch/csr/minstreth.yaml | 2 +- arch/csr/mip.yaml | 14 ++--- arch/csr/misa.yaml | 1 - arch/csr/mscratch.yaml | 2 +- arch/csr/mstatus.yaml | 52 +++++++++---------- arch/csr/mstatush.yaml | 1 - arch/csr/mtval.yaml | 14 ++--- arch/csr/mtvec.yaml | 2 +- arch/csr/scause.yaml | 2 +- arch/csr/schema.adoc | 1 - arch/csr/senvcfg.yaml | 4 +- arch/csr/sstatus.yaml | 20 +++---- arch/csr/stval.yaml | 16 +++--- arch/csr/stvec.yaml | 2 +- arch/csr/time.yaml | 8 +-- arch/csr/timeh.yaml | 8 +-- arch/csr/vscause.yaml | 2 +- arch/csr/vsstatus.yaml | 8 +-- arch/csr/vstval.yaml | 16 +++--- arch/csr/vstvec.yaml | 4 +- arch/ext/A.yaml | 4 +- arch/ext/C.yaml | 12 ++--- arch/ext/D.yaml | 2 +- arch/ext/F.yaml | 4 +- arch/ext/H.yaml | 8 +-- arch/ext/I.yaml | 2 +- arch/ext/M.yaml | 2 +- arch/ext/MockExt.yaml | 4 +- arch/ext/Sm.yaml | 10 ++-- arch/ext/Smcdeleg.yaml | 2 +- arch/ext/Smhpm.yaml | 4 +- arch/ext/Smpmp.yaml | 8 +-- arch/ext/Sstvala.yaml | 4 +- arch/ext/Svade.yaml | 1 - arch/ext/Svadu.yaml | 5 +- arch/ext/Svnapot.yaml | 4 +- arch/ext/U.yaml | 2 +- arch/ext/V.yaml | 2 +- arch/ext/Zalrsc.yaml | 2 +- arch/ext/Zbc.yaml | 2 - arch/ext/Zbs.yaml | 2 - arch/ext/Zcb.yaml | 14 ++--- arch/ext/Zfhmin.yaml | 1 - arch/ext/Zicboz.yaml | 2 +- arch/ext/Zicntr.yaml | 4 +- arch/ext/Zihpm.yaml | 4 +- arch/ext/Zkt.yaml | 5 +- arch/inst/A/amoadd.d.yaml | 8 +-- arch/inst/A/amoadd.w.yaml | 8 +-- arch/inst/A/amoand.d.yaml | 8 +-- arch/inst/A/amoand.w.yaml | 8 +-- arch/inst/A/amomax.d.yaml | 8 +-- arch/inst/A/amomax.w.yaml | 8 +-- arch/inst/A/amomaxu.d.yaml | 8 +-- arch/inst/A/amomaxu.w.yaml | 8 +-- arch/inst/A/amomin.d.yaml | 8 +-- arch/inst/A/amomin.w.yaml | 8 +-- arch/inst/A/amominu.d.yaml | 8 +-- arch/inst/A/amominu.w.yaml | 8 +-- arch/inst/A/amoor.d.yaml | 8 +-- arch/inst/A/amoor.w.yaml | 8 +-- arch/inst/A/amoswap.d.yaml | 8 +-- arch/inst/A/amoswap.w.yaml | 8 +-- arch/inst/A/amoxor.d.yaml | 8 +-- arch/inst/A/amoxor.w.yaml | 8 +-- arch/inst/A/lr.d.yaml | 4 -- arch/inst/A/lr.w.yaml | 4 -- arch/inst/A/sc.d.yaml | 4 -- arch/inst/A/sc.w.yaml | 4 -- arch/inst/B/add.uw.yaml | 4 -- arch/inst/B/andn.yaml | 4 -- arch/inst/B/bclr.yaml | 4 -- arch/inst/B/bclri.yaml | 4 -- arch/inst/B/bext.yaml | 4 -- arch/inst/B/bexti.yaml | 4 -- arch/inst/B/binv.yaml | 4 -- arch/inst/B/binvi.yaml | 4 -- arch/inst/B/bset.yaml | 4 -- arch/inst/B/bseti.yaml | 4 -- arch/inst/B/clmul.yaml | 4 -- arch/inst/B/clmulh.yaml | 4 -- arch/inst/B/clmulr.yaml | 4 -- arch/inst/B/clz.yaml | 4 -- arch/inst/B/clzw.yaml | 4 -- arch/inst/B/cpop.yaml | 4 -- arch/inst/B/cpopw.yaml | 4 -- arch/inst/B/ctz.yaml | 4 -- arch/inst/B/ctzw.yaml | 4 -- arch/inst/B/max.yaml | 4 -- arch/inst/B/maxu.yaml | 4 -- arch/inst/B/min.yaml | 4 -- arch/inst/B/minu.yaml | 4 -- arch/inst/B/orc.b.yaml | 4 -- arch/inst/B/orn.yaml | 4 -- arch/inst/B/rev8.yaml | 4 -- arch/inst/B/rol.yaml | 4 -- arch/inst/B/rolw.yaml | 4 -- arch/inst/B/ror.yaml | 4 -- arch/inst/B/rori.yaml | 4 -- arch/inst/B/roriw.yaml | 4 -- arch/inst/B/rorw.yaml | 4 -- arch/inst/B/sext.b.yaml | 4 -- arch/inst/B/sext.h.yaml | 4 -- arch/inst/B/sh1add.uw.yaml | 4 -- arch/inst/B/sh1add.yaml | 4 -- arch/inst/B/sh2add.uw.yaml | 4 -- arch/inst/B/sh2add.yaml | 4 -- arch/inst/B/sh3add.uw.yaml | 4 -- arch/inst/B/sh3add.yaml | 4 -- arch/inst/B/slli.uw.yaml | 4 -- arch/inst/B/xnor.yaml | 4 -- arch/inst/B/zext.h.yaml | 8 +-- arch/inst/C/c.add.yaml | 2 +- arch/inst/C/c.addi.yaml | 5 +- arch/inst/C/c.addi16sp.yaml | 7 ++- arch/inst/C/c.addi4spn.yaml | 5 +- arch/inst/C/c.addiw.yaml | 7 ++- arch/inst/C/c.addw.yaml | 2 +- arch/inst/C/c.and.yaml | 2 +- arch/inst/C/c.andi.yaml | 2 +- arch/inst/C/c.beqz.yaml | 2 +- arch/inst/C/c.bnez.yaml | 2 +- arch/inst/C/c.fld.yaml | 2 +- arch/inst/C/c.flw.yaml | 2 +- arch/inst/C/c.fsd.yaml | 2 +- arch/inst/C/c.fsw.yaml | 2 +- arch/inst/C/c.jr.yaml | 2 +- arch/inst/C/c.li.yaml | 5 +- arch/inst/C/c.lui.yaml | 7 ++- arch/inst/C/c.lw.yaml | 2 +- arch/inst/C/c.nop.yaml | 3 +- arch/inst/C/c.or.yaml | 2 +- arch/inst/C/c.sd.yaml | 2 +- arch/inst/C/c.slli.yaml | 6 +-- arch/inst/C/c.srai.yaml | 2 +- arch/inst/C/c.srli.yaml | 6 +-- arch/inst/C/c.sub.yaml | 2 +- arch/inst/C/c.subw.yaml | 2 +- arch/inst/C/c.sw.yaml | 2 +- arch/inst/C/c.xor.yaml | 2 +- arch/inst/D/fadd.d.yaml | 1 - arch/inst/D/fclass.d.yaml | 1 - arch/inst/D/fcvt.d.l.yaml | 1 - arch/inst/D/fcvt.d.lu.yaml | 1 - arch/inst/D/fcvt.d.s.yaml | 1 - arch/inst/D/fcvt.d.w.yaml | 1 - arch/inst/D/fcvt.d.wu.yaml | 1 - arch/inst/D/fcvt.l.d.yaml | 1 - arch/inst/D/fcvt.lu.d.yaml | 1 - arch/inst/D/fcvt.s.d.yaml | 1 - arch/inst/D/fcvt.w.d.yaml | 1 - arch/inst/D/fcvt.wu.d.yaml | 1 - arch/inst/D/fcvtmod.w.d.yaml | 1 - arch/inst/D/fdiv.d.yaml | 1 - arch/inst/D/feq.d.yaml | 1 - arch/inst/D/fld.yaml | 1 - arch/inst/D/fle.d.yaml | 1 - arch/inst/D/fleq.d.yaml | 1 - arch/inst/D/fli.d.yaml | 1 - arch/inst/D/flt.d.yaml | 1 - arch/inst/D/fltq.d.yaml | 1 - arch/inst/D/fmadd.d.yaml | 1 - arch/inst/D/fmax.d.yaml | 1 - arch/inst/D/fmaxm.d.yaml | 1 - arch/inst/D/fmin.d.yaml | 1 - arch/inst/D/fminm.d.yaml | 1 - arch/inst/D/fmsub.d.yaml | 1 - arch/inst/D/fmul.d.yaml | 1 - arch/inst/D/fmv.d.x.yaml | 1 - arch/inst/D/fmv.x.d.yaml | 1 - arch/inst/D/fmvh.x.d.yaml | 1 - arch/inst/D/fmvp.d.x.yaml | 1 - arch/inst/D/fnmadd.d.yaml | 1 - arch/inst/D/fnmsub.d.yaml | 1 - arch/inst/D/fround.d.yaml | 1 - arch/inst/D/froundnx.d.yaml | 1 - arch/inst/D/fsd.yaml | 1 - arch/inst/D/fsgnj.d.yaml | 1 - arch/inst/D/fsgnjn.d.yaml | 1 - arch/inst/D/fsgnjx.d.yaml | 1 - arch/inst/D/fsqrt.d.yaml | 1 - arch/inst/D/fsub.d.yaml | 1 - arch/inst/F/fadd.s.yaml | 6 +-- arch/inst/F/fclass.s.yaml | 6 +-- arch/inst/F/fcvt.l.s.yaml | 8 +-- arch/inst/F/fcvt.lu.s.yaml | 8 +-- arch/inst/F/fcvt.s.l.yaml | 8 +-- arch/inst/F/fcvt.s.lu.yaml | 8 +-- arch/inst/F/fcvt.s.w.yaml | 6 +-- arch/inst/F/fcvt.s.wu.yaml | 8 +-- arch/inst/F/fcvt.w.s.yaml | 6 +-- arch/inst/F/fcvt.wu.s.yaml | 8 +-- arch/inst/F/fdiv.s.yaml | 6 +-- arch/inst/F/feq.s.yaml | 8 +-- arch/inst/F/fle.s.yaml | 8 +-- arch/inst/F/fleq.s.yaml | 10 ++-- arch/inst/F/fli.s.yaml | 6 +-- arch/inst/F/flt.s.yaml | 10 ++-- arch/inst/F/fltq.s.yaml | 10 ++-- arch/inst/F/flw.yaml | 4 -- arch/inst/F/fmadd.s.yaml | 6 +-- arch/inst/F/fmax.s.yaml | 10 ++-- arch/inst/F/fmaxm.s.yaml | 12 ++--- arch/inst/F/fmin.s.yaml | 10 ++-- arch/inst/F/fminm.s.yaml | 12 ++--- arch/inst/F/fmsub.s.yaml | 6 +-- arch/inst/F/fmul.s.yaml | 6 +-- arch/inst/F/fmv.w.x.yaml | 4 -- arch/inst/F/fmv.x.w.yaml | 4 -- arch/inst/F/fnmadd.s.yaml | 6 +-- arch/inst/F/fnmsub.s.yaml | 6 +-- arch/inst/F/fround.s.yaml | 10 ++-- arch/inst/F/froundnx.s.yaml | 10 ++-- arch/inst/F/fsgnj.s.yaml | 8 +-- arch/inst/F/fsgnjn.s.yaml | 8 +-- arch/inst/F/fsgnjx.s.yaml | 8 +-- arch/inst/F/fsqrt.s.yaml | 8 +-- arch/inst/F/fsub.s.yaml | 6 +-- arch/inst/F/fsw.yaml | 4 -- arch/inst/H/hfence.gvma.yaml | 1 - arch/inst/H/hfence.vvma.yaml | 1 - arch/inst/H/hlv.b.yaml | 1 - arch/inst/H/hlv.bu.yaml | 1 - arch/inst/H/hlv.d.yaml | 1 - arch/inst/H/hlv.h.yaml | 1 - arch/inst/H/hlv.hu.yaml | 1 - arch/inst/H/hlv.w.yaml | 1 - arch/inst/H/hlv.wu.yaml | 1 - arch/inst/H/hlvx.hu.yaml | 1 - arch/inst/H/hlvx.wu.yaml | 1 - arch/inst/H/hsv.b.yaml | 1 - arch/inst/H/hsv.d.yaml | 1 - arch/inst/H/hsv.h.yaml | 1 - arch/inst/H/hsv.w.yaml | 1 - arch/inst/I/add.yaml | 4 -- arch/inst/I/addi.yaml | 4 -- arch/inst/I/addiw.yaml | 4 -- arch/inst/I/addw.yaml | 4 -- arch/inst/I/and.yaml | 4 -- arch/inst/I/andi.yaml | 4 -- arch/inst/I/auipc.yaml | 1 - arch/inst/I/beq.yaml | 4 -- arch/inst/I/bge.yaml | 6 +-- arch/inst/I/bgeu.yaml | 6 +-- arch/inst/I/blt.yaml | 6 +-- arch/inst/I/bltu.yaml | 6 +-- arch/inst/I/bne.yaml | 6 +-- arch/inst/I/ebreak.yaml | 4 -- arch/inst/I/ecall.yaml | 4 -- arch/inst/I/fence.yaml | 16 +++--- arch/inst/I/jal.yaml | 4 -- arch/inst/I/jalr.yaml | 4 -- arch/inst/I/lb.yaml | 4 -- arch/inst/I/lbu.yaml | 4 -- arch/inst/I/ld.yaml | 4 -- arch/inst/I/lh.yaml | 4 -- arch/inst/I/lhu.yaml | 4 -- arch/inst/I/lui.yaml | 4 -- arch/inst/I/lw.yaml | 4 -- arch/inst/I/lwu.yaml | 4 -- arch/inst/I/mret.yaml | 4 -- arch/inst/I/or.yaml | 4 -- arch/inst/I/ori.yaml | 8 +-- arch/inst/I/sb.yaml | 4 -- arch/inst/I/sd.yaml | 4 -- arch/inst/I/sh.yaml | 4 -- arch/inst/I/sll.yaml | 4 -- arch/inst/I/slli.yaml | 4 -- arch/inst/I/slliw.yaml | 4 -- arch/inst/I/sllw.yaml | 4 -- arch/inst/I/slt.yaml | 4 -- arch/inst/I/slti.yaml | 4 -- arch/inst/I/sltiu.yaml | 4 -- arch/inst/I/sltu.yaml | 4 -- arch/inst/I/sra.yaml | 4 -- arch/inst/I/srai.yaml | 4 -- arch/inst/I/sraiw.yaml | 4 -- arch/inst/I/sraw.yaml | 4 -- arch/inst/I/srl.yaml | 4 -- arch/inst/I/srli.yaml | 4 -- arch/inst/I/srliw.yaml | 4 -- arch/inst/I/srlw.yaml | 4 -- arch/inst/I/sub.yaml | 4 -- arch/inst/I/subw.yaml | 4 -- arch/inst/I/sw.yaml | 4 -- arch/inst/I/wfi.yaml | 8 +-- arch/inst/I/xor.yaml | 4 -- arch/inst/I/xori.yaml | 4 -- arch/inst/M/div.yaml | 6 +-- arch/inst/M/divu.yaml | 6 +-- arch/inst/M/divuw.yaml | 6 +-- arch/inst/M/divw.yaml | 8 +-- arch/inst/M/mul.yaml | 4 -- arch/inst/M/mulh.yaml | 4 -- arch/inst/M/mulhsu.yaml | 4 -- arch/inst/M/mulhu.yaml | 4 -- arch/inst/M/mulw.yaml | 4 -- arch/inst/M/rem.yaml | 6 +-- arch/inst/M/remu.yaml | 4 -- arch/inst/M/remuw.yaml | 4 -- arch/inst/M/remw.yaml | 6 +-- arch/inst/Q/fadd.q.yaml | 1 - arch/inst/Q/fclass.q.yaml | 1 - arch/inst/Q/fcvt.d.q.yaml | 1 - arch/inst/Q/fcvt.h.q.yaml | 1 - arch/inst/Q/fcvt.l.q.yaml | 1 - arch/inst/Q/fcvt.lu.q.yaml | 1 - arch/inst/Q/fcvt.q.d.yaml | 1 - arch/inst/Q/fcvt.q.h.yaml | 1 - arch/inst/Q/fcvt.q.l.yaml | 1 - arch/inst/Q/fcvt.q.lu.yaml | 1 - arch/inst/Q/fcvt.q.s.yaml | 1 - arch/inst/Q/fcvt.q.w.yaml | 1 - arch/inst/Q/fcvt.q.wu.yaml | 1 - arch/inst/Q/fcvt.s.q.yaml | 1 - arch/inst/Q/fcvt.w.q.yaml | 1 - arch/inst/Q/fcvt.wu.q.yaml | 1 - arch/inst/Q/fdiv.q.yaml | 1 - arch/inst/Q/feq.q.yaml | 1 - arch/inst/Q/fle.q.yaml | 1 - arch/inst/Q/fleq.q.yaml | 1 - arch/inst/Q/fli.q.yaml | 1 - arch/inst/Q/flq.yaml | 1 - arch/inst/Q/flt.q.yaml | 1 - arch/inst/Q/fltq.q.yaml | 1 - arch/inst/Q/fmadd.q.yaml | 1 - arch/inst/Q/fmax.q.yaml | 1 - arch/inst/Q/fmaxm.q.yaml | 1 - arch/inst/Q/fmin.q.yaml | 1 - arch/inst/Q/fminm.q.yaml | 1 - arch/inst/Q/fmsub.q.yaml | 1 - arch/inst/Q/fmul.q.yaml | 1 - arch/inst/Q/fmvh.x.q.yaml | 1 - arch/inst/Q/fmvp.q.x.yaml | 1 - arch/inst/Q/fnmadd.q.yaml | 1 - arch/inst/Q/fnmsub.q.yaml | 1 - arch/inst/Q/fround.q.yaml | 1 - arch/inst/Q/froundnx.q.yaml | 1 - arch/inst/Q/fsgnj.q.yaml | 1 - arch/inst/Q/fsgnjn.q.yaml | 1 - arch/inst/Q/fsgnjx.q.yaml | 1 - arch/inst/Q/fsq.yaml | 1 - arch/inst/Q/fsqrt.q.yaml | 1 - arch/inst/Q/fsub.q.yaml | 1 - arch/inst/S/sfence.vma.yaml | 4 -- arch/inst/S/sret.yaml | 10 ++-- arch/inst/Sdext/dret.yaml | 1 - arch/inst/Smdbltrp/sctrclr.yaml | 1 - arch/inst/Smrnmi/mnret.yaml | 1 - arch/inst/Svinval/hinval.gvma.yaml | 1 - arch/inst/Svinval/hinval.vvma.yaml | 1 - arch/inst/Svinval/sfence.w.inval.yaml | 1 - arch/inst/Svinval/sinval.vma.yaml | 1 - arch/inst/V/vaadd.vv.yaml | 15 +++--- arch/inst/V/vaadd.vx.yaml | 15 +++--- arch/inst/V/vaaddu.vv.yaml | 15 +++--- arch/inst/V/vaaddu.vx.yaml | 15 +++--- arch/inst/V/vadc.vim.yaml | 17 +++--- arch/inst/V/vadc.vvm.yaml | 17 +++--- arch/inst/V/vadc.vxm.yaml | 17 +++--- arch/inst/V/vadd.vi.yaml | 15 +++--- arch/inst/V/vadd.vv.yaml | 15 +++--- arch/inst/V/vadd.vx.yaml | 15 +++--- arch/inst/V/vand.vi.yaml | 15 +++--- arch/inst/V/vand.vv.yaml | 15 +++--- arch/inst/V/vand.vx.yaml | 15 +++--- arch/inst/V/vasub.vv.yaml | 15 +++--- arch/inst/V/vasub.vx.yaml | 15 +++--- arch/inst/V/vasubu.vv.yaml | 15 +++--- arch/inst/V/vasubu.vx.yaml | 15 +++--- arch/inst/V/vcompress.vm.yaml | 13 +++-- arch/inst/V/vcpop.m.yaml | 1 - arch/inst/V/vdiv.vv.yaml | 15 +++--- arch/inst/V/vdiv.vx.yaml | 15 +++--- arch/inst/V/vdivu.vv.yaml | 15 +++--- arch/inst/V/vdivu.vx.yaml | 15 +++--- arch/inst/V/vfadd.vf.yaml | 15 +++--- arch/inst/V/vfadd.vv.yaml | 15 +++--- arch/inst/V/vfclass.v.yaml | 15 +++--- arch/inst/V/vfcvt.f.x.v.yaml | 15 +++--- arch/inst/V/vfcvt.f.xu.v.yaml | 15 +++--- arch/inst/V/vfcvt.rtz.x.f.v.yaml | 15 +++--- arch/inst/V/vfcvt.rtz.xu.f.v.yaml | 15 +++--- arch/inst/V/vfcvt.x.f.v.yaml | 15 +++--- arch/inst/V/vfcvt.xu.f.v.yaml | 15 +++--- arch/inst/V/vfdiv.vf.yaml | 15 +++--- arch/inst/V/vfdiv.vv.yaml | 15 +++--- arch/inst/V/vfirst.m.yaml | 15 +++--- arch/inst/V/vfmacc.vf.yaml | 15 +++--- arch/inst/V/vfmacc.vv.yaml | 15 +++--- arch/inst/V/vfmadd.vf.yaml | 15 +++--- arch/inst/V/vfmadd.vv.yaml | 15 +++--- arch/inst/V/vfmax.vf.yaml | 15 +++--- arch/inst/V/vfmax.vv.yaml | 15 +++--- arch/inst/V/vfmerge.vfm.yaml | 13 +++-- arch/inst/V/vfmin.vf.yaml | 15 +++--- arch/inst/V/vfmin.vv.yaml | 15 +++--- arch/inst/V/vfmsac.vf.yaml | 15 +++--- arch/inst/V/vfmsac.vv.yaml | 15 +++--- arch/inst/V/vfmsub.vf.yaml | 15 +++--- arch/inst/V/vfmsub.vv.yaml | 15 +++--- arch/inst/V/vfmul.vf.yaml | 15 +++--- arch/inst/V/vfmul.vv.yaml | 15 +++--- arch/inst/V/vfmv.f.s.yaml | 11 ++-- arch/inst/V/vfmv.s.f.yaml | 17 +++--- arch/inst/V/vfmv.v.f.yaml | 15 +++--- arch/inst/V/vfncvt.f.f.w.yaml | 15 +++--- arch/inst/V/vfncvt.f.x.w.yaml | 15 +++--- arch/inst/V/vfncvt.f.xu.w.yaml | 15 +++--- arch/inst/V/vfncvt.rod.f.f.w.yaml | 15 +++--- arch/inst/V/vfncvt.rtz.x.f.w.yaml | 15 +++--- arch/inst/V/vfncvt.rtz.xu.f.w.yaml | 15 +++--- arch/inst/V/vfncvt.x.f.w.yaml | 15 +++--- arch/inst/V/vfncvt.xu.f.w.yaml | 15 +++--- arch/inst/V/vfnmacc.vf.yaml | 15 +++--- arch/inst/V/vfnmacc.vv.yaml | 15 +++--- arch/inst/V/vfnmadd.vf.yaml | 15 +++--- arch/inst/V/vfnmadd.vv.yaml | 15 +++--- arch/inst/V/vfnmsac.vf.yaml | 15 +++--- arch/inst/V/vfnmsac.vv.yaml | 15 +++--- arch/inst/V/vfnmsub.vf.yaml | 15 +++--- arch/inst/V/vfnmsub.vv.yaml | 15 +++--- arch/inst/V/vfrdiv.vf.yaml | 15 +++--- arch/inst/V/vfrec7.v.yaml | 15 +++--- arch/inst/V/vfredmax.vs.yaml | 5 +- arch/inst/V/vfredmin.vs.yaml | 5 +- arch/inst/V/vfredosum.vs.yaml | 5 +- arch/inst/V/vfredusum.vs.yaml | 5 +- arch/inst/V/vfrsqrt7.v.yaml | 15 +++--- arch/inst/V/vfrsub.vf.yaml | 15 +++--- arch/inst/V/vfsgnj.vf.yaml | 15 +++--- arch/inst/V/vfsgnj.vv.yaml | 15 +++--- arch/inst/V/vfsgnjn.vf.yaml | 15 +++--- arch/inst/V/vfsgnjn.vv.yaml | 15 +++--- arch/inst/V/vfsgnjx.vf.yaml | 15 +++--- arch/inst/V/vfsgnjx.vv.yaml | 15 +++--- arch/inst/V/vfslide1down.vf.yaml | 15 +++--- arch/inst/V/vfslide1up.vf.yaml | 15 +++--- arch/inst/V/vfsqrt.v.yaml | 15 +++--- arch/inst/V/vfsub.vf.yaml | 15 +++--- arch/inst/V/vfsub.vv.yaml | 15 +++--- arch/inst/V/vfwadd.vf.yaml | 15 +++--- arch/inst/V/vfwadd.vv.yaml | 15 +++--- arch/inst/V/vfwadd.wf.yaml | 15 +++--- arch/inst/V/vfwadd.wv.yaml | 15 +++--- arch/inst/V/vfwcvt.f.f.v.yaml | 15 +++--- arch/inst/V/vfwcvt.f.x.v.yaml | 15 +++--- arch/inst/V/vfwcvt.f.xu.v.yaml | 15 +++--- arch/inst/V/vfwcvt.rtz.x.f.v.yaml | 15 +++--- arch/inst/V/vfwcvt.rtz.xu.f.v.yaml | 15 +++--- arch/inst/V/vfwcvt.x.f.v.yaml | 15 +++--- arch/inst/V/vfwcvt.xu.f.v.yaml | 15 +++--- arch/inst/V/vfwmacc.vf.yaml | 15 +++--- arch/inst/V/vfwmacc.vv.yaml | 15 +++--- arch/inst/V/vfwmsac.vf.yaml | 15 +++--- arch/inst/V/vfwmsac.vv.yaml | 15 +++--- arch/inst/V/vfwmul.vf.yaml | 15 +++--- arch/inst/V/vfwmul.vv.yaml | 15 +++--- arch/inst/V/vfwnmacc.vf.yaml | 15 +++--- arch/inst/V/vfwnmacc.vv.yaml | 15 +++--- arch/inst/V/vfwnmsac.vf.yaml | 15 +++--- arch/inst/V/vfwnmsac.vv.yaml | 15 +++--- arch/inst/V/vfwredosum.vs.yaml | 5 +- arch/inst/V/vfwredusum.vs.yaml | 5 +- arch/inst/V/vfwsub.vf.yaml | 15 +++--- arch/inst/V/vfwsub.vv.yaml | 15 +++--- arch/inst/V/vfwsub.wf.yaml | 15 +++--- arch/inst/V/vfwsub.wv.yaml | 15 +++--- arch/inst/V/vid.v.yaml | 15 +++--- arch/inst/V/viota.m.yaml | 15 +++--- arch/inst/V/vl1re16.v.yaml | 1 - arch/inst/V/vl1re32.v.yaml | 1 - arch/inst/V/vl1re64.v.yaml | 1 - arch/inst/V/vl1re8.v.yaml | 1 - arch/inst/V/vl2re16.v.yaml | 1 - arch/inst/V/vl2re32.v.yaml | 1 - arch/inst/V/vl2re64.v.yaml | 1 - arch/inst/V/vl2re8.v.yaml | 1 - arch/inst/V/vl4re16.v.yaml | 1 - arch/inst/V/vl4re32.v.yaml | 1 - arch/inst/V/vl4re64.v.yaml | 1 - arch/inst/V/vl4re8.v.yaml | 1 - arch/inst/V/vl8re16.v.yaml | 1 - arch/inst/V/vl8re32.v.yaml | 1 - arch/inst/V/vl8re64.v.yaml | 1 - arch/inst/V/vl8re8.v.yaml | 1 - arch/inst/V/vle16.v.yaml | 7 ++- arch/inst/V/vle16ff.v.yaml | 7 ++- arch/inst/V/vle32.v.yaml | 7 ++- arch/inst/V/vle32ff.v.yaml | 7 ++- arch/inst/V/vle64.v.yaml | 7 ++- arch/inst/V/vle64ff.v.yaml | 7 ++- arch/inst/V/vle8.v.yaml | 7 ++- arch/inst/V/vle8ff.v.yaml | 7 ++- arch/inst/V/vlm.v.yaml | 7 ++- arch/inst/V/vloxei16.v.yaml | 7 ++- arch/inst/V/vloxei32.v.yaml | 7 ++- arch/inst/V/vloxei64.v.yaml | 7 ++- arch/inst/V/vloxei8.v.yaml | 7 ++- arch/inst/V/vloxseg2ei16.v.yaml | 1 - arch/inst/V/vloxseg2ei32.v.yaml | 1 - arch/inst/V/vloxseg2ei64.v.yaml | 1 - arch/inst/V/vloxseg2ei8.v.yaml | 1 - arch/inst/V/vloxseg3ei16.v.yaml | 1 - arch/inst/V/vloxseg3ei32.v.yaml | 1 - arch/inst/V/vloxseg3ei64.v.yaml | 1 - arch/inst/V/vloxseg3ei8.v.yaml | 1 - arch/inst/V/vloxseg4ei16.v.yaml | 1 - arch/inst/V/vloxseg4ei32.v.yaml | 1 - arch/inst/V/vloxseg4ei64.v.yaml | 1 - arch/inst/V/vloxseg4ei8.v.yaml | 1 - arch/inst/V/vloxseg5ei16.v.yaml | 1 - arch/inst/V/vloxseg5ei32.v.yaml | 1 - arch/inst/V/vloxseg5ei64.v.yaml | 1 - arch/inst/V/vloxseg5ei8.v.yaml | 1 - arch/inst/V/vloxseg6ei16.v.yaml | 1 - arch/inst/V/vloxseg6ei32.v.yaml | 1 - arch/inst/V/vloxseg6ei64.v.yaml | 1 - arch/inst/V/vloxseg6ei8.v.yaml | 1 - arch/inst/V/vloxseg7ei16.v.yaml | 1 - arch/inst/V/vloxseg7ei32.v.yaml | 1 - arch/inst/V/vloxseg7ei64.v.yaml | 1 - arch/inst/V/vloxseg7ei8.v.yaml | 1 - arch/inst/V/vloxseg8ei16.v.yaml | 1 - arch/inst/V/vloxseg8ei32.v.yaml | 1 - arch/inst/V/vloxseg8ei64.v.yaml | 1 - arch/inst/V/vloxseg8ei8.v.yaml | 1 - arch/inst/V/vlse16.v.yaml | 7 ++- arch/inst/V/vlse32.v.yaml | 7 ++- arch/inst/V/vlse64.v.yaml | 7 ++- arch/inst/V/vlse8.v.yaml | 7 ++- arch/inst/V/vlseg2e16.v.yaml | 1 - arch/inst/V/vlseg2e16ff.v.yaml | 1 - arch/inst/V/vlseg2e32.v.yaml | 1 - arch/inst/V/vlseg2e32ff.v.yaml | 1 - arch/inst/V/vlseg2e64.v.yaml | 1 - arch/inst/V/vlseg2e64ff.v.yaml | 1 - arch/inst/V/vlseg2e8.v.yaml | 1 - arch/inst/V/vlseg2e8ff.v.yaml | 1 - arch/inst/V/vlseg3e16.v.yaml | 1 - arch/inst/V/vlseg3e16ff.v.yaml | 1 - arch/inst/V/vlseg3e32.v.yaml | 1 - arch/inst/V/vlseg3e32ff.v.yaml | 1 - arch/inst/V/vlseg3e64.v.yaml | 1 - arch/inst/V/vlseg3e64ff.v.yaml | 1 - arch/inst/V/vlseg3e8.v.yaml | 1 - arch/inst/V/vlseg3e8ff.v.yaml | 1 - arch/inst/V/vlseg4e16.v.yaml | 1 - arch/inst/V/vlseg4e16ff.v.yaml | 1 - arch/inst/V/vlseg4e32.v.yaml | 1 - arch/inst/V/vlseg4e32ff.v.yaml | 1 - arch/inst/V/vlseg4e64.v.yaml | 1 - arch/inst/V/vlseg4e64ff.v.yaml | 1 - arch/inst/V/vlseg4e8.v.yaml | 1 - arch/inst/V/vlseg4e8ff.v.yaml | 1 - arch/inst/V/vlseg5e16.v.yaml | 1 - arch/inst/V/vlseg5e16ff.v.yaml | 1 - arch/inst/V/vlseg5e32.v.yaml | 1 - arch/inst/V/vlseg5e32ff.v.yaml | 1 - arch/inst/V/vlseg5e64.v.yaml | 1 - arch/inst/V/vlseg5e64ff.v.yaml | 1 - arch/inst/V/vlseg5e8.v.yaml | 1 - arch/inst/V/vlseg5e8ff.v.yaml | 1 - arch/inst/V/vlseg6e16.v.yaml | 1 - arch/inst/V/vlseg6e16ff.v.yaml | 1 - arch/inst/V/vlseg6e32.v.yaml | 1 - arch/inst/V/vlseg6e32ff.v.yaml | 1 - arch/inst/V/vlseg6e64.v.yaml | 1 - arch/inst/V/vlseg6e64ff.v.yaml | 1 - arch/inst/V/vlseg6e8.v.yaml | 1 - arch/inst/V/vlseg6e8ff.v.yaml | 1 - arch/inst/V/vlseg7e16.v.yaml | 1 - arch/inst/V/vlseg7e16ff.v.yaml | 1 - arch/inst/V/vlseg7e32.v.yaml | 1 - arch/inst/V/vlseg7e32ff.v.yaml | 1 - arch/inst/V/vlseg7e64.v.yaml | 1 - arch/inst/V/vlseg7e64ff.v.yaml | 1 - arch/inst/V/vlseg7e8.v.yaml | 1 - arch/inst/V/vlseg7e8ff.v.yaml | 1 - arch/inst/V/vlseg8e16.v.yaml | 1 - arch/inst/V/vlseg8e16ff.v.yaml | 1 - arch/inst/V/vlseg8e32.v.yaml | 1 - arch/inst/V/vlseg8e32ff.v.yaml | 1 - arch/inst/V/vlseg8e64.v.yaml | 1 - arch/inst/V/vlseg8e64ff.v.yaml | 1 - arch/inst/V/vlseg8e8.v.yaml | 1 - arch/inst/V/vlseg8e8ff.v.yaml | 1 - arch/inst/V/vlsseg2e16.v.yaml | 1 - arch/inst/V/vlsseg2e32.v.yaml | 1 - arch/inst/V/vlsseg2e64.v.yaml | 1 - arch/inst/V/vlsseg2e8.v.yaml | 1 - arch/inst/V/vlsseg3e16.v.yaml | 1 - arch/inst/V/vlsseg3e32.v.yaml | 1 - arch/inst/V/vlsseg3e64.v.yaml | 1 - arch/inst/V/vlsseg3e8.v.yaml | 1 - arch/inst/V/vlsseg4e16.v.yaml | 1 - arch/inst/V/vlsseg4e32.v.yaml | 1 - arch/inst/V/vlsseg4e64.v.yaml | 1 - arch/inst/V/vlsseg4e8.v.yaml | 1 - arch/inst/V/vlsseg5e16.v.yaml | 1 - arch/inst/V/vlsseg5e32.v.yaml | 1 - arch/inst/V/vlsseg5e64.v.yaml | 1 - arch/inst/V/vlsseg5e8.v.yaml | 1 - arch/inst/V/vlsseg6e16.v.yaml | 1 - arch/inst/V/vlsseg6e32.v.yaml | 1 - arch/inst/V/vlsseg6e64.v.yaml | 1 - arch/inst/V/vlsseg6e8.v.yaml | 1 - arch/inst/V/vlsseg7e16.v.yaml | 1 - arch/inst/V/vlsseg7e32.v.yaml | 1 - arch/inst/V/vlsseg7e64.v.yaml | 1 - arch/inst/V/vlsseg7e8.v.yaml | 1 - arch/inst/V/vlsseg8e16.v.yaml | 1 - arch/inst/V/vlsseg8e32.v.yaml | 1 - arch/inst/V/vlsseg8e64.v.yaml | 1 - arch/inst/V/vlsseg8e8.v.yaml | 1 - arch/inst/V/vluxei16.v.yaml | 7 ++- arch/inst/V/vluxei32.v.yaml | 7 ++- arch/inst/V/vluxei64.v.yaml | 7 ++- arch/inst/V/vluxei8.v.yaml | 7 ++- arch/inst/V/vluxseg2ei16.v.yaml | 1 - arch/inst/V/vluxseg2ei32.v.yaml | 1 - arch/inst/V/vluxseg2ei64.v.yaml | 1 - arch/inst/V/vluxseg2ei8.v.yaml | 1 - arch/inst/V/vluxseg3ei16.v.yaml | 1 - arch/inst/V/vluxseg3ei32.v.yaml | 1 - arch/inst/V/vluxseg3ei64.v.yaml | 1 - arch/inst/V/vluxseg3ei8.v.yaml | 1 - arch/inst/V/vluxseg4ei16.v.yaml | 1 - arch/inst/V/vluxseg4ei32.v.yaml | 1 - arch/inst/V/vluxseg4ei64.v.yaml | 1 - arch/inst/V/vluxseg4ei8.v.yaml | 1 - arch/inst/V/vluxseg5ei16.v.yaml | 1 - arch/inst/V/vluxseg5ei32.v.yaml | 1 - arch/inst/V/vluxseg5ei64.v.yaml | 1 - arch/inst/V/vluxseg5ei8.v.yaml | 1 - arch/inst/V/vluxseg6ei16.v.yaml | 1 - arch/inst/V/vluxseg6ei32.v.yaml | 1 - arch/inst/V/vluxseg6ei64.v.yaml | 1 - arch/inst/V/vluxseg6ei8.v.yaml | 1 - arch/inst/V/vluxseg7ei16.v.yaml | 1 - arch/inst/V/vluxseg7ei32.v.yaml | 1 - arch/inst/V/vluxseg7ei64.v.yaml | 1 - arch/inst/V/vluxseg7ei8.v.yaml | 1 - arch/inst/V/vluxseg8ei16.v.yaml | 1 - arch/inst/V/vluxseg8ei32.v.yaml | 1 - arch/inst/V/vluxseg8ei64.v.yaml | 1 - arch/inst/V/vluxseg8ei8.v.yaml | 1 - arch/inst/V/vmacc.vv.yaml | 15 +++--- arch/inst/V/vmacc.vx.yaml | 15 +++--- arch/inst/V/vmadc.vi.yaml | 15 +++--- arch/inst/V/vmadc.vim.yaml | 15 +++--- arch/inst/V/vmadc.vv.yaml | 15 +++--- arch/inst/V/vmadc.vvm.yaml | 15 +++--- arch/inst/V/vmadc.vx.yaml | 15 +++--- arch/inst/V/vmadc.vxm.yaml | 15 +++--- arch/inst/V/vmadd.vv.yaml | 15 +++--- arch/inst/V/vmadd.vx.yaml | 15 +++--- arch/inst/V/vmand.mm.yaml | 15 +++--- arch/inst/V/vmandn.mm.yaml | 1 - arch/inst/V/vmax.vv.yaml | 15 +++--- arch/inst/V/vmax.vx.yaml | 15 +++--- arch/inst/V/vmaxu.vv.yaml | 15 +++--- arch/inst/V/vmaxu.vx.yaml | 15 +++--- arch/inst/V/vmerge.vim.yaml | 13 +++-- arch/inst/V/vmerge.vvm.yaml | 13 +++-- arch/inst/V/vmerge.vxm.yaml | 13 +++-- arch/inst/V/vmfeq.vf.yaml | 15 +++--- arch/inst/V/vmfeq.vv.yaml | 15 +++--- arch/inst/V/vmfge.vf.yaml | 15 +++--- arch/inst/V/vmfgt.vf.yaml | 15 +++--- arch/inst/V/vmfle.vf.yaml | 15 +++--- arch/inst/V/vmfle.vv.yaml | 15 +++--- arch/inst/V/vmflt.vf.yaml | 15 +++--- arch/inst/V/vmflt.vv.yaml | 15 +++--- arch/inst/V/vmfne.vf.yaml | 15 +++--- arch/inst/V/vmfne.vv.yaml | 15 +++--- arch/inst/V/vmin.vv.yaml | 15 +++--- arch/inst/V/vmin.vx.yaml | 15 +++--- arch/inst/V/vminu.vv.yaml | 15 +++--- arch/inst/V/vminu.vx.yaml | 15 +++--- arch/inst/V/vmnand.mm.yaml | 15 +++--- arch/inst/V/vmnor.mm.yaml | 15 +++--- arch/inst/V/vmor.mm.yaml | 15 +++--- arch/inst/V/vmorn.mm.yaml | 1 - arch/inst/V/vmsbc.vv.yaml | 15 +++--- arch/inst/V/vmsbc.vvm.yaml | 15 +++--- arch/inst/V/vmsbc.vx.yaml | 15 +++--- arch/inst/V/vmsbc.vxm.yaml | 15 +++--- arch/inst/V/vmsbf.m.yaml | 15 +++--- arch/inst/V/vmseq.vi.yaml | 15 +++--- arch/inst/V/vmseq.vv.yaml | 15 +++--- arch/inst/V/vmseq.vx.yaml | 15 +++--- arch/inst/V/vmsgt.vi.yaml | 15 +++--- arch/inst/V/vmsgt.vx.yaml | 15 +++--- arch/inst/V/vmsgtu.vi.yaml | 15 +++--- arch/inst/V/vmsgtu.vx.yaml | 15 +++--- arch/inst/V/vmsif.m.yaml | 15 +++--- arch/inst/V/vmsle.vi.yaml | 15 +++--- arch/inst/V/vmsle.vv.yaml | 15 +++--- arch/inst/V/vmsle.vx.yaml | 15 +++--- arch/inst/V/vmsleu.vi.yaml | 15 +++--- arch/inst/V/vmsleu.vv.yaml | 15 +++--- arch/inst/V/vmsleu.vx.yaml | 15 +++--- arch/inst/V/vmslt.vv.yaml | 15 +++--- arch/inst/V/vmslt.vx.yaml | 15 +++--- arch/inst/V/vmsltu.vv.yaml | 15 +++--- arch/inst/V/vmsltu.vx.yaml | 15 +++--- arch/inst/V/vmsne.vi.yaml | 15 +++--- arch/inst/V/vmsne.vv.yaml | 15 +++--- arch/inst/V/vmsne.vx.yaml | 15 +++--- arch/inst/V/vmsof.m.yaml | 15 +++--- arch/inst/V/vmul.vv.yaml | 15 +++--- arch/inst/V/vmul.vx.yaml | 15 +++--- arch/inst/V/vmulh.vv.yaml | 15 +++--- arch/inst/V/vmulh.vx.yaml | 15 +++--- arch/inst/V/vmulhsu.vv.yaml | 15 +++--- arch/inst/V/vmulhsu.vx.yaml | 15 +++--- arch/inst/V/vmulhu.vv.yaml | 15 +++--- arch/inst/V/vmulhu.vx.yaml | 15 +++--- arch/inst/V/vmv.s.x.yaml | 17 +++--- arch/inst/V/vmv.v.i.yaml | 15 +++--- arch/inst/V/vmv.v.v.yaml | 15 +++--- arch/inst/V/vmv.v.x.yaml | 15 +++--- arch/inst/V/vmv.x.s.yaml | 11 ++-- arch/inst/V/vmv1r.v.yaml | 13 +++-- arch/inst/V/vmv2r.v.yaml | 13 +++-- arch/inst/V/vmv4r.v.yaml | 13 +++-- arch/inst/V/vmv8r.v.yaml | 13 +++-- arch/inst/V/vmxnor.mm.yaml | 15 +++--- arch/inst/V/vmxor.mm.yaml | 15 +++--- arch/inst/V/vnclip.wi.yaml | 15 +++--- arch/inst/V/vnclip.wv.yaml | 15 +++--- arch/inst/V/vnclip.wx.yaml | 15 +++--- arch/inst/V/vnclipu.wi.yaml | 15 +++--- arch/inst/V/vnclipu.wv.yaml | 15 +++--- arch/inst/V/vnclipu.wx.yaml | 15 +++--- arch/inst/V/vnmsac.vv.yaml | 15 +++--- arch/inst/V/vnmsac.vx.yaml | 15 +++--- arch/inst/V/vnmsub.vv.yaml | 15 +++--- arch/inst/V/vnmsub.vx.yaml | 15 +++--- arch/inst/V/vnsra.wi.yaml | 15 +++--- arch/inst/V/vnsra.wv.yaml | 15 +++--- arch/inst/V/vnsra.wx.yaml | 15 +++--- arch/inst/V/vnsrl.wi.yaml | 15 +++--- arch/inst/V/vnsrl.wv.yaml | 15 +++--- arch/inst/V/vnsrl.wx.yaml | 15 +++--- arch/inst/V/vor.vi.yaml | 15 +++--- arch/inst/V/vor.vv.yaml | 15 +++--- arch/inst/V/vor.vx.yaml | 15 +++--- arch/inst/V/vredand.vs.yaml | 15 +++--- arch/inst/V/vredmax.vs.yaml | 15 +++--- arch/inst/V/vredmaxu.vs.yaml | 15 +++--- arch/inst/V/vredmin.vs.yaml | 15 +++--- arch/inst/V/vredminu.vs.yaml | 15 +++--- arch/inst/V/vredor.vs.yaml | 15 +++--- arch/inst/V/vredsum.vs.yaml | 15 +++--- arch/inst/V/vredxor.vs.yaml | 15 +++--- arch/inst/V/vrem.vv.yaml | 15 +++--- arch/inst/V/vrem.vx.yaml | 15 +++--- arch/inst/V/vremu.vv.yaml | 15 +++--- arch/inst/V/vremu.vx.yaml | 15 +++--- arch/inst/V/vrgather.vi.yaml | 15 +++--- arch/inst/V/vrgather.vv.yaml | 15 +++--- arch/inst/V/vrgather.vx.yaml | 15 +++--- arch/inst/V/vrgatherei16.vv.yaml | 15 +++--- arch/inst/V/vrsub.vi.yaml | 15 +++--- arch/inst/V/vrsub.vx.yaml | 15 +++--- arch/inst/V/vs1r.v.yaml | 1 - arch/inst/V/vs2r.v.yaml | 1 - arch/inst/V/vs4r.v.yaml | 1 - arch/inst/V/vs8r.v.yaml | 1 - arch/inst/V/vsadd.vi.yaml | 15 +++--- arch/inst/V/vsadd.vv.yaml | 15 +++--- arch/inst/V/vsadd.vx.yaml | 15 +++--- arch/inst/V/vsaddu.vi.yaml | 15 +++--- arch/inst/V/vsaddu.vv.yaml | 15 +++--- arch/inst/V/vsaddu.vx.yaml | 15 +++--- arch/inst/V/vsbc.vvm.yaml | 17 +++--- arch/inst/V/vsbc.vxm.yaml | 17 +++--- arch/inst/V/vse16.v.yaml | 7 ++- arch/inst/V/vse32.v.yaml | 7 ++- arch/inst/V/vse64.v.yaml | 7 ++- arch/inst/V/vse8.v.yaml | 7 ++- arch/inst/V/vsetivli.yaml | 13 +++-- arch/inst/V/vsetvl.yaml | 1 - arch/inst/V/vsetvli.yaml | 16 +++--- arch/inst/V/vsext.vf2.yaml | 15 +++--- arch/inst/V/vsext.vf4.yaml | 15 +++--- arch/inst/V/vsext.vf8.yaml | 15 +++--- arch/inst/V/vslide1down.vx.yaml | 15 +++--- arch/inst/V/vslide1up.vx.yaml | 15 +++--- arch/inst/V/vslidedown.vi.yaml | 15 +++--- arch/inst/V/vslidedown.vx.yaml | 15 +++--- arch/inst/V/vslideup.vi.yaml | 15 +++--- arch/inst/V/vslideup.vx.yaml | 15 +++--- arch/inst/V/vsll.vi.yaml | 15 +++--- arch/inst/V/vsll.vv.yaml | 15 +++--- arch/inst/V/vsll.vx.yaml | 15 +++--- arch/inst/V/vsm.v.yaml | 7 ++- arch/inst/V/vsmul.vv.yaml | 15 +++--- arch/inst/V/vsmul.vx.yaml | 15 +++--- arch/inst/V/vsoxei16.v.yaml | 7 ++- arch/inst/V/vsoxei32.v.yaml | 7 ++- arch/inst/V/vsoxei64.v.yaml | 7 ++- arch/inst/V/vsoxei8.v.yaml | 7 ++- arch/inst/V/vsoxseg2ei16.v.yaml | 1 - arch/inst/V/vsoxseg2ei32.v.yaml | 1 - arch/inst/V/vsoxseg2ei64.v.yaml | 1 - arch/inst/V/vsoxseg2ei8.v.yaml | 1 - arch/inst/V/vsoxseg3ei16.v.yaml | 1 - arch/inst/V/vsoxseg3ei32.v.yaml | 1 - arch/inst/V/vsoxseg3ei64.v.yaml | 1 - arch/inst/V/vsoxseg3ei8.v.yaml | 1 - arch/inst/V/vsoxseg4ei16.v.yaml | 1 - arch/inst/V/vsoxseg4ei32.v.yaml | 1 - arch/inst/V/vsoxseg4ei64.v.yaml | 1 - arch/inst/V/vsoxseg4ei8.v.yaml | 1 - arch/inst/V/vsoxseg5ei16.v.yaml | 1 - arch/inst/V/vsoxseg5ei32.v.yaml | 1 - arch/inst/V/vsoxseg5ei64.v.yaml | 1 - arch/inst/V/vsoxseg5ei8.v.yaml | 1 - arch/inst/V/vsoxseg6ei16.v.yaml | 1 - arch/inst/V/vsoxseg6ei32.v.yaml | 1 - arch/inst/V/vsoxseg6ei64.v.yaml | 1 - arch/inst/V/vsoxseg6ei8.v.yaml | 1 - arch/inst/V/vsoxseg7ei16.v.yaml | 1 - arch/inst/V/vsoxseg7ei32.v.yaml | 1 - arch/inst/V/vsoxseg7ei64.v.yaml | 1 - arch/inst/V/vsoxseg7ei8.v.yaml | 1 - arch/inst/V/vsoxseg8ei16.v.yaml | 1 - arch/inst/V/vsoxseg8ei32.v.yaml | 1 - arch/inst/V/vsoxseg8ei64.v.yaml | 1 - arch/inst/V/vsoxseg8ei8.v.yaml | 1 - arch/inst/V/vsra.vi.yaml | 15 +++--- arch/inst/V/vsra.vv.yaml | 15 +++--- arch/inst/V/vsra.vx.yaml | 15 +++--- arch/inst/V/vsrl.vi.yaml | 15 +++--- arch/inst/V/vsrl.vv.yaml | 15 +++--- arch/inst/V/vsrl.vx.yaml | 15 +++--- arch/inst/V/vsse16.v.yaml | 7 ++- arch/inst/V/vsse32.v.yaml | 7 ++- arch/inst/V/vsse64.v.yaml | 7 ++- arch/inst/V/vsse8.v.yaml | 7 ++- arch/inst/V/vsseg2e16.v.yaml | 1 - arch/inst/V/vsseg2e32.v.yaml | 1 - arch/inst/V/vsseg2e64.v.yaml | 1 - arch/inst/V/vsseg2e8.v.yaml | 1 - arch/inst/V/vsseg3e16.v.yaml | 1 - arch/inst/V/vsseg3e32.v.yaml | 1 - arch/inst/V/vsseg3e64.v.yaml | 1 - arch/inst/V/vsseg3e8.v.yaml | 1 - arch/inst/V/vsseg4e16.v.yaml | 1 - arch/inst/V/vsseg4e32.v.yaml | 1 - arch/inst/V/vsseg4e64.v.yaml | 1 - arch/inst/V/vsseg4e8.v.yaml | 1 - arch/inst/V/vsseg5e16.v.yaml | 1 - arch/inst/V/vsseg5e32.v.yaml | 1 - arch/inst/V/vsseg5e64.v.yaml | 1 - arch/inst/V/vsseg5e8.v.yaml | 1 - arch/inst/V/vsseg6e16.v.yaml | 1 - arch/inst/V/vsseg6e32.v.yaml | 1 - arch/inst/V/vsseg6e64.v.yaml | 1 - arch/inst/V/vsseg6e8.v.yaml | 1 - arch/inst/V/vsseg7e16.v.yaml | 1 - arch/inst/V/vsseg7e32.v.yaml | 1 - arch/inst/V/vsseg7e64.v.yaml | 1 - arch/inst/V/vsseg7e8.v.yaml | 1 - arch/inst/V/vsseg8e16.v.yaml | 1 - arch/inst/V/vsseg8e32.v.yaml | 1 - arch/inst/V/vsseg8e64.v.yaml | 1 - arch/inst/V/vsseg8e8.v.yaml | 1 - arch/inst/V/vssra.vi.yaml | 15 +++--- arch/inst/V/vssra.vv.yaml | 15 +++--- arch/inst/V/vssra.vx.yaml | 15 +++--- arch/inst/V/vssrl.vi.yaml | 15 +++--- arch/inst/V/vssrl.vv.yaml | 15 +++--- arch/inst/V/vssrl.vx.yaml | 15 +++--- arch/inst/V/vssseg2e16.v.yaml | 1 - arch/inst/V/vssseg2e32.v.yaml | 1 - arch/inst/V/vssseg2e64.v.yaml | 1 - arch/inst/V/vssseg2e8.v.yaml | 1 - arch/inst/V/vssseg3e16.v.yaml | 1 - arch/inst/V/vssseg3e32.v.yaml | 1 - arch/inst/V/vssseg3e64.v.yaml | 1 - arch/inst/V/vssseg3e8.v.yaml | 1 - arch/inst/V/vssseg4e16.v.yaml | 1 - arch/inst/V/vssseg4e32.v.yaml | 1 - arch/inst/V/vssseg4e64.v.yaml | 1 - arch/inst/V/vssseg4e8.v.yaml | 1 - arch/inst/V/vssseg5e16.v.yaml | 1 - arch/inst/V/vssseg5e32.v.yaml | 1 - arch/inst/V/vssseg5e64.v.yaml | 1 - arch/inst/V/vssseg5e8.v.yaml | 1 - arch/inst/V/vssseg6e16.v.yaml | 1 - arch/inst/V/vssseg6e32.v.yaml | 1 - arch/inst/V/vssseg6e64.v.yaml | 1 - arch/inst/V/vssseg6e8.v.yaml | 1 - arch/inst/V/vssseg7e16.v.yaml | 1 - arch/inst/V/vssseg7e32.v.yaml | 1 - arch/inst/V/vssseg7e64.v.yaml | 1 - arch/inst/V/vssseg7e8.v.yaml | 1 - arch/inst/V/vssseg8e16.v.yaml | 1 - arch/inst/V/vssseg8e32.v.yaml | 1 - arch/inst/V/vssseg8e64.v.yaml | 1 - arch/inst/V/vssseg8e8.v.yaml | 1 - arch/inst/V/vssub.vv.yaml | 15 +++--- arch/inst/V/vssub.vx.yaml | 15 +++--- arch/inst/V/vssubu.vv.yaml | 15 +++--- arch/inst/V/vssubu.vx.yaml | 15 +++--- arch/inst/V/vsub.vv.yaml | 15 +++--- arch/inst/V/vsub.vx.yaml | 15 +++--- arch/inst/V/vsuxei16.v.yaml | 7 ++- arch/inst/V/vsuxei32.v.yaml | 7 ++- arch/inst/V/vsuxei64.v.yaml | 7 ++- arch/inst/V/vsuxei8.v.yaml | 7 ++- arch/inst/V/vsuxseg2ei16.v.yaml | 1 - arch/inst/V/vsuxseg2ei32.v.yaml | 1 - arch/inst/V/vsuxseg2ei64.v.yaml | 1 - arch/inst/V/vsuxseg2ei8.v.yaml | 1 - arch/inst/V/vsuxseg3ei16.v.yaml | 1 - arch/inst/V/vsuxseg3ei32.v.yaml | 1 - arch/inst/V/vsuxseg3ei64.v.yaml | 1 - arch/inst/V/vsuxseg3ei8.v.yaml | 1 - arch/inst/V/vsuxseg4ei16.v.yaml | 1 - arch/inst/V/vsuxseg4ei32.v.yaml | 1 - arch/inst/V/vsuxseg4ei64.v.yaml | 1 - arch/inst/V/vsuxseg4ei8.v.yaml | 1 - arch/inst/V/vsuxseg5ei16.v.yaml | 1 - arch/inst/V/vsuxseg5ei32.v.yaml | 1 - arch/inst/V/vsuxseg5ei64.v.yaml | 1 - arch/inst/V/vsuxseg5ei8.v.yaml | 1 - arch/inst/V/vsuxseg6ei16.v.yaml | 1 - arch/inst/V/vsuxseg6ei32.v.yaml | 1 - arch/inst/V/vsuxseg6ei64.v.yaml | 1 - arch/inst/V/vsuxseg6ei8.v.yaml | 1 - arch/inst/V/vsuxseg7ei16.v.yaml | 1 - arch/inst/V/vsuxseg7ei32.v.yaml | 1 - arch/inst/V/vsuxseg7ei64.v.yaml | 1 - arch/inst/V/vsuxseg7ei8.v.yaml | 1 - arch/inst/V/vsuxseg8ei16.v.yaml | 1 - arch/inst/V/vsuxseg8ei32.v.yaml | 1 - arch/inst/V/vsuxseg8ei64.v.yaml | 1 - arch/inst/V/vsuxseg8ei8.v.yaml | 1 - arch/inst/V/vwadd.vv.yaml | 15 +++--- arch/inst/V/vwadd.vx.yaml | 15 +++--- arch/inst/V/vwadd.wv.yaml | 15 +++--- arch/inst/V/vwadd.wx.yaml | 15 +++--- arch/inst/V/vwaddu.vv.yaml | 15 +++--- arch/inst/V/vwaddu.vx.yaml | 15 +++--- arch/inst/V/vwaddu.wv.yaml | 15 +++--- arch/inst/V/vwaddu.wx.yaml | 15 +++--- arch/inst/V/vwmacc.vv.yaml | 15 +++--- arch/inst/V/vwmacc.vx.yaml | 15 +++--- arch/inst/V/vwmaccsu.vv.yaml | 15 +++--- arch/inst/V/vwmaccsu.vx.yaml | 15 +++--- arch/inst/V/vwmaccu.vv.yaml | 15 +++--- arch/inst/V/vwmaccu.vx.yaml | 15 +++--- arch/inst/V/vwmaccus.vx.yaml | 15 +++--- arch/inst/V/vwmul.vv.yaml | 15 +++--- arch/inst/V/vwmul.vx.yaml | 15 +++--- arch/inst/V/vwmulsu.vv.yaml | 15 +++--- arch/inst/V/vwmulsu.vx.yaml | 15 +++--- arch/inst/V/vwmulu.vv.yaml | 15 +++--- arch/inst/V/vwmulu.vx.yaml | 15 +++--- arch/inst/V/vwredsum.vs.yaml | 15 +++--- arch/inst/V/vwredsumu.vs.yaml | 15 +++--- arch/inst/V/vwsub.vv.yaml | 15 +++--- arch/inst/V/vwsub.vx.yaml | 15 +++--- arch/inst/V/vwsub.wv.yaml | 15 +++--- arch/inst/V/vwsub.wx.yaml | 15 +++--- arch/inst/V/vwsubu.vv.yaml | 15 +++--- arch/inst/V/vwsubu.vx.yaml | 15 +++--- arch/inst/V/vwsubu.wv.yaml | 15 +++--- arch/inst/V/vwsubu.wx.yaml | 15 +++--- arch/inst/V/vxor.vi.yaml | 15 +++--- arch/inst/V/vxor.vv.yaml | 15 +++--- arch/inst/V/vxor.vx.yaml | 15 +++--- arch/inst/V/vzext.vf2.yaml | 15 +++--- arch/inst/V/vzext.vf4.yaml | 15 +++--- arch/inst/V/vzext.vf8.yaml | 15 +++--- arch/inst/Zabha/amoadd.b.yaml | 5 +- arch/inst/Zabha/amoadd.h.yaml | 5 +- arch/inst/Zabha/amoand.b.yaml | 5 +- arch/inst/Zabha/amoand.h.yaml | 5 +- arch/inst/Zabha/amocas.b.yaml | 1 - arch/inst/Zabha/amocas.h.yaml | 1 - arch/inst/Zabha/amomax.b.yaml | 5 +- arch/inst/Zabha/amomax.h.yaml | 5 +- arch/inst/Zabha/amomaxu.b.yaml | 5 +- arch/inst/Zabha/amomaxu.h.yaml | 5 +- arch/inst/Zabha/amomin.b.yaml | 5 +- arch/inst/Zabha/amomin.h.yaml | 5 +- arch/inst/Zabha/amominu.b.yaml | 5 +- arch/inst/Zabha/amominu.h.yaml | 5 +- arch/inst/Zabha/amoor.b.yaml | 5 +- arch/inst/Zabha/amoor.h.yaml | 5 +- arch/inst/Zabha/amoswap.b.yaml | 5 +- arch/inst/Zabha/amoswap.h.yaml | 5 +- arch/inst/Zabha/amoxor.b.yaml | 5 +- arch/inst/Zabha/amoxor.h.yaml | 5 +- arch/inst/Zacas/amocas.d.yaml | 1 - arch/inst/Zacas/amocas.q.yaml | 1 - arch/inst/Zacas/amocas.w.yaml | 1 - arch/inst/Zalasr/lb.aq.yaml | 3 +- arch/inst/Zalasr/ld.aq.yaml | 3 +- arch/inst/Zalasr/lh.aq.yaml | 3 +- arch/inst/Zalasr/lw.aq.yaml | 3 +- arch/inst/Zalasr/sb.rl.yaml | 3 +- arch/inst/Zalasr/sd.rl.yaml | 3 +- arch/inst/Zalasr/sh.rl.yaml | 3 +- arch/inst/Zalasr/sw.rl.yaml | 3 +- arch/inst/Zawrs/wrs.nto.yaml | 1 - arch/inst/Zawrs/wrs.sto.yaml | 1 - arch/inst/Zbkb/brev8.yaml | 1 - arch/inst/Zbkb/unzip.yaml | 1 - arch/inst/Zbkb/zip.yaml | 1 - arch/inst/Zbkx/xperm4.yaml | 1 - arch/inst/Zbkx/xperm8.yaml | 1 - arch/inst/Zbp/gorci.yaml | 1 - arch/inst/Zbp/grevi.yaml | 1 - arch/inst/Zbp/shfli.yaml | 1 - arch/inst/Zbp/unshfli.yaml | 1 - arch/inst/Zbp/xperm16.yaml | 1 - arch/inst/Zbp/xperm32.yaml | 1 - arch/inst/Zcb/c.lbu.yaml | 2 +- arch/inst/Zcb/c.lh.yaml | 2 +- arch/inst/Zcb/c.lhu.yaml | 2 +- arch/inst/Zcb/c.mul.yaml | 4 -- arch/inst/Zcb/c.not.yaml | 6 +-- arch/inst/Zcb/c.sb.yaml | 2 +- arch/inst/Zcb/c.sext.b.yaml | 8 +-- arch/inst/Zcb/c.sext.h.yaml | 8 +-- arch/inst/Zcb/c.sh.yaml | 2 +- arch/inst/Zcb/c.zext.b.yaml | 6 +-- arch/inst/Zcb/c.zext.h.yaml | 6 +-- arch/inst/Zcb/c.zext.w.yaml | 6 +-- arch/inst/Zfbfmin/fcvt.bf16.s.yaml | 1 - arch/inst/Zfbfmin/fcvt.s.bf16.yaml | 1 - arch/inst/Zfh/fadd.h.yaml | 1 - arch/inst/Zfh/fclass.h.yaml | 1 - arch/inst/Zfh/fcvt.d.h.yaml | 1 - arch/inst/Zfh/fcvt.h.d.yaml | 1 - arch/inst/Zfh/fcvt.h.l.yaml | 1 - arch/inst/Zfh/fcvt.h.lu.yaml | 1 - arch/inst/Zfh/fcvt.h.s.yaml | 8 +-- arch/inst/Zfh/fcvt.h.w.yaml | 1 - arch/inst/Zfh/fcvt.h.wu.yaml | 1 - arch/inst/Zfh/fcvt.l.h.yaml | 1 - arch/inst/Zfh/fcvt.lu.h.yaml | 1 - arch/inst/Zfh/fcvt.s.h.yaml | 10 ++-- arch/inst/Zfh/fcvt.w.h.yaml | 1 - arch/inst/Zfh/fcvt.wu.h.yaml | 1 - arch/inst/Zfh/fdiv.h.yaml | 1 - arch/inst/Zfh/feq.h.yaml | 1 - arch/inst/Zfh/fle.h.yaml | 1 - arch/inst/Zfh/fleq.h.yaml | 1 - arch/inst/Zfh/flh.yaml | 4 -- arch/inst/Zfh/fli.h.yaml | 1 - arch/inst/Zfh/flt.h.yaml | 1 - arch/inst/Zfh/fltq.h.yaml | 1 - arch/inst/Zfh/fmadd.h.yaml | 1 - arch/inst/Zfh/fmax.h.yaml | 1 - arch/inst/Zfh/fmaxm.h.yaml | 1 - arch/inst/Zfh/fmin.h.yaml | 1 - arch/inst/Zfh/fminm.h.yaml | 1 - arch/inst/Zfh/fmsub.h.yaml | 1 - arch/inst/Zfh/fmul.h.yaml | 1 - arch/inst/Zfh/fmv.h.x.yaml | 4 -- arch/inst/Zfh/fmv.x.h.yaml | 6 +-- arch/inst/Zfh/fnmadd.h.yaml | 1 - arch/inst/Zfh/fnmsub.h.yaml | 1 - arch/inst/Zfh/fround.h.yaml | 1 - arch/inst/Zfh/froundnx.h.yaml | 1 - arch/inst/Zfh/fsgnj.h.yaml | 1 - arch/inst/Zfh/fsgnjn.h.yaml | 1 - arch/inst/Zfh/fsgnjx.h.yaml | 1 - arch/inst/Zfh/fsh.yaml | 6 +-- arch/inst/Zfh/fsqrt.h.yaml | 1 - arch/inst/Zfh/fsub.h.yaml | 1 - arch/inst/Zicbom/cbo.clean.yaml | 13 +++-- arch/inst/Zicbom/cbo.flush.yaml | 11 ++-- arch/inst/Zicbom/cbo.inval.yaml | 28 +++++----- arch/inst/Zicboz/cbo.zero.yaml | 12 ++--- arch/inst/Zicfilp/lpad.yaml | 1 - arch/inst/Zicfiss/ssamoswap.d.yaml | 1 - arch/inst/Zicfiss/ssamoswap.w.yaml | 1 - arch/inst/Zicfiss/sspopchk.x1.yaml | 1 - arch/inst/Zicfiss/sspopchk.x5.yaml | 1 - arch/inst/Zicfiss/sspush.x1.yaml | 1 - arch/inst/Zicfiss/sspush.x5.yaml | 1 - arch/inst/Zicfiss/ssrdp.yaml | 1 - arch/inst/Zicond/czero.eqz.yaml | 3 +- arch/inst/Zicond/czero.nez.yaml | 3 +- arch/inst/Zicsr/csrrc.yaml | 1 - arch/inst/Zicsr/csrrci.yaml | 1 - arch/inst/Zicsr/csrrs.yaml | 4 -- arch/inst/Zicsr/csrrsi.yaml | 1 - arch/inst/Zicsr/csrrw.yaml | 6 +-- arch/inst/Zicsr/csrrwi.yaml | 6 +-- arch/inst/Zifencei/fence.i.yaml | 4 -- arch/inst/Zimop/mop.r.n.yaml | 1 - arch/inst/Zimop/mop.rr.n.yaml | 1 - arch/inst/Zk/aes32dsi.yaml | 1 - arch/inst/Zk/aes32dsmi.yaml | 1 - arch/inst/Zk/aes32esi.yaml | 1 - arch/inst/Zk/aes32esmi.yaml | 1 - arch/inst/Zk/aes64ds.yaml | 1 - arch/inst/Zk/aes64dsm.yaml | 1 - arch/inst/Zk/aes64es.yaml | 1 - arch/inst/Zk/aes64esm.yaml | 1 - arch/inst/Zk/aes64im.yaml | 1 - arch/inst/Zk/aes64ks1i.yaml | 1 - arch/inst/Zk/aes64ks2.yaml | 1 - arch/inst/Zk/pack.yaml | 1 - arch/inst/Zk/packh.yaml | 1 - arch/inst/Zk/packw.yaml | 1 - arch/inst/Zk/sha256sig0.yaml | 1 - arch/inst/Zk/sha256sig1.yaml | 1 - arch/inst/Zk/sha256sum0.yaml | 1 - arch/inst/Zk/sha256sum1.yaml | 1 - arch/inst/Zk/sha512sig0.yaml | 1 - arch/inst/Zk/sha512sig0h.yaml | 1 - arch/inst/Zk/sha512sig0l.yaml | 1 - arch/inst/Zk/sha512sig1.yaml | 1 - arch/inst/Zk/sha512sig1h.yaml | 1 - arch/inst/Zk/sha512sig1l.yaml | 1 - arch/inst/Zk/sha512sum0.yaml | 1 - arch/inst/Zk/sha512sum0r.yaml | 1 - arch/inst/Zk/sha512sum1.yaml | 1 - arch/inst/Zk/sha512sum1r.yaml | 1 - arch/inst/Zks/sm3p0.yaml | 1 - arch/inst/Zks/sm3p1.yaml | 1 - arch/inst/Zks/sm4ed.yaml | 1 - arch/inst/Zks/sm4ks.yaml | 1 - arch/inst/Zvbb/vandn.vv.yaml | 1 - arch/inst/Zvbb/vandn.vx.yaml | 1 - arch/inst/Zvbb/vbrev.v.yaml | 1 - arch/inst/Zvbb/vbrev8.v.yaml | 1 - arch/inst/Zvbb/vclz.v.yaml | 1 - arch/inst/Zvbb/vcpop.v.yaml | 1 - arch/inst/Zvbb/vctz.v.yaml | 1 - arch/inst/Zvbb/vrev8.v.yaml | 1 - arch/inst/Zvbb/vrol.vv.yaml | 1 - arch/inst/Zvbb/vrol.vx.yaml | 1 - arch/inst/Zvbb/vror.vi.yaml | 1 - arch/inst/Zvbb/vror.vv.yaml | 1 - arch/inst/Zvbb/vror.vx.yaml | 1 - arch/inst/Zvbb/vwsll.vi.yaml | 1 - arch/inst/Zvbb/vwsll.vv.yaml | 1 - arch/inst/Zvbb/vwsll.vx.yaml | 1 - arch/inst/Zvbc/vclmul.vv.yaml | 1 - arch/inst/Zvbc/vclmul.vx.yaml | 1 - arch/inst/Zvbc/vclmulh.vv.yaml | 1 - arch/inst/Zvbc/vclmulh.vx.yaml | 1 - arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml | 1 - arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml | 1 - arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml | 1 - arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml | 1 - arch/inst/Zvkg/vghsh.vv.yaml | 1 - arch/inst/Zvkg/vgmul.vv.yaml | 1 - arch/inst/Zvkn/vaesdf.vs.yaml | 1 - arch/inst/Zvkn/vaesdf.vv.yaml | 1 - arch/inst/Zvkn/vaesdm.vs.yaml | 1 - arch/inst/Zvkn/vaesdm.vv.yaml | 1 - arch/inst/Zvkn/vaesef.vs.yaml | 1 - arch/inst/Zvkn/vaesef.vv.yaml | 1 - arch/inst/Zvkn/vaesem.vs.yaml | 1 - arch/inst/Zvkn/vaesem.vv.yaml | 1 - arch/inst/Zvkn/vaeskf1.vi.yaml | 1 - arch/inst/Zvkn/vaeskf2.vi.yaml | 1 - arch/inst/Zvkn/vaesz.vs.yaml | 1 - arch/inst/Zvkn/vsha2ch.vv.yaml | 1 - arch/inst/Zvkn/vsha2cl.vv.yaml | 1 - arch/inst/Zvkn/vsha2ms.vv.yaml | 1 - arch/inst/Zvks/vsm3c.vi.yaml | 1 - arch/inst/Zvks/vsm3me.vv.yaml | 1 - arch/inst/Zvks/vsm4k.vi.yaml | 1 - arch/inst/Zvks/vsm4r.vs.yaml | 1 - arch/inst/Zvks/vsm4r.vv.yaml | 1 - arch/isa/builtin_functions.idl | 6 +-- arch/isa/fp.idl | 4 +- arch/isa/globals.isa | 22 ++++---- arch/isa/util.idl | 4 +- arch/manual/isa/20240411/contents.yaml | 2 +- arch/manual/isa/isa.yaml | 2 +- arch/profile_class/MockProfileClass.yaml | 2 +- arch/profile_class/RVA.yaml | 22 ++++---- arch/profile_class/RVB.yaml | 2 +- arch/profile_class/RVI.yaml | 4 +- arch/profile_release/MockProfileRelease.yaml | 24 ++++----- arch/profile_release/RVA20.yaml | 6 +-- arch/profile_release/RVA22.yaml | 8 +-- arch/profile_release/RVI20.yaml | 12 ++--- arch/prose/idl.adoc | 24 ++++----- arch/prose/interrupts.adoc | 4 +- backends/arch_gen/lib/arch_gen.rb | 8 +-- backends/arch_gen/tasks.rake | 2 +- backends/certificate_doc/tasks.rake | 6 +-- .../templates/certificate.adoc.erb | 24 ++++----- backends/cfg_html_doc/templates/ext.adoc.erb | 4 +- backends/cfg_html_doc/templates/func.adoc.erb | 2 +- backends/cfg_html_doc/templates/inst.adoc.erb | 7 ++- .../cfg_html_doc/templates/landing.adoc.erb | 2 +- backends/cfg_html_doc/templates/toc.adoc.erb | 2 +- backends/ext_pdf_doc/idl_lexer.rb | 2 +- .../ext_pdf_doc/templates/ext_pdf.adoc.erb | 2 +- backends/manual/templates/csr.adoc.erb | 1 - backends/manual/templates/ext.adoc.erb | 2 +- backends/manual/templates/func.adoc.erb | 2 +- .../manual/templates/instruction.adoc.erb | 7 ++- .../templates/isa_version_index.adoc.erb | 1 - backends/manual/templates/param_list.adoc.erb | 2 +- backends/manual/templates/playbook.yml.erb | 2 +- .../portfolio_doc/templates/family_intro.erb | 2 +- .../profile_doc/templates/profile.adoc.erb | 12 ++--- bin/pre-commit | 1 - cfgs/_32/implemented_exts.yaml | 2 +- cfgs/_64/implemented_exts.yaml | 2 +- cfgs/config_validation.rb | 2 +- cfgs/generic_rv64/params.yaml | 4 +- docs/index.html | 2 +- lib/DB_MODEL.README.adoc | 6 +-- lib/arch_def.rb | 8 +-- lib/arch_obj_models/certificate.rb | 2 +- lib/arch_obj_models/csr.rb | 2 +- lib/arch_obj_models/csr_field.rb | 4 +- lib/arch_obj_models/extension.rb | 6 +-- lib/arch_obj_models/instruction.rb | 4 +- lib/arch_obj_models/obj.rb | 8 +-- lib/arch_obj_models/portfolio.rb | 32 ++++++------ lib/arch_obj_models/profile.rb | 6 +-- lib/arch_obj_models/schema.rb | 9 ++-- lib/asciidoc_extensions.js | 2 +- lib/idl/ast.rb | 16 +++--- lib/idl/idl.treetop | 4 +- lib/idl/passes/gen_adoc.rb | 2 +- lib/idl/passes/gen_option_adoc.rb | 2 +- lib/idl/passes/reachable_functions.rb | 2 +- lib/idl/symbol_table.rb | 4 +- lib/idl/tests/helpers.rb | 2 +- lib/idl/tests/test_lexer.rb | 4 +- lib/resolver.rb | 2 +- lib/test/test_yaml_loader.rb | 30 +++++------ lib/validate.rb | 2 +- lib/yaml_loader.rb | 4 +- lib/yaml_resolver.py | 2 +- schemas/cert_class_schema.json | 2 +- schemas/cert_model_schema.json | 2 +- schemas/csr_schema.json | 2 +- schemas/ext_schema.json | 6 +-- schemas/manual_version_schema.json | 2 +- schemas/schema_defs.json | 2 +- 1388 files changed, 3433 insertions(+), 5112 deletions(-) create mode 100644 .pre-commit-config.yaml diff --git a/.devcontainer/onCreateCommand.sh b/.devcontainer/onCreateCommand.sh index c51b5e23b..d4ecba051 100755 --- a/.devcontainer/onCreateCommand.sh +++ b/.devcontainer/onCreateCommand.sh @@ -1,4 +1,4 @@ #!/bin/bash -npm i +npm i bundle install diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 000000000..3063481e8 --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,14 @@ +--- +exclude: ^docs/ruby/ # All generated code + +repos: + - repo: https://github.com/pre-commit/pre-commit-hooks + rev: v5.0.0 + hooks: + - id: check-symlinks + - id: end-of-file-fixer + - id: trailing-whitespace + args: [--markdown-linebreak-ext=md] + - id: check-merge-conflict + args: ["--assume-in-merge"] + exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise diff --git a/LICENSE b/LICENSE index c7a4e51d5..c61afe239 100644 --- a/LICENSE +++ b/LICENSE @@ -18,7 +18,7 @@ met: NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN diff --git a/Rakefile b/Rakefile index bddeefd9d..84461cca2 100644 --- a/Rakefile +++ b/Rakefile @@ -98,7 +98,7 @@ namespace :test do validator.validate(f) end Rake::Task["test:insts"].invoke - puts "All files validate against their schema" + puts "All files validate against their schema" end task idl_model: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"] do print "Parsing IDL code for RV32..." @@ -298,7 +298,7 @@ namespace :test do ENV["MANUAL_NAME"] = "isa" ENV["VERSIONS"] = "all" Rake::Task["gen:html_manual"].invoke - + ENV["EXT"] = "B" ENV["VERSION"] = "latest" Rake::Task["gen:ext_pdf"].invoke @@ -371,4 +371,4 @@ namespace :gen do puts "===================================" Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke end -end \ No newline at end of file +end diff --git a/arch/README.adoc b/arch/README.adoc index 06f5c6859..185100f3b 100644 --- a/arch/README.adoc +++ b/arch/README.adoc @@ -21,7 +21,7 @@ To tame this challenge, this specification generator takes the following approac The architecture is specified in a series of https://en.wikipedia.org/wiki/YAML[YAML] files for _Extensions_, _Instructions_, and _Control and Status Registers (CSRs)_. -Each extension/instruction/CSR has its own file. +Each extension/instruction/CSR has its own file. == Flow diff --git a/arch/certificate_class/MC.yaml b/arch/certificate_class/MC.yaml index cf2d7512c..d31c7a25f 100644 --- a/arch/certificate_class/MC.yaml +++ b/arch/certificate_class/MC.yaml @@ -21,12 +21,12 @@ naming_scheme: | Where: - * Left & right square braces denote optional. + * Left & right square braces denote optional. * \ is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD. ** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond) ** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP) ** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H) - * \ is a semantic version (see semver.org) formatted as [..[patch]]. If \ is omitted, the reference applies equally to all versions. + * \ is a semantic version (see semver.org) formatted as [..[patch]]. If \ is omitted, the reference applies equally to all versions. ** A release indicates support for a new optional extension. ** A release indicates one or more of the following changes to the certification tests associated with the CRD. *** Fix test bug or increase test coverage @@ -35,4 +35,4 @@ naming_scheme: | ** A release indicates just CRD specification changes without any difference in functional behavior mandatory_priv_modes: -- M \ No newline at end of file +- M diff --git a/arch/certificate_model/MC100.yaml b/arch/certificate_model/MC100.yaml index a182de120..4589f965f 100644 --- a/arch/certificate_model/MC100.yaml +++ b/arch/certificate_model/MC100.yaml @@ -8,7 +8,7 @@ class: $ref: certificate_class/MC.yaml# # Semantic versions within the model -versions: +versions: - version: "1.0.0" # XLEN used by rakefile @@ -139,4 +139,4 @@ extensions: const: little XLEN: schema: - const: 32 \ No newline at end of file + const: 32 diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index 2f19b00b5..188a05b82 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -13,7 +13,7 @@ base: 64 # Semantic versions within the model versions: - version: "1.0.0" - - version: "1.1.0" + - version: "1.1.0" revision_history: - revision: "0.1.0" @@ -223,4 +223,4 @@ recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes. -- text: Micky should give Pluto an extra treat \ No newline at end of file +- text: Micky should give Pluto an extra treat diff --git a/arch/csr/F/fcsr.yaml b/arch/csr/F/fcsr.yaml index 3948be255..a44a5b39c 100644 --- a/arch/csr/F/fcsr.yaml +++ b/arch/csr/F/fcsr.yaml @@ -42,7 +42,7 @@ description: | modes are encoded as shown in <>. A value of 111 in the instruction's _rm_ field selects the dynamic rounding mode held in `frm`. The behavior of floating-point instructions that depend on - rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to + rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). @@ -122,7 +122,7 @@ fields: including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the - rounding mode; software should set their _rm_ field to + rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). type: RW-H @@ -181,4 +181,4 @@ fields: Set by hardware when a floating point operation is inexact and stays set until explicitly cleared by software. type: RW-H - reset_value: UNDEFINED_LEGAL \ No newline at end of file + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/H/henvcfg.yaml b/arch/csr/H/henvcfg.yaml index 8086aec41..462bc0f13 100644 --- a/arch/csr/H/henvcfg.yaml +++ b/arch/csr/H/henvcfg.yaml @@ -12,7 +12,7 @@ description: | If bit `henvcfg.FIOM` (Fence of I/O implies Memory) is set to one in henvcfg, `fence` instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. - + <> details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1. @@ -71,7 +71,7 @@ description: | The Zicfiss extension adds the `SSE` field in `henvcfg`. If the `SSE` field is set to 1, the Zicfiss extension is activated in VS-mode. When the `SSE` field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules - apply when `V=1`: + apply when `V=1`: * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. @@ -127,12 +127,12 @@ fields: The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage address translation. - + When PBMTE=1, Svpbmt is available for VS-stage address translation. - + When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for VS-stage address translation. - + If `Svpbmt` is not implemented, PBMTE is read-only zero. `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero. @@ -141,7 +141,7 @@ fields: _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT fields. - By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with + By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT fields for the currently active VMID. @@ -165,14 +165,14 @@ fields: description: | If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation. - + When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation. - + When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation. - + If Svadu is not implemented, ADUE is read-only zero. Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only @@ -287,4 +287,4 @@ sw_read(): | # henvcfg.ADUE must read-as-zero value = value & ~(1 << 61); } - return value; \ No newline at end of file + return value; diff --git a/arch/csr/H/henvcfgh.yaml b/arch/csr/H/henvcfgh.yaml index 692e159fe..3b45ec2d4 100644 --- a/arch/csr/H/henvcfgh.yaml +++ b/arch/csr/H/henvcfgh.yaml @@ -47,12 +47,12 @@ fields: The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage address translation. - + When PBMTE=1, Svpbmt is available for VS-stage address translation. - + When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for VS-stage address translation. - + If `Svpbmt` is not implemented, PBMTE is read-only zero. `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero. @@ -61,7 +61,7 @@ fields: _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT fields. - By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with + By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT fields for the currently active VMID. @@ -86,14 +86,14 @@ fields: description: | If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation. - + When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation. - + When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation. - + If Svadu is not implemented, ADUE is read-only zero. Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only @@ -104,4 +104,4 @@ fields: reset_value(): | return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; sw_read(): | - return CSR[henvcfg].sw_read()[63:32]; \ No newline at end of file + return CSR[henvcfg].sw_read()[63:32]; diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 01bb120e1..43a84b54a 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -225,7 +225,7 @@ fields: return csr_value.PPN; sw_read(): | - if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4)) + if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv39x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv48x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv57x4))) { @@ -233,4 +233,4 @@ sw_read(): | return $bits(CSR[hgatp]) & ~64'h3; } else { return $bits(CSR[hgatp]); - } \ No newline at end of file + } diff --git a/arch/csr/H/vsatp.yaml b/arch/csr/H/vsatp.yaml index d95e56e45..fef44032c 100644 --- a/arch/csr/H/vsatp.yaml +++ b/arch/csr/H/vsatp.yaml @@ -127,7 +127,7 @@ fields: reset_value: UNDEFINED_LEGAL sw_write(csr_value): | if (csr_value.MODE == 0) { - if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) { + if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) { # when MODE == Bare, PPN and ASID must be zero if (csr_value.ASID == 0 && csr_value.PPN == 0) { return csr_value.PPN; diff --git a/arch/csr/I/pmpaddrN.layout b/arch/csr/I/pmpaddrN.layout index d42a4cb5c..076b1d34e 100644 --- a/arch/csr/I/pmpaddrN.layout +++ b/arch/csr/I/pmpaddrN.layout @@ -1,6 +1,6 @@ # yaml-language-server: $schema=../../../schemas/csr_schema.json -<%- +<%- raise "'pmpaddr_num' must be defined" if pmpaddr_num.nil? pmpcfg_num_32 = (pmpaddr_num / 4) pmpcfg_num_64 = (pmpaddr_num / 8)*2 diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index b1a599b02..51714e954 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index b4dd1bb58..44e262a69 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index b44572844..aa4343c0f 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index cd94a72b1..7ba8d05b6 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index fa1e34583..8897f4db9 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index 207a5aa77..aa151be42 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index f17cc62b1..e5c4744d4 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 8b267586b..43454115e 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index 5a502d96b..bad4210e8 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index d1a704789..31f5a4806 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index ae6a9c6b5..d55346cc5 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index 95585e539..3b9e2477c 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index 6fe859fb6..a7ab336b6 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index 2639b5870..bebd1871e 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index 7cb54f73c..fa3b0fbd4 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index d8daa4a91..6fccacb66 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfgN.layout b/arch/csr/I/pmpcfgN.layout index 9c76a61fc..571f75097 100644 --- a/arch/csr/I/pmpcfgN.layout +++ b/arch/csr/I/pmpcfgN.layout @@ -34,7 +34,7 @@ fields: h! - ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! _Reserved_ Writes shall be ignored. h! A ! <%= ((i+1)*8)-4 %>:<%= ((i+1)*8)-5 %> a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -48,7 +48,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! <%= ((i)*8)+2 %> ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! <%= ((i)*8)+1 %> ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! <%= ((i)*8)+0 %> ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/Zicntr/mcountinhibit.layout b/arch/csr/Zicntr/mcountinhibit.layout index 01d8a4bce..549b2061e 100644 --- a/arch/csr/Zicntr/mcountinhibit.layout +++ b/arch/csr/Zicntr/mcountinhibit.layout @@ -74,4 +74,4 @@ fields: return COUNTINHIBIT_EN[<%= hpm_num %>] ? CsrFieldType::RW : CsrFieldType::RO; reset_value(): | return COUNTINHIBIT_EN[<%= hpm_num %>] ? UNDEFINED_LEGAL : 0; - <%- end -%> \ No newline at end of file + <%- end -%> diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index f88d8c047..73b4b9c3c 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter10` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM10`# - ^.>h! `hpmcounter10` behavior + ^.>h! `hpmcounter10` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 4f524ae5a..682f95116 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter10h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index f0b6df2c0..0cd3adbd9 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter11` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM11`# - ^.>h! `hpmcounter11` behavior + ^.>h! `hpmcounter11` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index ae1d606a7..d710fcfb1 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter11h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index ac643a168..940be2a1a 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter12` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM12`# - ^.>h! `hpmcounter12` behavior + ^.>h! `hpmcounter12` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index 3f4cda485..da1b60847 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter12h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 68a8c0e12..251679470 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter13` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM13`# - ^.>h! `hpmcounter13` behavior + ^.>h! `hpmcounter13` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 938204ac0..4f7ad9c11 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter13h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index c547b8d74..c65d0acd8 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter14` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM14`# - ^.>h! `hpmcounter14` behavior + ^.>h! `hpmcounter14` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 79877a08f..f5da64665 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter14h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index 418b7c3cd..0a1eeda23 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter15` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM15`# - ^.>h! `hpmcounter15` behavior + ^.>h! `hpmcounter15` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index bba8da3d1..0349cceaa 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter15h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index 4c46e4ab6..fef98c2a2 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter16` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM16`# - ^.>h! `hpmcounter16` behavior + ^.>h! `hpmcounter16` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 5e7db6fe5..350f8f88d 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter16h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index bcc2844fd..4326683c3 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter17` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM17`# - ^.>h! `hpmcounter17` behavior + ^.>h! `hpmcounter17` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index de64d2915..7d77d8dba 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter17h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index 35219de64..365ea8889 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter18` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM18`# - ^.>h! `hpmcounter18` behavior + ^.>h! `hpmcounter18` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 794dddb2b..1714bdddd 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter18h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index e1e9e8714..abeb3c0ae 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter19` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM19`# - ^.>h! `hpmcounter19` behavior + ^.>h! `hpmcounter19` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index 84f6a8339..fe8d94677 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter19h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index 5db4a0a99..a92640605 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter20` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM20`# - ^.>h! `hpmcounter20` behavior + ^.>h! `hpmcounter20` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 692e695be..db31015b8 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter20h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index ac6a44772..3d8ba93b2 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter21` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM21`# - ^.>h! `hpmcounter21` behavior + ^.>h! `hpmcounter21` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 6c6cd2838..57db30d76 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter21h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index c422add0d..a2db1a461 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter22` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM22`# - ^.>h! `hpmcounter22` behavior + ^.>h! `hpmcounter22` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index f67e7df7a..c6f5555fc 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter22h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index 600270bd6..e8c4b5ff4 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter23` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM23`# - ^.>h! `hpmcounter23` behavior + ^.>h! `hpmcounter23` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index fab756b4c..e6b261d23 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter23h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index e30a48ff4..5a214615d 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter24` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM24`# - ^.>h! `hpmcounter24` behavior + ^.>h! `hpmcounter24` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index 9d255c1fa..9602adfb4 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter24h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index 0022adae0..d10352ccd 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter25` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM25`# - ^.>h! `hpmcounter25` behavior + ^.>h! `hpmcounter25` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index a91731b4b..f77f95c9b 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter25h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index e018ddd3e..778d77da5 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter26` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM26`# - ^.>h! `hpmcounter26` behavior + ^.>h! `hpmcounter26` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 439495746..346866402 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter26h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index f4c4bfa21..1e3014f54 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter27` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM27`# - ^.>h! `hpmcounter27` behavior + ^.>h! `hpmcounter27` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 77ebfae20..bf683b7f9 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter27h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index 04e32bed2..f0359b73c 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter28` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM28`# - ^.>h! `hpmcounter28` behavior + ^.>h! `hpmcounter28` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index bd79376a8..635ba7b1e 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter28h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index 504ce545a..479cae002 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter29` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM29`# - ^.>h! `hpmcounter29` behavior + ^.>h! `hpmcounter29` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index 708c0095b..7c76ca624 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter29h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index e0ef755ed..99907b9b8 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter3` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM3`# - ^.>h! `hpmcounter3` behavior + ^.>h! `hpmcounter3` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 205e9d6f9..855b1087c 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter30` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM30`# - ^.>h! `hpmcounter30` behavior + ^.>h! `hpmcounter30` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index f80aca0db..10e30fa68 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter30h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 8682dd896..64aa6a664 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter31` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM31`# - ^.>h! `hpmcounter31` behavior + ^.>h! `hpmcounter31` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index b84202355..07bf78fe6 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter31h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 11acfe0f8..ea664cc42 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter3h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index 0947a5f15..06d2d04cb 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter4` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM4`# - ^.>h! `hpmcounter4` behavior + ^.>h! `hpmcounter4` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index b5920dd61..47951185a 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter4h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index 93c4ab78f..ff0ce06fa 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter5` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM5`# - ^.>h! `hpmcounter5` behavior + ^.>h! `hpmcounter5` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index f637926f6..354e4465a 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter5h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index ad2646d52..dd153ff5a 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter6` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM6`# - ^.>h! `hpmcounter6` behavior + ^.>h! `hpmcounter6` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 83996abc5..238c4e628 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter6h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index 103aa95ff..b350ebbd6 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter7` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM7`# - ^.>h! `hpmcounter7` behavior + ^.>h! `hpmcounter7` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 37ee38eab..27b2468c8 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter7h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index 3a1000472..7c4a50d31 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter8` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM8`# - ^.>h! `hpmcounter8` behavior + ^.>h! `hpmcounter8` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index bbba142d7..5eb7fcf05 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter8h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 1a62dc357..91fbcf184 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter9` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM9`# - ^.>h! `hpmcounter9` behavior + ^.>h! `hpmcounter9` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index daa0da012..8a9e203c7 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter9h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounterN.layout b/arch/csr/Zihpm/hpmcounterN.layout index feba9813c..c273c374e 100644 --- a/arch/csr/Zihpm/hpmcounterN.layout +++ b/arch/csr/Zihpm/hpmcounterN.layout @@ -26,10 +26,10 @@ description: | 4+^.>h! `hpmcounter<%= hpm_num %>` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%%- elsif ext?(:S) -%> @@ -47,7 +47,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM<%= hpm_num %>`# - ^.>h! `hpmcounter<%= hpm_num %>` behavior + ^.>h! `hpmcounter<%= hpm_num %>` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounterNh.layout b/arch/csr/Zihpm/hpmcounterNh.layout index 8a6274727..b573d35b8 100644 --- a/arch/csr/Zihpm/hpmcounterNh.layout +++ b/arch/csr/Zihpm/hpmcounterNh.layout @@ -18,10 +18,10 @@ description: | 4+^.>h! `hpmcounter<%= hpm_num %>h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index d0921b108..d020a06c0 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(10)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 480175167..51e1157b1 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(11)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 9b376187f..552478c7b 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(12)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index 2fa48f8d3..de931ede3 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(13)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index 02a78cf6f..fad4f5d6e 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(14)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 6c2694f66..56080a49c 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(15)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index 2efc26bc1..040cf26b5 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(16)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 6983f5a66..913a81271 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(17)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index 2c55efb86..b8dd73f0b 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(18)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 6810df997..306eea43c 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(19)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 00373df91..7366268de 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(20)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index e1759442d..8686eab27 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(21)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index de6284ce5..f4049e79c 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(22)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 5208fa471..9152e9d9a 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(23)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index 76808b2a6..55bdde30a 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(24)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index 1829aca09..3d136816b 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(25)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index 3ea26055d..b98d78a8c 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(26)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index 750305e5a..b45fd8ebe 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(27)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index d210f2a60..2167cc2e9 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(28)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index 5f493f590..e924c6460 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(29)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index 387568c41..603f63f89 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(30)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index 8d4922a73..da1da7a17 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(31)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index bd9d3e556..cd0e5dd7c 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(3)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index 94ee0f926..ca888f72e 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(4)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index 87008b5f8..88ef7737f 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(5)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index c51a0f487..6907ddba6 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(6)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 0d05d9c9c..08aa55fb7 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(7)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 0df82e412..8ae9a5aed 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(8)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index b3bb95d7c..9081f053b 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(9)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounterNh.layout b/arch/csr/Zihpm/mhpmcounterNh.layout index b9f4b2f14..4c9c42f16 100644 --- a/arch/csr/Zihpm/mhpmcounterNh.layout +++ b/arch/csr/Zihpm/mhpmcounterNh.layout @@ -26,4 +26,4 @@ sw_read(): | return read_hpm_counter(<%= hpm_num %>)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/cycle.yaml b/arch/csr/cycle.yaml index 50084c604..99824ed6e 100644 --- a/arch/csr/cycle.yaml +++ b/arch/csr/cycle.yaml @@ -16,10 +16,10 @@ description: | 4+^.>h! `cycle` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/cycleh.yaml b/arch/csr/cycleh.yaml index 2c2f664d4..720e4b341 100644 --- a/arch/csr/cycleh.yaml +++ b/arch/csr/cycleh.yaml @@ -17,10 +17,10 @@ description: | 4+^.>h! `cycle` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index eb2c5940d..c14c19331 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -90,7 +90,7 @@ fields: amount of time (which can be 0). When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction - executes in VS-mode without a timeout period. + executes in VS-mode without a timeout period. The `wfi` instruction is also affected by `mstatus.TW`, as shown below: @@ -99,7 +99,7 @@ fields: .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior h! HS-mode h! U-mode h! VS-mode h! VU-mode - ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V) + ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V) ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V) ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I) diff --git a/arch/csr/instret.yaml b/arch/csr/instret.yaml index 7f45d0160..779f47c5f 100644 --- a/arch/csr/instret.yaml +++ b/arch/csr/instret.yaml @@ -16,10 +16,10 @@ description: | 4+^.>h! `instret` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U @@ -68,4 +68,4 @@ sw_read(): | } } - return CSR[minstret].COUNT; \ No newline at end of file + return CSR[minstret].COUNT; diff --git a/arch/csr/instreth.yaml b/arch/csr/instreth.yaml index f4a610ccb..7a850f01a 100644 --- a/arch/csr/instreth.yaml +++ b/arch/csr/instreth.yaml @@ -17,10 +17,10 @@ description: | 4+^.>h! `instret` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U @@ -71,4 +71,4 @@ sw_read(): | # since the counter may be shared among harts, reads must be handled # as a builtin function - return read_mcycle(); \ No newline at end of file + return read_mcycle(); diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index 5f64818bf..a097a3f0e 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -16,7 +16,7 @@ fields: location_rv64: 63 description: | Written by hardware when a trap is taken into M-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `mcause.INT` is writeable. diff --git a/arch/csr/medeleg.yaml b/arch/csr/medeleg.yaml index 16a7b6c5c..275796660 100644 --- a/arch/csr/medeleg.yaml +++ b/arch/csr/medeleg.yaml @@ -67,7 +67,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -104,7 +104,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> @@ -142,7 +142,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -179,7 +179,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -220,7 +220,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> @@ -258,9 +258,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -300,9 +300,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -338,9 +338,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL EU: @@ -375,9 +375,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -401,7 +401,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! (H)S + ! 1 ! M ! (H)S !=== type: RW reset_value: UNDEFINED_LEGAL @@ -425,7 +425,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! (H)S + ! 1 ! M ! (H)S !=== type: RW reset_value: UNDEFINED_LEGAL @@ -472,9 +472,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL LPF: @@ -509,9 +509,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -547,9 +547,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL IGPF: @@ -572,7 +572,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW reset_value: UNDEFINED_LEGAL @@ -597,7 +597,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW @@ -623,7 +623,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW @@ -649,7 +649,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/menvcfg.yaml b/arch/csr/menvcfg.yaml index 31b2d7e99..49d263d8b 100644 --- a/arch/csr/menvcfg.yaml +++ b/arch/csr/menvcfg.yaml @@ -176,7 +176,7 @@ fields: updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation. - + When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation. When ADUE=0, the diff --git a/arch/csr/menvcfgh.yaml b/arch/csr/menvcfgh.yaml index 20e5308c0..41aa7f816 100644 --- a/arch/csr/menvcfgh.yaml +++ b/arch/csr/menvcfgh.yaml @@ -19,7 +19,7 @@ fields: alias: menvcfg.STCE description: | *STimecmp Enable* - + Alias of `menvcfg.STCE` definedBy: Sstc type: RW @@ -43,4 +43,4 @@ fields: type(): | return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RO : CsrFieldType::RW; reset_value(): | - return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; \ No newline at end of file + return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; diff --git a/arch/csr/mepc.yaml b/arch/csr/mepc.yaml index 7d291543d..b08d8ebda 100644 --- a/arch/csr/mepc.yaml +++ b/arch/csr/mepc.yaml @@ -45,4 +45,4 @@ sw_read(): | return CSR[mepc].PC & ~64'b1; } else { return CSR[mepc].PC; - } \ No newline at end of file + } diff --git a/arch/csr/mhartid.yaml b/arch/csr/mhartid.yaml index 1e5425801..8b5e50793 100644 --- a/arch/csr/mhartid.yaml +++ b/arch/csr/mhartid.yaml @@ -17,4 +17,4 @@ fields: description: hart-specific ID. reset_value: UNDEFINED_LEGAL sw_read(): | - return hartid(); \ No newline at end of file + return hartid(); diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index c8d408f1d..dab340dce 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -26,7 +26,7 @@ description: | appropriate level with the `MRET` instruction. To increase performance, implementations can provide individual read/write bits within `mideleg` to indicate that certain exceptions and interrupts should - be processed directly by a lower privilege level. + be processed directly by a lower privilege level. In harts with S-mode, the `mideleg` register must exist, and setting a bit `mideleg` will delegate the @@ -104,7 +104,7 @@ fields: *Virtual Supervisor Software Interrupt delegation* When 1, Virtual Supervisor Software interrupts are delegated to HS-mode. - + Virtual Supervisor Software Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 @@ -113,7 +113,7 @@ fields: location: 3 description: | *Machine Software interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -121,7 +121,7 @@ fields: location: 5 description: | *Supervisor Timer interrupt delegation* - + When 1, Supervisor Timer interrupts are delegated to HS/S-mode. type: RW reset_value: 0 @@ -131,7 +131,7 @@ fields: *Virutal Supervisor Timer interrupt delegation* When 1, Virtual Supervisor Timer interrupts are delegated to HS-mode. - + Virtual Supervisor Time Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 @@ -140,7 +140,7 @@ fields: location: 7 description: | *Machine Timer interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -148,7 +148,7 @@ fields: location: 9 description: | *Supervisor External interrupt delegation* - + When 1, Supervisor External interrupts are delegated to HS/S-mode. type: RW reset_value: 0 @@ -165,7 +165,7 @@ fields: location: 11 description: | *Machine External interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -173,7 +173,7 @@ fields: location: 12 description: | *Supervisor Guest External Interrupt delegation* - + Supervisor Guest External interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 diff --git a/arch/csr/mie.yaml b/arch/csr/mie.yaml index 2a51b862d..927ed583c 100644 --- a/arch/csr/mie.yaml +++ b/arch/csr/mie.yaml @@ -8,7 +8,7 @@ address: 0x304 priv_mode: M length: MXLEN definedBy: Sm -description: +description: $copy: "mip.yaml#/description" fields: SSIE: @@ -134,4 +134,4 @@ fields: Alias of `vsip.LCOFIE` when `hideleg.LCOFI` is set. Otherwise, `vsip.LCOFIE` is read-only 0. type: RW definedBy: Sscofpmf - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/mimpid.yaml b/arch/csr/mimpid.yaml index 228953b37..4d35e45c7 100644 --- a/arch/csr/mimpid.yaml +++ b/arch/csr/mimpid.yaml @@ -32,4 +32,4 @@ fields: location_rv64: 63-0 type: RO description: Vendor-specific implementation ID. - reset_value(): return IMP_ID; \ No newline at end of file + reset_value(): return IMP_ID; diff --git a/arch/csr/minstreth.yaml b/arch/csr/minstreth.yaml index 0d3f71ccb..9930ef02d 100644 --- a/arch/csr/minstreth.yaml +++ b/arch/csr/minstreth.yaml @@ -28,4 +28,4 @@ fields: return csr_value.COUNT; definedBy: Zicntr sw_read(): | - return CSR[minstret].COUNT[63:32]; \ No newline at end of file + return CSR[minstret].COUNT[63:32]; diff --git a/arch/csr/mip.yaml b/arch/csr/mip.yaml index b1e77a627..5dd94ffb0 100644 --- a/arch/csr/mip.yaml +++ b/arch/csr/mip.yaml @@ -14,11 +14,11 @@ description: | Note that the CLINT refers to an interrupt controller used by some RISC-V implementations but isn't a ratified RISC-V International standard. - + The `mip` CSR contains information on pending interrupts, while `mie` is the corresponding CSR containing interrupt enable bits. Interrupt cause number _i_ (as reported in the `mcause` CSR) - corresponds to bit _i_ in both `mip` and `mie`. + corresponds to bit _i_ in both `mip` and `mie`. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. @@ -26,7 +26,7 @@ description: | at the platform's discretion. An interrupt _i_ will trap to M-mode (causing the privilege mode to - change to M-mode) if all of the following are true: + change to M-mode) if all of the following are true: * either the current privilege mode is M and the MIE bit in the `mstatus` register is set, or the current privilege mode has less privilege than M-mode; @@ -261,7 +261,7 @@ fields: - hip.VSTIP description: | *Virtual Supervisor Timer Interrupt Pending* - + Reports the current pending state of a VS-mode timer interrupt <%- if ext?(:Sstc) -%> , which is normally controlled by the `vstimecmp` CSR, but can also be injected by the hypervisor through `hvip.VSTIP`. @@ -294,7 +294,7 @@ fields: location: 7 description: | *Machine Timer Interrupt Pending* - + Reports the current pending state of an M-mode timer interrupt. Bit is controlled by the timer device (using `mtimecmp`), and is not writeable. @@ -357,7 +357,7 @@ fields: *Machine External Interrupt Pending* Reports the current pending state of an M-mode external interrupt. - + MEIP is controlled by the external interrupt controller <% if ext?(:Smaia) %>(AIA) <% end %>. It is not writable by software. type: RO-H @@ -402,4 +402,4 @@ fields: <%- end -%> type: RW-H reset_value: 0 - definedBy: Sscofpmf \ No newline at end of file + definedBy: Sscofpmf diff --git a/arch/csr/misa.yaml b/arch/csr/misa.yaml index 7b9f06b70..5b3674d80 100644 --- a/arch/csr/misa.yaml +++ b/arch/csr/misa.yaml @@ -184,4 +184,3 @@ sw_read(): | (CSR[misa].C << 2) | (CSR[misa].B << 1) | CSR[misa].A); - \ No newline at end of file diff --git a/arch/csr/mscratch.yaml b/arch/csr/mscratch.yaml index 9a95af596..544b6bce0 100644 --- a/arch/csr/mscratch.yaml +++ b/arch/csr/mscratch.yaml @@ -15,4 +15,4 @@ fields: location_rv64: 63-0 description: Scratch value type: RW - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index 9461de08a..f496aa1ac 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -20,7 +20,7 @@ fields: location_rv64: 63 description: | State Dirty. - + Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state. definedBy: @@ -74,7 +74,7 @@ fields: base: 64 description: | *M-mode Big Endian* - + Controls the endianness of data M-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -96,7 +96,7 @@ fields: definedBy: S description: | *S-mode Big Endian* - + Controls the endianness of S-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -123,7 +123,7 @@ fields: definedBy: S description: | *S-mode XLEN* - + Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]). [when,"SXLEN==32"] @@ -135,9 +135,9 @@ fields: [when,"SXLEN=3264"] -- It is not valid to have SXLEN less than UXLEN. - + It is UNDEFINED_LEGAL what will happen if a software sets `mstatus.SXL` to be greater than `mstatus.UXL`. - + It is UNDEFINED_LEGAL to set the MSB of SXL. -- type(): | @@ -172,7 +172,7 @@ fields: definedBy: U description: | U-mode XLEN. - + Sets the effective XLEN for U-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]). [when,"UXLEN == 32"] @@ -185,9 +185,9 @@ fields: [when,"UXLEN == 3264"] -- It is not valid to have SXLEN less than UXLEN. - + It is UNDEFINED_LEGAL what will happen if a software sets `mstatus.SXL` to be greater than `mstatus.UXL`. - + It is UNDEFINED_LEGAL to set the MSB of UXL. -- type(): | @@ -210,7 +210,7 @@ fields: return csr_value.UXL == 1; } else { return csr_value.UXL <= 1; - } + } reset_value(): | if (UXLEN == 32) { @@ -258,7 +258,7 @@ fields: * writing the `hgtap` CSR, executing an `hfence.gvma`, or executing an `hinval.gvma` while in HS-mode Notably, `mstatus.TVM` does *not* cause - + *`hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap. * Any additional traps in VS-mode (controlled via `hstatus.VTVM` instead). @@ -289,7 +289,7 @@ fields: location: 19 description: | Make eXecutable Readable. - + When 1, loads from pages marked readable *or executable* are allowed. When 0, loads from pages marked executable raise a Page Fault exception. definedBy: S @@ -299,7 +299,7 @@ fields: location: 18 description: | permit Supervisor Memory Access. - + When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01 to a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception. definedBy: S @@ -321,7 +321,7 @@ fields: location: 17 description: | Modify PRiVilege. - + When 1, loads and stores behave as if the current virutalization mode:privilege level was `mstatus.MPV`:`mstatus.MPP`. @@ -334,7 +334,7 @@ fields: location: 16-15 description: | *Custom (X) extension context Status* - + Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions in the base spec, this field is read-only 0. @@ -344,12 +344,12 @@ fields: location: 14-13 description: | Floating point context status. - + When 0, floating point instructions (from F and D extensions) are disabled, and cause `ILLEGAL INSTRUCTION` exceptions. When a floating point register, or the fCSR register is written, FS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware - other than to possibly enable a previously-disabled floating point unit. + other than to possibly enable a previously-disabled floating point unit. type(): | if (CSR[misa].F == 1'b1){ return CsrFieldType::RWH; @@ -427,7 +427,7 @@ fields: location: 10-9 description: | Vector context status. - + When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a vector register or vector CSR is written, VS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware @@ -468,7 +468,7 @@ fields: location: 8 description: | *S-mode Previous Privilege* - + Written by hardware in two cases: * Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt. @@ -498,7 +498,7 @@ fields: location: 7 description: | *M-mode Previous Interrupt Enable* - + Written by hardware in two cases: * Written with prior value of `mstatus.MIE` when entering M-mode from an exception/interrupt. @@ -507,7 +507,7 @@ fields: Can also be written by software without immediate side effect. Other than serving as a record of nested traps as described above, `mstatus.MPIE` does not affect execution. - + type: RW-H reset_value: UNDEFINED_LEGAL UBE: @@ -515,7 +515,7 @@ fields: definedBy: U description: | *U-mode Big Endian* - + Controls the endianness of U-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -523,7 +523,7 @@ fields: Since the CPU does not support big endian in U-mode, this is hardwired to 0. [when,"U_MODE_ENDIANESS == 'big'"] - Since the CPU does not support litte endian in U-mode, this is hardwired to 1. + Since the CPU does not support litte endian in U-mode, this is hardwired to 1. type(): | return (U_MODE_ENDIANESS == "dynamic") ? CsrFieldType::RW : CsrFieldType::RO; @@ -558,7 +558,7 @@ fields: location: 3 description: | *M-mode Interrupt Enable* - + Written by hardware in two cases: * Written with the value 0 when entering M-mode from an exception/interrupt. @@ -568,14 +568,14 @@ fields: * When 0, all interrupts are disabled when the current privilege level is M. * When 1, interrupts that are not otherwise disabled with a field in `mie` are enabled. - + type: RW-H reset_value: 0 SIE: location: 1 description: | *S-mode Interrupt Enable* - + Written by hardware in two cases: * Written with the value 0 when entering (H)S-mode from an exception/interrupt. diff --git a/arch/csr/mstatush.yaml b/arch/csr/mstatush.yaml index 329d2a99e..3fac5fdcb 100644 --- a/arch/csr/mstatush.yaml +++ b/arch/csr/mstatush.yaml @@ -55,4 +55,3 @@ fields: } else { return UNDEFINED_LEGAL; } - diff --git a/arch/csr/mtval.yaml b/arch/csr/mtval.yaml index e2d4da1a0..067f84b6f 100644 --- a/arch/csr/mtval.yaml +++ b/arch/csr/mtval.yaml @@ -46,7 +46,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -63,34 +63,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. <%- end -%> !=== diff --git a/arch/csr/mtvec.yaml b/arch/csr/mtvec.yaml index f38a48b8c..265f39fd3 100644 --- a/arch/csr/mtvec.yaml +++ b/arch/csr/mtvec.yaml @@ -28,7 +28,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2). diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index 21b8b4a54..2e0e58559 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -16,7 +16,7 @@ fields: location_rv64: 63 description: | Written by hardware when a trap is taken into S-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `scause.INT` is writeable. diff --git a/arch/csr/schema.adoc b/arch/csr/schema.adoc index e13ceb224..acdb74bd3 100644 --- a/arch/csr/schema.adoc +++ b/arch/csr/schema.adoc @@ -218,4 +218,3 @@ Custom Write Function:: Alias:: Some fields are aliases for another field, often in a different CSR. THe `alias` key is used to indicate that this field just points somewhere else. - diff --git a/arch/csr/senvcfg.yaml b/arch/csr/senvcfg.yaml index e804e5aae..1c6aea47d 100644 --- a/arch/csr/senvcfg.yaml +++ b/arch/csr/senvcfg.yaml @@ -101,7 +101,7 @@ fields: * `01`: The instruction is executed and performs a flush operation * `10`: _Reserved_ * `11`: The instruction is executed and performs an invalidate operation - + See `cbo.inval` for more details. definedBy: Zicbom type: RW-R @@ -142,4 +142,4 @@ fields: See `fence` for more details. type: RW - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/sstatus.yaml b/arch/csr/sstatus.yaml index ba014122e..c9ae22e33 100644 --- a/arch/csr/sstatus.yaml +++ b/arch/csr/sstatus.yaml @@ -22,7 +22,7 @@ fields: *State Dirty* Alias of `mstatus.SD`. - + type: RO-H reset_value: UNDEFINED_LEGAL affectedBy: [F, D, V] @@ -34,7 +34,7 @@ fields: *U-mode XLEN* Alias of `mstatus.UXL`. - + type: RO reset_value: UNDEFINED_LEGAL MXR: @@ -44,7 +44,7 @@ fields: *Make eXecutable Readable* Alias of `mstatus.MXR`. - + type: RW reset_value: UNDEFINED_LEGAL SUM: @@ -54,7 +54,7 @@ fields: *permit Supervisor Memory Access* Alias of `mstatus.SUM`. - + type: RW reset_value: UNDEFINED_LEGAL XS: @@ -62,9 +62,9 @@ fields: location: 16-15 description: | Custom (X) extension context Status. - + Alias of `mstatus.XS`. - + type: RO reset_value: UNDEFINED_LEGAL FS: @@ -87,7 +87,7 @@ fields: Alias of `mstatus.VS`. type: RW-H - reset_value: UNDEFINED_LEGAL + reset_value: UNDEFINED_LEGAL definedBy: V SPP: alias: mstatus.SPP @@ -116,7 +116,7 @@ fields: *S-mode Previous Interrupt Enable* Alias of `mstatus.SPIE`. - + type: RW-H definedBy: S reset_value: UNDEFINED_LEGAL @@ -127,6 +127,6 @@ fields: *S-mode Interrupt Enable* Alias of `mstatus.SIE`. - + type: RW-H - reset_value: UNDEFINED_LEGAL \ No newline at end of file + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/stval.yaml b/arch/csr/stval.yaml index 0e2a64bf4..e301e3c79 100644 --- a/arch/csr/stval.yaml +++ b/arch/csr/stval.yaml @@ -27,7 +27,7 @@ fields: ! [3] Breakpoint ! [when,"REPORT_VA_IN_STVAL_ON_BREAKPOINT == true"] When caused by an EBREAK instruction, the virtual PC of the breakpoint instruction. - + [when,"REPORT_VA_IN_STVAL_ON_BREAKPOINT == false"] When caused by an EBREAK instruction, zero. @@ -45,7 +45,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -61,34 +61,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `htval`. <%- end -%> !=== diff --git a/arch/csr/stvec.yaml b/arch/csr/stvec.yaml index acc02efed..3432f8a89 100644 --- a/arch/csr/stvec.yaml +++ b/arch/csr/stvec.yaml @@ -30,7 +30,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`stvec.BASE` << 2). diff --git a/arch/csr/time.yaml b/arch/csr/time.yaml index c900402d9..72e4706fa 100644 --- a/arch/csr/time.yaml +++ b/arch/csr/time.yaml @@ -21,10 +21,10 @@ description: | 4+^.>h! `time` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== -- diff --git a/arch/csr/timeh.yaml b/arch/csr/timeh.yaml index 8d9ebf3b1..f3aa95bfb 100644 --- a/arch/csr/timeh.yaml +++ b/arch/csr/timeh.yaml @@ -21,10 +21,10 @@ description: | 4+^.>h! `time` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== -- diff --git a/arch/csr/vscause.yaml b/arch/csr/vscause.yaml index 56c407058..cfaf02d1d 100644 --- a/arch/csr/vscause.yaml +++ b/arch/csr/vscause.yaml @@ -16,7 +16,7 @@ fields: location_rv32: 31 description: | Written by hardware when a trap is taken into VS-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `vscause.INT` is writeable. diff --git a/arch/csr/vsstatus.yaml b/arch/csr/vsstatus.yaml index 9a3a9d72b..5df4d8451 100644 --- a/arch/csr/vsstatus.yaml +++ b/arch/csr/vsstatus.yaml @@ -23,7 +23,7 @@ fields: location_rv32: 31 description: | *State Dirty* - + Read-only bit that summarizes whether any of the `vsstatus.FS`, <% if ext?(:V) %> `vsstatus.VS`, <% end %> or `vsstatus.XS` fields signal the presence of some dirty state @@ -104,7 +104,7 @@ fields: location: 16-15 description: | *Custom (X) extension context Status* - + Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions, this field is read-only 0. @@ -124,7 +124,7 @@ fields: `vsstatus.FS` is written with the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware - other than to possibly enable a previously-disabled floating point unit. + other than to possibly enable a previously-disabled floating point unit. type: RW-H definedBy: F reset_value: UNDEFINED_LEGAL @@ -138,7 +138,7 @@ fields: Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled vector unit. type: RW-H - reset_value: UNDEFINED_LEGAL + reset_value: UNDEFINED_LEGAL definedBy: V SPP: location: 8 diff --git a/arch/csr/vstval.yaml b/arch/csr/vstval.yaml index bc1cbfc87..ced416f70 100644 --- a/arch/csr/vstval.yaml +++ b/arch/csr/vstval.yaml @@ -29,7 +29,7 @@ fields: ! [3] Breakpoint a! [when,"REPORT_VA_IN_VSTVAL_ON_BREAKPOINT == true"] When caused by an EBREAK instruction, the virtual PC of the breakpoint instruction. - + [when,"REPORT_VA_IN_VSTVAL_ON_BREAKPOINT == false"] When caused by an EBREAK instruction, zero. @@ -47,7 +47,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -63,34 +63,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `htval`. <%- end -%> !=== diff --git a/arch/csr/vstvec.yaml b/arch/csr/vstvec.yaml index 1d77e20b4..a74254e64 100644 --- a/arch/csr/vstvec.yaml +++ b/arch/csr/vstvec.yaml @@ -31,7 +31,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts taken into VS-mode. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`vstvec.BASE` << 2). @@ -44,4 +44,4 @@ fields: } else { return UNDEFINED_LEGAL_DETERMINISTIC; } - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/ext/A.yaml b/arch/ext/A.yaml index b857f9d79..f72416a5b 100644 --- a/arch/ext/A.yaml +++ b/arch/ext/A.yaml @@ -80,8 +80,8 @@ params: description: | Strategy used to handle reservation sets. - * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address - * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address + * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address + * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC schema: diff --git a/arch/ext/C.yaml b/arch/ext/C.yaml index 5321d7d90..4559fa8c6 100644 --- a/arch/ext/C.yaml +++ b/arch/ext/C.yaml @@ -68,7 +68,7 @@ description: | Double-precision loads and stores are a significant fraction of static and dynamic instructions, hence the motivation to include them in the RV32C and RV64C encoding. - + Although single-precision loads and stores are not a significant source of static or dynamic compression for benchmarks compiled for the currently supported ABIs, for microcontrollers that only provide @@ -240,7 +240,7 @@ description: | //[%header] [float="center",align="center",cols="1a, 2a",frame="none",grid="none"] |=== - | + | [%autowidth,float="right",align="right",cols="^,^",frame="none",grid="none",options="noheader"] !=== !Format ! Meaning @@ -275,14 +275,14 @@ description: | //[cols="20%,10%,10%,10%,10%,10%,10%,10%,10%"] [float="center",align="center",cols="1a, 1a",frame="none",grid="none"] |=== - | + | [%autowidth,cols="<",frame="none",grid="none",options="noheader"] !=== !RVC Register Number !Integer Register Number - !Integer Register ABI Name + !Integer Register ABI Name !Floating-Point Register Number - !Floating-Point Register ABI Name + !Floating-Point Register ABI Name !=== | @@ -300,4 +300,4 @@ params: description: | Indicates whether or not the `C` extension can be disabled with the `misa.C` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/D.yaml b/arch/ext/D.yaml index a5b20acf8..a99778999 100644 --- a/arch/ext/D.yaml +++ b/arch/ext/D.yaml @@ -106,4 +106,4 @@ params: description: | Indicates whether or not the `D` extension can be disabled with the `misa.D` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/F.yaml b/arch/ext/F.yaml index 3193d1a3c..fd45f3bcc 100644 --- a/arch/ext/F.yaml +++ b/arch/ext/F.yaml @@ -125,7 +125,7 @@ description: | modes are encoded as shown in <>. A value of 111 in the instruction's _rm_ field selects the dynamic rounding mode held in `frm`. The behavior of floating-point instructions that depend on - rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to + rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). @@ -270,4 +270,4 @@ params: assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) # if HW is writing FS, then Dirty (3) better be a supported value - assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never") \ No newline at end of file + assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never") diff --git a/arch/ext/H.yaml b/arch/ext/H.yaml index 0e8bb8bcd..3ff99325b 100644 --- a/arch/ext/H.yaml +++ b/arch/ext/H.yaml @@ -161,7 +161,7 @@ params: NUM_EXTERNAL_GUEST_INTERRUPTS: description: | Number of supported virtualized guest interrupts - + Corresponds to the `GEILEN` parameter in the RVI specs schema: type: integer @@ -454,7 +454,7 @@ params: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding - * "custom": A custom value, which will cause an UNPREDICTABLE event. + * "custom": A custom value, which will cause an UNPREDICTABLE event. schema: type: string enum: @@ -470,7 +470,7 @@ params: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding - * "custom": A custom value, which will cause an UNPREDICTABLE event. + * "custom": A custom value, which will cause an UNPREDICTABLE event. schema: type: string enum: @@ -636,4 +636,4 @@ params: without raising a trap, in which case the EEI must provide a builtin. schema: type: boolean - default: true \ No newline at end of file + default: true diff --git a/arch/ext/I.yaml b/arch/ext/I.yaml index 72eae0eac..31a0e9099 100644 --- a/arch/ext/I.yaml +++ b/arch/ext/I.yaml @@ -12,4 +12,4 @@ versions: changes: - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA description: | - Base integer instructions -- TODO \ No newline at end of file + Base integer instructions -- TODO diff --git a/arch/ext/M.yaml b/arch/ext/M.yaml index e5bf5fa1b..25f3af18b 100644 --- a/arch/ext/M.yaml +++ b/arch/ext/M.yaml @@ -26,4 +26,4 @@ params: description: | Indicates whether or not the `M` extension can be disabled with the `misa.M` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/MockExt.yaml b/arch/ext/MockExt.yaml index 8ba867c8d..57cc560d4 100644 --- a/arch/ext/MockExt.yaml +++ b/arch/ext/MockExt.yaml @@ -89,7 +89,7 @@ params: description: foo schema: type: integer - minimum: 1000 + minimum: 1000 maximum: 2048 MOCK_INT_RANGE_0_TO_128: description: foo @@ -153,4 +153,4 @@ params: additionalItems: type: boolean maxItems: 8 - minItems: 8 \ No newline at end of file + minItems: 8 diff --git a/arch/ext/Sm.yaml b/arch/ext/Sm.yaml index 47b5a40a6..fdd3b5d35 100644 --- a/arch/ext/Sm.yaml +++ b/arch/ext/Sm.yaml @@ -231,8 +231,8 @@ params: maximum: 127 MISALIGNED_LDST: description: | - Does the implementation perform non-atomic misaligned loads and stores to main memory - (does *not* affect misaligned support to device memory)? + Does the implementation perform non-atomic misaligned loads and stores to main memory + (does *not* affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception. schema: type: boolean @@ -282,7 +282,7 @@ params: * by_byte: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address * custom: Something else. Will result in a call to unpredictable() in the execution - schema: + schema: type: string enum: ["by_byte", "custom"] TRAP_ON_ILLEGAL_WLRL: @@ -431,7 +431,7 @@ params: PMA_GRANULARITY: description: | log2 of the smallest supported PMA region. - + Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations @@ -468,7 +468,7 @@ params: true:: The `misa` CSR returns a non-zero value. - + false:: The `misa` CSR is read-only-0. schema: diff --git a/arch/ext/Smcdeleg.yaml b/arch/ext/Smcdeleg.yaml index cf03c5253..5979178c8 100644 --- a/arch/ext/Smcdeleg.yaml +++ b/arch/ext/Smcdeleg.yaml @@ -34,4 +34,4 @@ versions: email: gfavor@ventanamicro.com company: Ventana Microsystems - name: John Hauser - email: jh.riscv@jhauser.us \ No newline at end of file + email: jh.riscv@jhauser.us diff --git a/arch/ext/Smhpm.yaml b/arch/ext/Smhpm.yaml index ebb5b1842..fa2d63df3 100644 --- a/arch/ext/Smhpm.yaml +++ b/arch/ext/Smhpm.yaml @@ -56,7 +56,7 @@ params: description: | Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`. - An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, + An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true. COUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcountinhibit.TM`, @@ -88,4 +88,4 @@ params: items: type: boolean maxItems: 32 - minItems: 32 \ No newline at end of file + minItems: 32 diff --git a/arch/ext/Smpmp.yaml b/arch/ext/Smpmp.yaml index f50f73c6d..05e0ec654 100644 --- a/arch/ext/Smpmp.yaml +++ b/arch/ext/Smpmp.yaml @@ -46,7 +46,7 @@ params: must appear to be 0, 16, or 64. Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES: - + [separator="!"] !=== ! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15> @@ -59,7 +59,7 @@ params: if TRAP_ON_UNIMPLEMENTED_CSR is true ** Y = Implemented; access will not cause an exception (from M-mode), but register may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register - + [NOTE] `pmpcfgN` for an odd N never exists when XLEN == 64 @@ -72,7 +72,7 @@ params: PMP_GRANULARITY: description: | log2 of the smallest supported PMP region. - + Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations @@ -82,4 +82,4 @@ params: schema: type: integer minimum: 2 - maximum: 66 \ No newline at end of file + maximum: 66 diff --git a/arch/ext/Sstvala.yaml b/arch/ext/Sstvala.yaml index 118b7811d..98e5fce73 100644 --- a/arch/ext/Sstvala.yaml +++ b/arch/ext/Sstvala.yaml @@ -9,7 +9,7 @@ description: | and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the `ebreak` or `c.ebreak instructions. - + For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction. @@ -60,4 +60,4 @@ versions: const: true REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: schema: - const: true \ No newline at end of file + const: true diff --git a/arch/ext/Svade.yaml b/arch/ext/Svade.yaml index b776ca6bb..8dcbf4857 100644 --- a/arch/ext/Svade.yaml +++ b/arch/ext/Svade.yaml @@ -39,4 +39,3 @@ conflicts: Svadu doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ - diff --git a/arch/ext/Svadu.yaml b/arch/ext/Svadu.yaml index bd505b5be..93202f732 100644 --- a/arch/ext/Svadu.yaml +++ b/arch/ext/Svadu.yaml @@ -12,7 +12,7 @@ description: | * When a virtual page is accessed and the A bit is clear, the PTE is updated to set the A bit. When the virtual page is written and the D bit is clear, the PTE is updated to set the D bit. When G-stage address translation is in use - and is not Bare, the G-stage virtual pages may be accessed or written by + and is not Bare, the G-stage virtual pages may be accessed or written by implicit accesses to VS-level memory management data structures, such as page tables. @@ -38,7 +38,7 @@ description: | remote harts. + + The PTE update is not required to be atomic with respect to the memory access - that caused the update and a trap may occur between the PTE update and the + that caused the update and a trap may occur between the PTE update and the memory access that caused the PTE update. If a trap occurs then the A and/or D bit may be updated but the memory access that caused the PTE update might not occur. The hart must not perform the memory access that caused the PTE update @@ -122,4 +122,3 @@ conflicts: Svade doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ - diff --git a/arch/ext/Svnapot.yaml b/arch/ext/Svnapot.yaml index af42265d3..240f60cf7 100644 --- a/arch/ext/Svnapot.yaml +++ b/arch/ext/Svnapot.yaml @@ -56,7 +56,7 @@ description: | <>, then a page-fault exception must be raised. * Implicit reads of NAPOT page table entries may create address-translation cache entries mapping - _a_ + _j_*PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] + _a_ + _j_*PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] is replaced by _vpn[i][pte.napot_bits_-1:0], for any or all _j_ such that __j__ >> __napot_bits__ = __vpn__[__i__] >> __napot_bits__, all for the address space identified in _satp_ as loaded by step 1. @@ -152,7 +152,7 @@ description: | 1 + 2 + ... - |=== + |=== In such a case, an implementation may or may not support all options. The discoverability mechanism for this extension would be extended to diff --git a/arch/ext/U.yaml b/arch/ext/U.yaml index c7c4fc253..a3a42d8de 100644 --- a/arch/ext/U.yaml +++ b/arch/ext/U.yaml @@ -47,4 +47,4 @@ params: without raising a trap, in which case the EEI must provide a builtin. schema: type: boolean - default: true \ No newline at end of file + default: true diff --git a/arch/ext/V.yaml b/arch/ext/V.yaml index e40290605..462b12a6d 100644 --- a/arch/ext/V.yaml +++ b/arch/ext/V.yaml @@ -46,4 +46,4 @@ params: assert MSTATUS_VS_LEGAL_VALUES.include?(0) && MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) # if HW is writing VS, then Dirty (3) better be a supported value - assert MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never") \ No newline at end of file + assert MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never") diff --git a/arch/ext/Zalrsc.yaml b/arch/ext/Zalrsc.yaml index d2d0da35f..90043522f 100644 --- a/arch/ext/Zalrsc.yaml +++ b/arch/ext/Zalrsc.yaml @@ -310,4 +310,4 @@ description: | starvation-freedom guarantee. However, the weaker livelock-freedom guarantee is sufficient to implement the C11 and C++11 languages, and is substantially easier to provide in some microarchitectural styles. - ==== \ No newline at end of file + ==== diff --git a/arch/ext/Zbc.yaml b/arch/ext/Zbc.yaml index 671fb9c21..1668b2042 100644 --- a/arch/ext/Zbc.yaml +++ b/arch/ext/Zbc.yaml @@ -49,5 +49,3 @@ versions: - name: Andrew Waterman - name: Thomas Wicki - name: Claire Wolf - - diff --git a/arch/ext/Zbs.yaml b/arch/ext/Zbs.yaml index ac5e67835..b7aee60c7 100644 --- a/arch/ext/Zbs.yaml +++ b/arch/ext/Zbs.yaml @@ -54,5 +54,3 @@ versions: - name: Andrew Waterman - name: Thomas Wicki - name: Claire Wolf - - diff --git a/arch/ext/Zcb.yaml b/arch/ext/Zcb.yaml index 53fb28e66..ccd0012fc 100644 --- a/arch/ext/Zcb.yaml +++ b/arch/ext/Zcb.yaml @@ -5,12 +5,12 @@ kind: extension name: Zcb long_name: Simple code-size saving instructions description: | - Zcb has simple code-size saving instructions which are easy to implement on all CPUs. + Zcb has simple code-size saving instructions which are easy to implement on all CPUs. All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions. - + The Zcb extension depends on the Zca extension. - - As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. + + As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented. type: unprivileged @@ -31,12 +31,12 @@ versions: - name: Matteo Perotti - name: Nidal Faour - name: Bill Traynor - - name: Rafael Sene + - name: Rafael Sene - name: Xinlong Wu - name: sinan - name: Jeremy Bennett - - name: Heda Chen + - name: Heda Chen - name: Alasdair Armstrong - name: Graeme Smecher - - name: Nicolas Brunie + - name: Nicolas Brunie - name: Jiawei diff --git a/arch/ext/Zfhmin.yaml b/arch/ext/Zfhmin.yaml index 2f68bfb7a..024f43efa 100644 --- a/arch/ext/Zfhmin.yaml +++ b/arch/ext/Zfhmin.yaml @@ -50,4 +50,3 @@ versions: requires: name: F version: ">= 2.2" - diff --git a/arch/ext/Zicboz.yaml b/arch/ext/Zicboz.yaml index 84bd7cf42..343b25baf 100644 --- a/arch/ext/Zicboz.yaml +++ b/arch/ext/Zicboz.yaml @@ -16,4 +16,4 @@ params: The observable size of a cache block, in bytes also_defined_in: [Zicbom, Zicbop] schema: - type: integer \ No newline at end of file + type: integer diff --git a/arch/ext/Zicntr.yaml b/arch/ext/Zicntr.yaml index bd791827a..85f2ce5e2 100644 --- a/arch/ext/Zicntr.yaml +++ b/arch/ext/Zicntr.yaml @@ -23,11 +23,11 @@ params: true:: `time`/`timeh` exists, and accessing it will not cause an IllegalInstruction trap - + false:: `time`/`timeh` does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the `time` CSR, or may pass the exception to a lower level. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/Zihpm.yaml b/arch/ext/Zihpm.yaml index 6b6da5dab..f7ec3b9ba 100644 --- a/arch/ext/Zihpm.yaml +++ b/arch/ext/Zihpm.yaml @@ -10,5 +10,5 @@ versions: - version: "2.0.0" state: ratified ratification_date: unknown - requires: - name: Smhpm \ No newline at end of file + requires: + name: Smhpm diff --git a/arch/ext/Zkt.yaml b/arch/ext/Zkt.yaml index df11a4e36..d5946dd45 100644 --- a/arch/ext/Zkt.yaml +++ b/arch/ext/Zkt.yaml @@ -105,14 +105,14 @@ description: | If a secret ends up in address calculation affecting a load or store, that is a violation. If a secret affects a branch's condition, that is also a violation. A secret variable location or register becomes a non-secret via - specific zeroization/sanitisation or by being declared ciphertext + specific zeroization/sanitisation or by being declared ciphertext (or otherwise no-longer-secret information). In essence, secrets can only "touch" instructions on the Zkt list while they are secrets. == Specific Instruction Rationale * HINT instruction forms (typically encodings with `rd=x0`) are excluded from - the data-independent time requirement. + the data-independent time requirement. * Floating point (F, D, Q, L extensions) are currently excluded from the constant-time requirement as they have very few applications in standardised cryptography. We may consider adding floating point add, sub, multiply as a @@ -360,4 +360,3 @@ versions: company: name: RISC-V International url: https://riscv.org - diff --git a/arch/inst/A/amoadd.d.yaml b/arch/inst/A/amoadd.d.yaml index bbe674de1..3d7c6b529 100644 --- a/arch/inst/A/amoadd.d.yaml +++ b/arch/inst/A/amoadd.d.yaml @@ -6,7 +6,7 @@ name: amoadd.d long_name: Atomic fetch-and-add doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Add the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoadd.w.yaml b/arch/inst/A/amoadd.w.yaml index 6a70c42fb..81938edbd 100644 --- a/arch/inst/A/amoadd.w.yaml +++ b/arch/inst/A/amoadd.w.yaml @@ -6,7 +6,7 @@ name: amoadd.w long_name: Atomic fetch-and-add word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Add the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoand.d.yaml b/arch/inst/A/amoand.d.yaml index ae9d8dcfd..3d12556b3 100644 --- a/arch/inst/A/amoand.d.yaml +++ b/arch/inst/A/amoand.d.yaml @@ -6,7 +6,7 @@ name: amoand.d long_name: Atomic fetch-and-and doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * AND the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoand.w.yaml b/arch/inst/A/amoand.w.yaml index 485105d4f..512501131 100644 --- a/arch/inst/A/amoand.w.yaml +++ b/arch/inst/A/amoand.w.yaml @@ -6,7 +6,7 @@ name: amoand.w long_name: Atomic fetch-and-and word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * AND the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomax.d.yaml b/arch/inst/A/amomax.d.yaml index a5c110988..c223bf017 100644 --- a/arch/inst/A/amomax.d.yaml +++ b/arch/inst/A/amomax.d.yaml @@ -6,7 +6,7 @@ name: amomax.d long_name: Atomic MAX doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomax.w.yaml b/arch/inst/A/amomax.w.yaml index b8a5b4db7..2f4602c7d 100644 --- a/arch/inst/A/amomax.w.yaml +++ b/arch/inst/A/amomax.w.yaml @@ -6,7 +6,7 @@ name: amomax.w long_name: Atomic MAX word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomaxu.d.yaml b/arch/inst/A/amomaxu.d.yaml index 7ccf572b0..821ea8ea7 100644 --- a/arch/inst/A/amomaxu.d.yaml +++ b/arch/inst/A/amomaxu.d.yaml @@ -6,7 +6,7 @@ name: amomaxu.d long_name: Atomic MAX unsigned doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomaxu.w.yaml b/arch/inst/A/amomaxu.w.yaml index 555a689c9..268abc22a 100644 --- a/arch/inst/A/amomaxu.w.yaml +++ b/arch/inst/A/amomaxu.w.yaml @@ -6,7 +6,7 @@ name: amomaxu.w long_name: Atomic MAX unsigned word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomin.d.yaml b/arch/inst/A/amomin.d.yaml index 367ae39b1..f111b4102 100644 --- a/arch/inst/A/amomin.d.yaml +++ b/arch/inst/A/amomin.d.yaml @@ -6,7 +6,7 @@ name: amomin.d long_name: Atomic MIN doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomin.w.yaml b/arch/inst/A/amomin.w.yaml index 3890b056c..b461a48f8 100644 --- a/arch/inst/A/amomin.w.yaml +++ b/arch/inst/A/amomin.w.yaml @@ -6,7 +6,7 @@ name: amomin.w long_name: Atomic MIN word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amominu.d.yaml b/arch/inst/A/amominu.d.yaml index 8bfc19055..3252fe812 100644 --- a/arch/inst/A/amominu.d.yaml +++ b/arch/inst/A/amominu.d.yaml @@ -6,7 +6,7 @@ name: amominu.d long_name: Atomic MIN unsigned doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amominu.w.yaml b/arch/inst/A/amominu.w.yaml index 6f41b3c64..c5eba85a8 100644 --- a/arch/inst/A/amominu.w.yaml +++ b/arch/inst/A/amominu.w.yaml @@ -6,7 +6,7 @@ name: amominu.w long_name: Atomic MIN unsigned word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoor.d.yaml b/arch/inst/A/amoor.d.yaml index 63783db75..bb4a019e0 100644 --- a/arch/inst/A/amoor.d.yaml +++ b/arch/inst/A/amoor.d.yaml @@ -6,7 +6,7 @@ name: amoor.d long_name: Atomic fetch-and-or doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * OR the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoor.w.yaml b/arch/inst/A/amoor.w.yaml index ecde879fa..bd31b909f 100644 --- a/arch/inst/A/amoor.w.yaml +++ b/arch/inst/A/amoor.w.yaml @@ -6,7 +6,7 @@ name: amoor.w long_name: Atomic fetch-and-or word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * OR the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoswap.d.yaml b/arch/inst/A/amoswap.d.yaml index 6fe322a4c..e6f065534 100644 --- a/arch/inst/A/amoswap.d.yaml +++ b/arch/inst/A/amoswap.d.yaml @@ -6,7 +6,7 @@ name: amoswap.d long_name: Atomic SWAP doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the value into _rd_ * Store the value of register _rs2_ to the address in _rs1_ @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoswap.w.yaml b/arch/inst/A/amoswap.w.yaml index 224a7d173..152b663b6 100644 --- a/arch/inst/A/amoswap.w.yaml +++ b/arch/inst/A/amoswap.w.yaml @@ -6,7 +6,7 @@ name: amoswap.w long_name: Atomic SWAP word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Store the least-significant word of register _rs2_ to the address in _rs1_ @@ -94,7 +94,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -134,7 +134,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoxor.d.yaml b/arch/inst/A/amoxor.d.yaml index fecb96843..a47e9373c 100644 --- a/arch/inst/A/amoxor.d.yaml +++ b/arch/inst/A/amoxor.d.yaml @@ -6,7 +6,7 @@ name: amoxor.d long_name: Atomic fetch-and-xor doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * XOR the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoxor.w.yaml b/arch/inst/A/amoxor.w.yaml index e299f6350..1c262bd09 100644 --- a/arch/inst/A/amoxor.w.yaml +++ b/arch/inst/A/amoxor.w.yaml @@ -6,7 +6,7 @@ name: amoxor.w long_name: Atomic fetch-and-xor word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * XOR the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/lr.d.yaml b/arch/inst/A/lr.d.yaml index ca7b2288e..4844143e8 100644 --- a/arch/inst/A/lr.d.yaml +++ b/arch/inst/A/lr.d.yaml @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/lr.w.yaml b/arch/inst/A/lr.w.yaml index 0ae9dd0c8..883fedf19 100644 --- a/arch/inst/A/lr.w.yaml +++ b/arch/inst/A/lr.w.yaml @@ -144,7 +144,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 72a0a79f3..3f55a4ec7 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -228,7 +228,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/A/sc.w.yaml b/arch/inst/A/sc.w.yaml index c8dcac714..fc29cbc00 100644 --- a/arch/inst/A/sc.w.yaml +++ b/arch/inst/A/sc.w.yaml @@ -234,7 +234,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/B/add.uw.yaml b/arch/inst/B/add.uw.yaml index c07907206..f8aedbf6d 100644 --- a/arch/inst/B/add.uw.yaml +++ b/arch/inst/B/add.uw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/andn.yaml b/arch/inst/B/andn.yaml index 9de7b36a2..c377ce8a1 100644 --- a/arch/inst/B/andn.yaml +++ b/arch/inst/B/andn.yaml @@ -56,7 +56,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bclr.yaml b/arch/inst/B/bclr.yaml index b6b8117f7..03ebc50ba 100644 --- a/arch/inst/B/bclr.yaml +++ b/arch/inst/B/bclr.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bclri.yaml b/arch/inst/B/bclri.yaml index c718e3cf5..7c270a899 100644 --- a/arch/inst/B/bclri.yaml +++ b/arch/inst/B/bclri.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bext.yaml b/arch/inst/B/bext.yaml index 4d3b4caf7..92ea15b8f 100644 --- a/arch/inst/B/bext.yaml +++ b/arch/inst/B/bext.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bexti.yaml b/arch/inst/B/bexti.yaml index fbb2705c5..44b568785 100644 --- a/arch/inst/B/bexti.yaml +++ b/arch/inst/B/bexti.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/binv.yaml b/arch/inst/B/binv.yaml index 8390947af..40262f63b 100644 --- a/arch/inst/B/binv.yaml +++ b/arch/inst/B/binv.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/binvi.yaml b/arch/inst/B/binvi.yaml index cd9be980b..ac23c5775 100644 --- a/arch/inst/B/binvi.yaml +++ b/arch/inst/B/binvi.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bset.yaml b/arch/inst/B/bset.yaml index 5cf11e49f..c0a5e0427 100644 --- a/arch/inst/B/bset.yaml +++ b/arch/inst/B/bset.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bseti.yaml b/arch/inst/B/bseti.yaml index 84466cdde..9b9e69307 100644 --- a/arch/inst/B/bseti.yaml +++ b/arch/inst/B/bseti.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmul.yaml b/arch/inst/B/clmul.yaml index 42c104025..73529d043 100644 --- a/arch/inst/B/clmul.yaml +++ b/arch/inst/B/clmul.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmulh.yaml b/arch/inst/B/clmulh.yaml index d93284718..44b695eaf 100644 --- a/arch/inst/B/clmulh.yaml +++ b/arch/inst/B/clmulh.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmulr.yaml b/arch/inst/B/clmulr.yaml index 249382ceb..7a4033f8a 100644 --- a/arch/inst/B/clmulr.yaml +++ b/arch/inst/B/clmulr.yaml @@ -52,7 +52,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clz.yaml b/arch/inst/B/clz.yaml index f17057957..4349b7bda 100644 --- a/arch/inst/B/clz.yaml +++ b/arch/inst/B/clz.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clzw.yaml b/arch/inst/B/clzw.yaml index 7c5b6224a..d0ede84fc 100644 --- a/arch/inst/B/clzw.yaml +++ b/arch/inst/B/clzw.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/cpop.yaml b/arch/inst/B/cpop.yaml index a09524600..cb9d5a6fe 100644 --- a/arch/inst/B/cpop.yaml +++ b/arch/inst/B/cpop.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/cpopw.yaml b/arch/inst/B/cpopw.yaml index 59e65f41d..f061ae07b 100644 --- a/arch/inst/B/cpopw.yaml +++ b/arch/inst/B/cpopw.yaml @@ -61,7 +61,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ctz.yaml b/arch/inst/B/ctz.yaml index 848c32352..d39a0f351 100644 --- a/arch/inst/B/ctz.yaml +++ b/arch/inst/B/ctz.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ctzw.yaml b/arch/inst/B/ctzw.yaml index 1ef098151..97ac4ee96 100644 --- a/arch/inst/B/ctzw.yaml +++ b/arch/inst/B/ctzw.yaml @@ -47,7 +47,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/max.yaml b/arch/inst/B/max.yaml index a612ff282..aab174111 100644 --- a/arch/inst/B/max.yaml +++ b/arch/inst/B/max.yaml @@ -62,7 +62,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/maxu.yaml b/arch/inst/B/maxu.yaml index bc8e60282..d2cb26ff2 100644 --- a/arch/inst/B/maxu.yaml +++ b/arch/inst/B/maxu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/min.yaml b/arch/inst/B/min.yaml index 073572963..b7e838fd9 100644 --- a/arch/inst/B/min.yaml +++ b/arch/inst/B/min.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/minu.yaml b/arch/inst/B/minu.yaml index 1d4966312..3a0038c2c 100644 --- a/arch/inst/B/minu.yaml +++ b/arch/inst/B/minu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/orc.b.yaml b/arch/inst/B/orc.b.yaml index ccb867b57..6fdedd626 100644 --- a/arch/inst/B/orc.b.yaml +++ b/arch/inst/B/orc.b.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/orn.yaml b/arch/inst/B/orn.yaml index ba06cea15..50f45f0c4 100644 --- a/arch/inst/B/orn.yaml +++ b/arch/inst/B/orn.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rev8.yaml b/arch/inst/B/rev8.yaml index d2e50680a..950629425 100644 --- a/arch/inst/B/rev8.yaml +++ b/arch/inst/B/rev8.yaml @@ -66,7 +66,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rol.yaml b/arch/inst/B/rol.yaml index f65cf35fa..251f039bf 100644 --- a/arch/inst/B/rol.yaml +++ b/arch/inst/B/rol.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rolw.yaml b/arch/inst/B/rolw.yaml index 105f568ba..daadd41df 100644 --- a/arch/inst/B/rolw.yaml +++ b/arch/inst/B/rolw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ror.yaml b/arch/inst/B/ror.yaml index a7be3ba46..1d75f3112 100644 --- a/arch/inst/B/ror.yaml +++ b/arch/inst/B/ror.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index 1feba8327..e66453373 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/roriw.yaml b/arch/inst/B/roriw.yaml index 7967bc196..df7da5ab3 100644 --- a/arch/inst/B/roriw.yaml +++ b/arch/inst/B/roriw.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rorw.yaml b/arch/inst/B/rorw.yaml index 9f25c3dc6..62f4036d1 100644 --- a/arch/inst/B/rorw.yaml +++ b/arch/inst/B/rorw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sext.b.yaml b/arch/inst/B/sext.b.yaml index 6a7a2018e..a4d2a4bd4 100644 --- a/arch/inst/B/sext.b.yaml +++ b/arch/inst/B/sext.b.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sext.h.yaml b/arch/inst/B/sext.h.yaml index 2ceef5be8..fe2054f4f 100644 --- a/arch/inst/B/sext.h.yaml +++ b/arch/inst/B/sext.h.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh1add.uw.yaml b/arch/inst/B/sh1add.uw.yaml index f85bdb29f..1d5ee5299 100644 --- a/arch/inst/B/sh1add.uw.yaml +++ b/arch/inst/B/sh1add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh1add.yaml b/arch/inst/B/sh1add.yaml index 472dd48b5..88c89a1e7 100644 --- a/arch/inst/B/sh1add.yaml +++ b/arch/inst/B/sh1add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh2add.uw.yaml b/arch/inst/B/sh2add.uw.yaml index a6b6c975d..2256b8ff9 100644 --- a/arch/inst/B/sh2add.uw.yaml +++ b/arch/inst/B/sh2add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh2add.yaml b/arch/inst/B/sh2add.yaml index 952799354..e0c7e3cc5 100644 --- a/arch/inst/B/sh2add.yaml +++ b/arch/inst/B/sh2add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh3add.uw.yaml b/arch/inst/B/sh3add.uw.yaml index 7a64f8049..9cc2a29a0 100644 --- a/arch/inst/B/sh3add.uw.yaml +++ b/arch/inst/B/sh3add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh3add.yaml b/arch/inst/B/sh3add.yaml index 6f84c5308..ace5749ef 100644 --- a/arch/inst/B/sh3add.yaml +++ b/arch/inst/B/sh3add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/slli.uw.yaml b/arch/inst/B/slli.uw.yaml index 98e77bad0..47c9d7d5d 100644 --- a/arch/inst/B/slli.uw.yaml +++ b/arch/inst/B/slli.uw.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/xnor.yaml b/arch/inst/B/xnor.yaml index 9c5444c3c..fc64d5e2e 100644 --- a/arch/inst/B/xnor.yaml +++ b/arch/inst/B/xnor.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/zext.h.yaml b/arch/inst/B/zext.h.yaml index 52c255a37..4e1b492f9 100644 --- a/arch/inst/B/zext.h.yaml +++ b/arch/inst/B/zext.h.yaml @@ -30,8 +30,8 @@ encoding: location: 19-15 - name: rd location: 11-7 -excludedBy: - anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented +excludedBy: + anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented assembly: xd, xs1 access: s: always @@ -58,7 +58,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.add.yaml b/arch/inst/C/c.add.yaml index 0c67ee672..678dfbb14 100644 --- a/arch/inst/C/c.add.yaml +++ b/arch/inst/C/c.add.yaml @@ -6,7 +6,7 @@ name: c.add long_name: Add description: | Add the value in rs2 to rd, and store the result in rd. - C.ADD expands into `add rd, rd, rs2`. + C.ADD expands into `add rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.addi.yaml b/arch/inst/C/c.addi.yaml index aaab1d707..445543b1b 100644 --- a/arch/inst/C/c.addi.yaml +++ b/arch/inst/C/c.addi.yaml @@ -6,8 +6,8 @@ name: c.addi long_name: Add a sign-extended non-zero immediate description: | C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. - C.ADDI expands into `addi rd, rd, imm`. - C.ADDI is only valid when rd ≠ x0 and imm ≠ 0. + C.ADDI expands into `addi rd, rd, imm`. + C.ADDI is only valid when rd ≠ x0 and imm ≠ 0. The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = X[rd] + imm; - diff --git a/arch/inst/C/c.addi16sp.yaml b/arch/inst/C/c.addi16sp.yaml index d83c81825..5b3e53196 100644 --- a/arch/inst/C/c.addi16sp.yaml +++ b/arch/inst/C/c.addi16sp.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addi16sp long_name: Add a sign-extended non-zero immediate description: | - C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). - C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. - It expands into `addi x2, x2, nzimm[9:4]`. + C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). + C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. + It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved. definedBy: anyOf: @@ -32,4 +32,3 @@ operation(): | } X[2] = X[2] + imm; - diff --git a/arch/inst/C/c.addi4spn.yaml b/arch/inst/C/c.addi4spn.yaml index e1a102e3c..d51063be9 100644 --- a/arch/inst/C/c.addi4spn.yaml +++ b/arch/inst/C/c.addi4spn.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addi4spn long_name: Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer description: | - Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. + Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. - It expands to `addi rd', x2, nzuimm[9:2]`. + It expands to `addi rd', x2, nzuimm[9:2]`. C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd+8] = X[2] + imm; - diff --git a/arch/inst/C/c.addiw.yaml b/arch/inst/C/c.addiw.yaml index 41da2cf8c..a5c8220c9 100644 --- a/arch/inst/C/c.addiw.yaml +++ b/arch/inst/C/c.addiw.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addiw long_name: Add a sign-extended non-zero immediate description: | - C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. - C.ADDIW expands into `addiw rd, rd, imm`. - The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. + C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. + C.ADDIW expands into `addiw rd, rd, imm`. + The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is only valid when rd ≠ x0; the code points with rd=x0 are reserved. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = sext((X[rd] + imm), 32); - diff --git a/arch/inst/C/c.addw.yaml b/arch/inst/C/c.addw.yaml index ec8fe7e01..61ba1a41f 100644 --- a/arch/inst/C/c.addw.yaml +++ b/arch/inst/C/c.addw.yaml @@ -7,7 +7,7 @@ long_name: Add word description: | Add the 32-bit values in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.ADDW expands into `addw rd, rd, rs2`. + C.ADDW expands into `addw rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.and.yaml b/arch/inst/C/c.and.yaml index 16914a371..6f365559b 100644 --- a/arch/inst/C/c.and.yaml +++ b/arch/inst/C/c.and.yaml @@ -7,7 +7,7 @@ long_name: And description: | And rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.AND expands into `and rd, rd, rs2`. + C.AND expands into `and rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.andi.yaml b/arch/inst/C/c.andi.yaml index 53eb4d142..c32f5f8e7 100644 --- a/arch/inst/C/c.andi.yaml +++ b/arch/inst/C/c.andi.yaml @@ -7,7 +7,7 @@ long_name: And immediate description: | And an immediate to the value in rd, and store the result in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.ANDI expands into `andi rd, rd, imm`. + C.ANDI expands into `andi rd, rd, imm`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.beqz.yaml b/arch/inst/C/c.beqz.yaml index b8492708e..75d88ee54 100644 --- a/arch/inst/C/c.beqz.yaml +++ b/arch/inst/C/c.beqz.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.beqz long_name: Branch if Equal Zero description: | - C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is zero. + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is zero. It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: diff --git a/arch/inst/C/c.bnez.yaml b/arch/inst/C/c.bnez.yaml index df9912750..91ee35e96 100644 --- a/arch/inst/C/c.bnez.yaml +++ b/arch/inst/C/c.bnez.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.bnez long_name: Branch if NOT Equal Zero description: | - C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero. + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero. It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: diff --git a/arch/inst/C/c.fld.yaml b/arch/inst/C/c.fld.yaml index 524c727e1..4e2c54bca 100644 --- a/arch/inst/C/c.fld.yaml +++ b/arch/inst/C/c.fld.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fld -long_name: Load double-precision +long_name: Load double-precision description: | Loads a double precision floating-point value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.flw.yaml b/arch/inst/C/c.flw.yaml index 44d121ea6..e99c975c3 100644 --- a/arch/inst/C/c.flw.yaml +++ b/arch/inst/C/c.flw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.flw -long_name: Load single-precision +long_name: Load single-precision description: | Loads a single precision floating-point value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.fsd.yaml b/arch/inst/C/c.fsd.yaml index 4531761b9..b16493053 100644 --- a/arch/inst/C/c.fsd.yaml +++ b/arch/inst/C/c.fsd.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fsd -long_name: Store double-precision +long_name: Store double-precision description: | Stores a double precision floating-point value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.fsw.yaml b/arch/inst/C/c.fsw.yaml index e7f258634..b50f1f257 100644 --- a/arch/inst/C/c.fsw.yaml +++ b/arch/inst/C/c.fsw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fsw -long_name: Store single-precision +long_name: Store single-precision description: | Stores a single precision floating-point value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.jr.yaml b/arch/inst/C/c.jr.yaml index 6342aa3f9..97ede0638 100644 --- a/arch/inst/C/c.jr.yaml +++ b/arch/inst/C/c.jr.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.jr long_name: Jump Register description: | - C.JR (jump register) performs an unconditional control transfer to the address in register rs1. + C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to jalr x0, 0(rs1). definedBy: anyOf: diff --git a/arch/inst/C/c.li.yaml b/arch/inst/C/c.li.yaml index a18ea1bab..e162bc7fb 100644 --- a/arch/inst/C/c.li.yaml +++ b/arch/inst/C/c.li.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.li long_name: Load the sign-extended 6-bit immediate description: | - C.LI loads the sign-extended 6-bit immediate, imm, into register rd. - C.LI expands into `addi rd, x0, imm`. + C.LI loads the sign-extended 6-bit immediate, imm, into register rd. + C.LI expands into `addi rd, x0, imm`. C.LI is only valid when rd ≠ x0; the code points with rd=x0 encode HINTs. definedBy: anyOf: @@ -32,4 +32,3 @@ operation(): | } X[rd] = imm; - diff --git a/arch/inst/C/c.lui.yaml b/arch/inst/C/c.lui.yaml index 515c277dd..85c946574 100644 --- a/arch/inst/C/c.lui.yaml +++ b/arch/inst/C/c.lui.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.lui long_name: Load the non-zero 6-bit immediate field into bits 17-12 of the destination register description: | - C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. - C.LUI expands into `lui rd, imm`. - C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero. + C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. + C.LUI expands into `lui rd, imm`. + C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero. The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = imm; - diff --git a/arch/inst/C/c.lw.yaml b/arch/inst/C/c.lw.yaml index 0fa1b48f4..91c2d3a60 100644 --- a/arch/inst/C/c.lw.yaml +++ b/arch/inst/C/c.lw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lw -long_name: Load word +long_name: Load word description: | Loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.nop.yaml b/arch/inst/C/c.nop.yaml index 9fb3e794b..804e23ed0 100644 --- a/arch/inst/C/c.nop.yaml +++ b/arch/inst/C/c.nop.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.nop long_name: Non-operation description: | - C.NOP expands into `addi x0, x0, imm`. + C.NOP expands into `addi x0, x0, imm`. definedBy: anyOf: - C @@ -26,4 +26,3 @@ operation(): | if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { raise(ExceptionCode::IllegalInstruction, mode(), $encoding); } - diff --git a/arch/inst/C/c.or.yaml b/arch/inst/C/c.or.yaml index f6899d9aa..29c2e379a 100644 --- a/arch/inst/C/c.or.yaml +++ b/arch/inst/C/c.or.yaml @@ -7,7 +7,7 @@ long_name: Or description: | Or rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.OR expands into `or rd, rd, rs2`. + C.OR expands into `or rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.sd.yaml b/arch/inst/C/c.sd.yaml index b9cf43c0a..ccb9b2d84 100644 --- a/arch/inst/C/c.sd.yaml +++ b/arch/inst/C/c.sd.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sd -long_name: Store double +long_name: Store double description: | Stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.slli.yaml b/arch/inst/C/c.slli.yaml index 6769be23b..34457091f 100644 --- a/arch/inst/C/c.slli.yaml +++ b/arch/inst/C/c.slli.yaml @@ -6,7 +6,7 @@ name: c.slli long_name: Shift left logical immediate description: | Shift the value in rd left by shamt, and store the result back in rd. - C.SLLI expands into `slli rd, rd, shamt`. + C.SLLI expands into `slli rd, rd, shamt`. definedBy: anyOf: - C @@ -47,7 +47,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.srai.yaml b/arch/inst/C/c.srai.yaml index e0b42444a..1f3a70b16 100644 --- a/arch/inst/C/c.srai.yaml +++ b/arch/inst/C/c.srai.yaml @@ -7,7 +7,7 @@ long_name: Shift right arithmetical immediate description: | Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.SRAI expands into `srai rd, rd, shamt`. + C.SRAI expands into `srai rd, rd, shamt`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.srli.yaml b/arch/inst/C/c.srli.yaml index 63a1a35d7..51b246f48 100644 --- a/arch/inst/C/c.srli.yaml +++ b/arch/inst/C/c.srli.yaml @@ -7,7 +7,7 @@ long_name: Shift right logical immediate description: | Shift the value in rd right by shamt, and store the result back in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.SRLI expands into `srli rd, rd, shamt`. + C.SRLI expands into `srli rd, rd, shamt`. definedBy: anyOf: - C @@ -47,7 +47,3 @@ sail(): | X(rd+8) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.sub.yaml b/arch/inst/C/c.sub.yaml index 36f233523..60af66e88 100644 --- a/arch/inst/C/c.sub.yaml +++ b/arch/inst/C/c.sub.yaml @@ -7,7 +7,7 @@ long_name: Subtract description: | Subtract the value in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.SUB expands into `sub rd, rd, rs2`. + C.SUB expands into `sub rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.subw.yaml b/arch/inst/C/c.subw.yaml index 40c047a13..2e45ead86 100644 --- a/arch/inst/C/c.subw.yaml +++ b/arch/inst/C/c.subw.yaml @@ -7,7 +7,7 @@ long_name: Subtract word description: | Subtract the 32-bit values in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.SUBW expands into `subw rd, rd, rs2`. + C.SUBW expands into `subw rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.sw.yaml b/arch/inst/C/c.sw.yaml index c4a7d0858..2717ce020 100644 --- a/arch/inst/C/c.sw.yaml +++ b/arch/inst/C/c.sw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sw -long_name: Store word +long_name: Store word description: | Stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.xor.yaml b/arch/inst/C/c.xor.yaml index f15a3bae9..ca04d2a18 100644 --- a/arch/inst/C/c.xor.yaml +++ b/arch/inst/C/c.xor.yaml @@ -7,7 +7,7 @@ long_name: Exclusive Or description: | Exclusive or rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.XOR expands into `xor rd, rd, rs2`. + C.XOR expands into `xor rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/D/fadd.d.yaml b/arch/inst/D/fadd.d.yaml index 263afe656..78b384072 100644 --- a/arch/inst/D/fadd.d.yaml +++ b/arch/inst/D/fadd.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fclass.d.yaml b/arch/inst/D/fclass.d.yaml index 5deb39d6e..06bd14a88 100644 --- a/arch/inst/D/fclass.d.yaml +++ b/arch/inst/D/fclass.d.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.l.yaml b/arch/inst/D/fcvt.d.l.yaml index 2e5f4dc44..1754fe9c3 100644 --- a/arch/inst/D/fcvt.d.l.yaml +++ b/arch/inst/D/fcvt.d.l.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.d.lu.yaml b/arch/inst/D/fcvt.d.lu.yaml index 9668ee921..71cc3e6ec 100644 --- a/arch/inst/D/fcvt.d.lu.yaml +++ b/arch/inst/D/fcvt.d.lu.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.d.s.yaml b/arch/inst/D/fcvt.d.s.yaml index ca93fa3b1..19fd2e7d7 100644 --- a/arch/inst/D/fcvt.d.s.yaml +++ b/arch/inst/D/fcvt.d.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.w.yaml b/arch/inst/D/fcvt.d.w.yaml index 779e77749..cefecd930 100644 --- a/arch/inst/D/fcvt.d.w.yaml +++ b/arch/inst/D/fcvt.d.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.wu.yaml b/arch/inst/D/fcvt.d.wu.yaml index 897637dd7..9a05ce038 100644 --- a/arch/inst/D/fcvt.d.wu.yaml +++ b/arch/inst/D/fcvt.d.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.l.d.yaml b/arch/inst/D/fcvt.l.d.yaml index 3cfa12bea..20352af5d 100644 --- a/arch/inst/D/fcvt.l.d.yaml +++ b/arch/inst/D/fcvt.l.d.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.lu.d.yaml b/arch/inst/D/fcvt.lu.d.yaml index aecb2ca0e..f2e1f103e 100644 --- a/arch/inst/D/fcvt.lu.d.yaml +++ b/arch/inst/D/fcvt.lu.d.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.s.d.yaml b/arch/inst/D/fcvt.s.d.yaml index 88d599d53..6f69d7638 100644 --- a/arch/inst/D/fcvt.s.d.yaml +++ b/arch/inst/D/fcvt.s.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.w.d.yaml b/arch/inst/D/fcvt.w.d.yaml index e2714af75..243fc5694 100644 --- a/arch/inst/D/fcvt.w.d.yaml +++ b/arch/inst/D/fcvt.w.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.wu.d.yaml b/arch/inst/D/fcvt.wu.d.yaml index 59a3ed84d..abd390d4d 100644 --- a/arch/inst/D/fcvt.wu.d.yaml +++ b/arch/inst/D/fcvt.wu.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvtmod.w.d.yaml b/arch/inst/D/fcvtmod.w.d.yaml index 4d186be08..d890f78fa 100644 --- a/arch/inst/D/fcvtmod.w.d.yaml +++ b/arch/inst/D/fcvtmod.w.d.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fdiv.d.yaml b/arch/inst/D/fdiv.d.yaml index 5194db5de..a3c17b19a 100644 --- a/arch/inst/D/fdiv.d.yaml +++ b/arch/inst/D/fdiv.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/feq.d.yaml b/arch/inst/D/feq.d.yaml index 3f0dffd80..e3249eca6 100644 --- a/arch/inst/D/feq.d.yaml +++ b/arch/inst/D/feq.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fld.yaml b/arch/inst/D/fld.yaml index a1097d179..cc6a60256 100644 --- a/arch/inst/D/fld.yaml +++ b/arch/inst/D/fld.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fle.d.yaml b/arch/inst/D/fle.d.yaml index 42b06629a..149a7ee35 100644 --- a/arch/inst/D/fle.d.yaml +++ b/arch/inst/D/fle.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fleq.d.yaml b/arch/inst/D/fleq.d.yaml index 77948081b..2046c32a7 100644 --- a/arch/inst/D/fleq.d.yaml +++ b/arch/inst/D/fleq.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fli.d.yaml b/arch/inst/D/fli.d.yaml index e78305d40..113895fc0 100644 --- a/arch/inst/D/fli.d.yaml +++ b/arch/inst/D/fli.d.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/flt.d.yaml b/arch/inst/D/flt.d.yaml index 20ae39d59..8ab8d1996 100644 --- a/arch/inst/D/flt.d.yaml +++ b/arch/inst/D/flt.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fltq.d.yaml b/arch/inst/D/fltq.d.yaml index f2dc4d0c4..63b1e93ed 100644 --- a/arch/inst/D/fltq.d.yaml +++ b/arch/inst/D/fltq.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmadd.d.yaml b/arch/inst/D/fmadd.d.yaml index 8057fb9fb..c269141a7 100644 --- a/arch/inst/D/fmadd.d.yaml +++ b/arch/inst/D/fmadd.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmax.d.yaml b/arch/inst/D/fmax.d.yaml index ea557fb82..4e35cc44c 100644 --- a/arch/inst/D/fmax.d.yaml +++ b/arch/inst/D/fmax.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmaxm.d.yaml b/arch/inst/D/fmaxm.d.yaml index 2ab31feab..37765a2a5 100644 --- a/arch/inst/D/fmaxm.d.yaml +++ b/arch/inst/D/fmaxm.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmin.d.yaml b/arch/inst/D/fmin.d.yaml index e7928b72e..b91899406 100644 --- a/arch/inst/D/fmin.d.yaml +++ b/arch/inst/D/fmin.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fminm.d.yaml b/arch/inst/D/fminm.d.yaml index d8c6ee360..06ef3eae8 100644 --- a/arch/inst/D/fminm.d.yaml +++ b/arch/inst/D/fminm.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmsub.d.yaml b/arch/inst/D/fmsub.d.yaml index 6eee5f8e2..3d582fdf9 100644 --- a/arch/inst/D/fmsub.d.yaml +++ b/arch/inst/D/fmsub.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmul.d.yaml b/arch/inst/D/fmul.d.yaml index cc1847a14..5a7d07db6 100644 --- a/arch/inst/D/fmul.d.yaml +++ b/arch/inst/D/fmul.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmv.d.x.yaml b/arch/inst/D/fmv.d.x.yaml index a6859fbf9..62007aaf2 100644 --- a/arch/inst/D/fmv.d.x.yaml +++ b/arch/inst/D/fmv.d.x.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fmv.x.d.yaml b/arch/inst/D/fmv.x.d.yaml index dbad3a006..729fe7dc9 100644 --- a/arch/inst/D/fmv.x.d.yaml +++ b/arch/inst/D/fmv.x.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fmvh.x.d.yaml b/arch/inst/D/fmvh.x.d.yaml index c9492bc7f..86f7d4976 100644 --- a/arch/inst/D/fmvh.x.d.yaml +++ b/arch/inst/D/fmvh.x.d.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/D/fmvp.d.x.yaml b/arch/inst/D/fmvp.d.x.yaml index a7aee0eb9..c44068bb4 100644 --- a/arch/inst/D/fmvp.d.x.yaml +++ b/arch/inst/D/fmvp.d.x.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/D/fnmadd.d.yaml b/arch/inst/D/fnmadd.d.yaml index 4decb5936..6e73fcf6f 100644 --- a/arch/inst/D/fnmadd.d.yaml +++ b/arch/inst/D/fnmadd.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fnmsub.d.yaml b/arch/inst/D/fnmsub.d.yaml index a5a067037..f9f49cee5 100644 --- a/arch/inst/D/fnmsub.d.yaml +++ b/arch/inst/D/fnmsub.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fround.d.yaml b/arch/inst/D/fround.d.yaml index 8d5b70109..b67de8da0 100644 --- a/arch/inst/D/fround.d.yaml +++ b/arch/inst/D/fround.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/froundnx.d.yaml b/arch/inst/D/froundnx.d.yaml index b1c151da9..411f4c8a6 100644 --- a/arch/inst/D/froundnx.d.yaml +++ b/arch/inst/D/froundnx.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsd.yaml b/arch/inst/D/fsd.yaml index fe879dd5e..989b89200 100644 --- a/arch/inst/D/fsd.yaml +++ b/arch/inst/D/fsd.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnj.d.yaml b/arch/inst/D/fsgnj.d.yaml index e87590932..fdab3944f 100644 --- a/arch/inst/D/fsgnj.d.yaml +++ b/arch/inst/D/fsgnj.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnjn.d.yaml b/arch/inst/D/fsgnjn.d.yaml index 21f54f530..6e7a206f8 100644 --- a/arch/inst/D/fsgnjn.d.yaml +++ b/arch/inst/D/fsgnjn.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnjx.d.yaml b/arch/inst/D/fsgnjx.d.yaml index 737aef9a5..b4e55c47c 100644 --- a/arch/inst/D/fsgnjx.d.yaml +++ b/arch/inst/D/fsgnjx.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsqrt.d.yaml b/arch/inst/D/fsqrt.d.yaml index 5a0772445..657abdfa7 100644 --- a/arch/inst/D/fsqrt.d.yaml +++ b/arch/inst/D/fsqrt.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsub.d.yaml b/arch/inst/D/fsub.d.yaml index f7723cf23..1bddc6665 100644 --- a/arch/inst/D/fsub.d.yaml +++ b/arch/inst/D/fsub.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/F/fadd.s.yaml b/arch/inst/F/fadd.s.yaml index d5291ea1e..fdefa3a07 100644 --- a/arch/inst/F/fadd.s.yaml +++ b/arch/inst/F/fadd.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fclass.s.yaml b/arch/inst/F/fclass.s.yaml index 29d9505ab..29f391926 100644 --- a/arch/inst/F/fclass.s.yaml +++ b/arch/inst/F/fclass.s.yaml @@ -72,7 +72,7 @@ operation(): | } else { assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value"); X[rd] = 1 << 9; - } + } @@ -83,7 +83,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fcvt.l.s.yaml b/arch/inst/F/fcvt.l.s.yaml index a218c623f..c5d156aa4 100644 --- a/arch/inst/F/fcvt.l.s.yaml +++ b/arch/inst/F/fcvt.l.s.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.lu.s.yaml b/arch/inst/F/fcvt.lu.s.yaml index 262b9ee1f..a77ccfe53 100644 --- a/arch/inst/F/fcvt.lu.s.yaml +++ b/arch/inst/F/fcvt.lu.s.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.l.yaml b/arch/inst/F/fcvt.s.l.yaml index 3f1e6f7d8..436bf1906 100644 --- a/arch/inst/F/fcvt.s.l.yaml +++ b/arch/inst/F/fcvt.s.l.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.lu.yaml b/arch/inst/F/fcvt.s.lu.yaml index ff28f6085..b999a2296 100644 --- a/arch/inst/F/fcvt.s.lu.yaml +++ b/arch/inst/F/fcvt.s.lu.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.w.yaml b/arch/inst/F/fcvt.s.w.yaml index b4194fd99..70074ff6d 100644 --- a/arch/inst/F/fcvt.s.w.yaml +++ b/arch/inst/F/fcvt.s.w.yaml @@ -62,14 +62,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.wu.yaml b/arch/inst/F/fcvt.s.wu.yaml index c8aa4a27b..783e1a461 100644 --- a/arch/inst/F/fcvt.s.wu.yaml +++ b/arch/inst/F/fcvt.s.wu.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.w.s.yaml b/arch/inst/F/fcvt.w.s.yaml index 9763b41d4..5693a6046 100644 --- a/arch/inst/F/fcvt.w.s.yaml +++ b/arch/inst/F/fcvt.w.s.yaml @@ -92,14 +92,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.wu.s.yaml b/arch/inst/F/fcvt.wu.s.yaml index c8280f82b..62468f564 100644 --- a/arch/inst/F/fcvt.wu.s.yaml +++ b/arch/inst/F/fcvt.wu.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fdiv.s.yaml b/arch/inst/F/fdiv.s.yaml index 218271c14..a022a8965 100644 --- a/arch/inst/F/fdiv.s.yaml +++ b/arch/inst/F/fdiv.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/feq.s.yaml b/arch/inst/F/feq.s.yaml index b704996ce..5cb61a47b 100644 --- a/arch/inst/F/feq.s.yaml +++ b/arch/inst/F/feq.s.yaml @@ -52,15 +52,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fle.s.yaml b/arch/inst/F/fle.s.yaml index 79dc623c5..23cee21f4 100644 --- a/arch/inst/F/fle.s.yaml +++ b/arch/inst/F/fle.s.yaml @@ -53,15 +53,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fleq.s.yaml b/arch/inst/F/fleq.s.yaml index 0f5b5796a..b2645b9d8 100644 --- a/arch/inst/F/fleq.s.yaml +++ b/arch/inst/F/fleq.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le_quiet (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fli.s.yaml b/arch/inst/F/fli.s.yaml index 008c13fa8..293103c89 100644 --- a/arch/inst/F/fli.s.yaml +++ b/arch/inst/F/fli.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -65,7 +65,3 @@ sail(): | F_S(rd) = bits; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/flt.s.yaml b/arch/inst/F/flt.s.yaml index e18c36b47..e6d63d55b 100644 --- a/arch/inst/F/flt.s.yaml +++ b/arch/inst/F/flt.s.yaml @@ -40,7 +40,7 @@ operation(): | Boolean sign_a = sp_value_a[31] == 1; Boolean sign_b = sp_value_b[31] == 1; - Boolean a_lt_b = + Boolean a_lt_b = (sign_a != sign_b) ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0)) # opposite sign, a is negative. a is less than b as long as both are not zero : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b))); @@ -55,15 +55,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fltq.s.yaml b/arch/inst/F/fltq.s.yaml index fcda54723..219da4452 100644 --- a/arch/inst/F/fltq.s.yaml +++ b/arch/inst/F/fltq.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Lt_quiet (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/flw.yaml b/arch/inst/F/flw.yaml index 700f79d00..1ca5c6928 100644 --- a/arch/inst/F/flw.yaml +++ b/arch/inst/F/flw.yaml @@ -70,7 +70,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmadd.s.yaml b/arch/inst/F/fmadd.s.yaml index 54ac1e3d4..353d68e44 100644 --- a/arch/inst/F/fmadd.s.yaml +++ b/arch/inst/F/fmadd.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmax.s.yaml b/arch/inst/F/fmax.s.yaml index 9a7ade26b..c617d7543 100644 --- a/arch/inst/F/fmax.s.yaml +++ b/arch/inst/F/fmax.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmaxm.s.yaml b/arch/inst/F/fmaxm.s.yaml index b303bdfdd..39d20ca1e 100644 --- a/arch/inst/F/fmaxm.s.yaml +++ b/arch/inst/F/fmaxm.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,21 +32,17 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let is_quiet = true; let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet); - + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S else if rs2_lt_rs1 then rs1_val_S else /* (not rs2_lt_rs1) */ rs2_val_S; - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmin.s.yaml b/arch/inst/F/fmin.s.yaml index 667ddee84..06dd4c629 100644 --- a/arch/inst/F/fmin.s.yaml +++ b/arch/inst/F/fmin.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fminm.s.yaml b/arch/inst/F/fminm.s.yaml index 83b6cf7bf..da71a465c 100644 --- a/arch/inst/F/fminm.s.yaml +++ b/arch/inst/F/fminm.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,21 +32,17 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let is_quiet = true; let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet); - + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S else if rs1_lt_rs2 then rs1_val_S else /* (not rs1_lt_rs2) */ rs2_val_S; - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmsub.s.yaml b/arch/inst/F/fmsub.s.yaml index b12a96acd..13d2a7f52 100644 --- a/arch/inst/F/fmsub.s.yaml +++ b/arch/inst/F/fmsub.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmul.s.yaml b/arch/inst/F/fmul.s.yaml index c374137a1..66d5392b7 100644 --- a/arch/inst/F/fmul.s.yaml +++ b/arch/inst/F/fmul.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmv.w.x.yaml b/arch/inst/F/fmv.w.x.yaml index e65476f9a..4b593de63 100644 --- a/arch/inst/F/fmv.w.x.yaml +++ b/arch/inst/F/fmv.w.x.yaml @@ -46,7 +46,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmv.x.w.yaml b/arch/inst/F/fmv.x.w.yaml index baf798a9a..f8887234c 100644 --- a/arch/inst/F/fmv.x.w.yaml +++ b/arch/inst/F/fmv.x.w.yaml @@ -40,7 +40,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fnmadd.s.yaml b/arch/inst/F/fnmadd.s.yaml index 6d6675003..1b0eaecf5 100644 --- a/arch/inst/F/fnmadd.s.yaml +++ b/arch/inst/F/fnmadd.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fnmsub.s.yaml b/arch/inst/F/fnmsub.s.yaml index 61bfb97d1..c1a1997b8 100644 --- a/arch/inst/F/fnmsub.s.yaml +++ b/arch/inst/F/fnmsub.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fround.s.yaml b/arch/inst/F/fround.s.yaml index cd57704a9..83753b0a8 100644 --- a/arch/inst/F/fround.s.yaml +++ b/arch/inst/F/fround.s.yaml @@ -24,27 +24,23 @@ access: vu: always data_independent_timing: true operation(): | - + sail(): | { let rs1_val_S = F_S(rs1); - + match (select_instr_or_fcsr_rm(rm)) { None() => { handle_illegal(); RETIRE_FAIL }, Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false); - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/froundnx.s.yaml b/arch/inst/F/froundnx.s.yaml index 828dfd8b6..b3d8927e0 100644 --- a/arch/inst/F/froundnx.s.yaml +++ b/arch/inst/F/froundnx.s.yaml @@ -24,27 +24,23 @@ access: vu: always data_independent_timing: true operation(): | - + sail(): | { let rs1_val_S = F_S(rs1); - + match (select_instr_or_fcsr_rm(rm)) { None() => { handle_illegal(); RETIRE_FAIL }, Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true); - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fsgnj.s.yaml b/arch/inst/F/fsgnj.s.yaml index 46e49f2a0..544d564e1 100644 --- a/arch/inst/F/fsgnj.s.yaml +++ b/arch/inst/F/fsgnj.s.yaml @@ -49,15 +49,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsgnjn.s.yaml b/arch/inst/F/fsgnjn.s.yaml index a6b927efa..286f7bffd 100644 --- a/arch/inst/F/fsgnjn.s.yaml +++ b/arch/inst/F/fsgnjn.s.yaml @@ -48,15 +48,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsgnjx.s.yaml b/arch/inst/F/fsgnjx.s.yaml index 720e88e6f..e6fba2282 100644 --- a/arch/inst/F/fsgnjx.s.yaml +++ b/arch/inst/F/fsgnjx.s.yaml @@ -47,15 +47,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsqrt.s.yaml b/arch/inst/F/fsqrt.s.yaml index 5a4c708c6..a869687a2 100644 --- a/arch/inst/F/fsqrt.s.yaml +++ b/arch/inst/F/fsqrt.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fsub.s.yaml b/arch/inst/F/fsub.s.yaml index 7a2382675..ecce09860 100644 --- a/arch/inst/F/fsub.s.yaml +++ b/arch/inst/F/fsub.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fsw.yaml b/arch/inst/F/fsw.yaml index 047d045ad..d2f23782a 100644 --- a/arch/inst/F/fsw.yaml +++ b/arch/inst/F/fsw.yaml @@ -73,7 +73,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/H/hfence.gvma.yaml b/arch/inst/H/hfence.gvma.yaml index 9645a5c49..4bffc4c60 100644 --- a/arch/inst/H/hfence.gvma.yaml +++ b/arch/inst/H/hfence.gvma.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hfence.vvma.yaml b/arch/inst/H/hfence.vvma.yaml index e82abec6d..dd015039f 100644 --- a/arch/inst/H/hfence.vvma.yaml +++ b/arch/inst/H/hfence.vvma.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.b.yaml b/arch/inst/H/hlv.b.yaml index 227e2e5c0..c89ccd5c6 100644 --- a/arch/inst/H/hlv.b.yaml +++ b/arch/inst/H/hlv.b.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.bu.yaml b/arch/inst/H/hlv.bu.yaml index 2c5418ec2..5938d786a 100644 --- a/arch/inst/H/hlv.bu.yaml +++ b/arch/inst/H/hlv.bu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.d.yaml b/arch/inst/H/hlv.d.yaml index 919cc6875..98c27700b 100644 --- a/arch/inst/H/hlv.d.yaml +++ b/arch/inst/H/hlv.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hlv.h.yaml b/arch/inst/H/hlv.h.yaml index 8e7191cb0..6abbd7d9b 100644 --- a/arch/inst/H/hlv.h.yaml +++ b/arch/inst/H/hlv.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.hu.yaml b/arch/inst/H/hlv.hu.yaml index ac69cc127..99614784c 100644 --- a/arch/inst/H/hlv.hu.yaml +++ b/arch/inst/H/hlv.hu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.w.yaml b/arch/inst/H/hlv.w.yaml index 2c56a33d5..53d318cad 100644 --- a/arch/inst/H/hlv.w.yaml +++ b/arch/inst/H/hlv.w.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.wu.yaml b/arch/inst/H/hlv.wu.yaml index 9b2aa3fd4..2b8d652c9 100644 --- a/arch/inst/H/hlv.wu.yaml +++ b/arch/inst/H/hlv.wu.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hlvx.hu.yaml b/arch/inst/H/hlvx.hu.yaml index 20491065b..b527451cd 100644 --- a/arch/inst/H/hlvx.hu.yaml +++ b/arch/inst/H/hlvx.hu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlvx.wu.yaml b/arch/inst/H/hlvx.wu.yaml index 0f93baf90..d764afeb3 100644 --- a/arch/inst/H/hlvx.wu.yaml +++ b/arch/inst/H/hlvx.wu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.b.yaml b/arch/inst/H/hsv.b.yaml index b05b3dd89..03da5add6 100644 --- a/arch/inst/H/hsv.b.yaml +++ b/arch/inst/H/hsv.b.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.d.yaml b/arch/inst/H/hsv.d.yaml index 5fa349994..cda8a6b5b 100644 --- a/arch/inst/H/hsv.d.yaml +++ b/arch/inst/H/hsv.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hsv.h.yaml b/arch/inst/H/hsv.h.yaml index a307f6a5d..2ceb5b6b7 100644 --- a/arch/inst/H/hsv.h.yaml +++ b/arch/inst/H/hsv.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.w.yaml b/arch/inst/H/hsv.w.yaml index e5e778bbd..2379bc83a 100644 --- a/arch/inst/H/hsv.w.yaml +++ b/arch/inst/H/hsv.w.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/I/add.yaml b/arch/inst/I/add.yaml index 83706ffdb..e7038315a 100644 --- a/arch/inst/I/add.yaml +++ b/arch/inst/I/add.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 05db65005..74adf7a40 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index 36f72a725..9060c51ee 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -35,7 +35,3 @@ sail(): | X(rd) = sign_extend(result[31..0]); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addw.yaml b/arch/inst/I/addw.yaml index de8262a4e..2abb97ed7 100644 --- a/arch/inst/I/addw.yaml +++ b/arch/inst/I/addw.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/and.yaml b/arch/inst/I/and.yaml index 815c2cbe6..85a3a2022 100644 --- a/arch/inst/I/and.yaml +++ b/arch/inst/I/and.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 9ef488e42..708d67edb 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/auipc.yaml b/arch/inst/I/auipc.yaml index f65fdad53..3aa89876e 100644 --- a/arch/inst/I/auipc.yaml +++ b/arch/inst/I/auipc.yaml @@ -34,4 +34,3 @@ sail(): | X(rd) = ret; RETIRE_SUCCESS } - diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index 1dde072bf..a58721bb6 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -67,7 +67,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index 94edce67d..41369cb8e 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -33,7 +33,7 @@ operation(): | if ($signed(lhs) >= $signed(rhs)) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bgeu.yaml b/arch/inst/I/bgeu.yaml index 687a65116..daa2a490f 100644 --- a/arch/inst/I/bgeu.yaml +++ b/arch/inst/I/bgeu.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs >= rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index fca0c0025..beed9ad24 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -33,7 +33,7 @@ operation(): | if ($signed(lhs) < $signed(rhs)) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bltu.yaml b/arch/inst/I/bltu.yaml index 919c8cafc..bfc1ab77f 100644 --- a/arch/inst/I/bltu.yaml +++ b/arch/inst/I/bltu.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs < rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index 099ba0db8..96c72a066 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs != rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/ebreak.yaml b/arch/inst/I/ebreak.yaml index 5b08b202d..c13b7435f 100644 --- a/arch/inst/I/ebreak.yaml +++ b/arch/inst/I/ebreak.yaml @@ -40,7 +40,3 @@ sail(): | handle_mem_exception(PC, E_Breakpoint()); RETIRE_FAIL } - - - - diff --git a/arch/inst/I/ecall.yaml b/arch/inst/I/ecall.yaml index 2e6eb97d8..205b43201 100644 --- a/arch/inst/I/ecall.yaml +++ b/arch/inst/I/ecall.yaml @@ -71,7 +71,3 @@ sail(): | set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC)); RETIRE_FAIL } - - - - diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index 8edbc5776..b5173ec68 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -20,7 +20,7 @@ description: | [%autowidth] |=== 4+| `pred` 4+| `succ` - + | 27 | 26 |25 | 24 | 23 | 22 | 21| 20 | PI | PO |PR | PW | SI | SO |SR | SW |=== @@ -187,14 +187,14 @@ operation(): | if (pred_o) { pred_w = true; } if (succ_i) { succ_r = true; } if (succ_o) { succ_w = true; } - } + } } else if (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU) { if ((CSR[menvcfg].FIOM | CSR[henvcfg].FIOM) == 1) { if (pred_i) { pred_r = true; } if (pred_o) { pred_w = true; } if (succ_i) { succ_r = true; } if (succ_o) { succ_w = true; } - } + } } fence( @@ -216,7 +216,7 @@ sail(): | let fiom = is_fiom_active(); let pred = effective_fence_set(pred, fiom); let succ = effective_fence_set(succ, fiom); - + match (pred, succ) { (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()), (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()), @@ -227,16 +227,12 @@ sail(): | (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()), (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()), (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()), - + (_ : bits(4) , _ : bits(2) @ 0b00) => (), (_ : bits(2) @ 0b00, _ : bits(4) ) => (), - + _ => { print("FIXME: unsupported fence"); () } }; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index fdd537478..7c0b299d3 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index d3aebbf17..d3591fd2f 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -60,7 +60,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lb.yaml b/arch/inst/I/lb.yaml index 5c3f1edf9..96c27ead6 100644 --- a/arch/inst/I/lb.yaml +++ b/arch/inst/I/lb.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lbu.yaml b/arch/inst/I/lbu.yaml index ac4cd38a4..c04ff027f 100644 --- a/arch/inst/I/lbu.yaml +++ b/arch/inst/I/lbu.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/ld.yaml b/arch/inst/I/ld.yaml index c4c23b40b..dc00e7d60 100644 --- a/arch/inst/I/ld.yaml +++ b/arch/inst/I/ld.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lh.yaml b/arch/inst/I/lh.yaml index d316e61b8..22cfcfc0e 100644 --- a/arch/inst/I/lh.yaml +++ b/arch/inst/I/lh.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lhu.yaml b/arch/inst/I/lhu.yaml index bea81ff05..7c5da3396 100644 --- a/arch/inst/I/lhu.yaml +++ b/arch/inst/I/lhu.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lui.yaml b/arch/inst/I/lui.yaml index 4253ddb06..2401cf14a 100644 --- a/arch/inst/I/lui.yaml +++ b/arch/inst/I/lui.yaml @@ -35,7 +35,3 @@ sail(): | X(rd) = ret; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/lw.yaml b/arch/inst/I/lw.yaml index 99b721a42..db9e08794 100644 --- a/arch/inst/I/lw.yaml +++ b/arch/inst/I/lw.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lwu.yaml b/arch/inst/I/lwu.yaml index c33be3984..d20029bc5 100644 --- a/arch/inst/I/lwu.yaml +++ b/arch/inst/I/lwu.yaml @@ -59,7 +59,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/mret.yaml b/arch/inst/I/mret.yaml index 356654adc..114f68c33 100644 --- a/arch/inst/I/mret.yaml +++ b/arch/inst/I/mret.yaml @@ -42,7 +42,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/I/or.yaml b/arch/inst/I/or.yaml index 43cb35a28..0297a0cce 100644 --- a/arch/inst/I/or.yaml +++ b/arch/inst/I/or.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/ori.yaml b/arch/inst/I/ori.yaml index fe8a2fa0b..6785c87e3 100644 --- a/arch/inst/I/ori.yaml +++ b/arch/inst/I/ori.yaml @@ -32,11 +32,11 @@ operation(): | } else if (imm[4:0] == 1) { # prefetch.r instruction Bits<12> offset = {imm[11:5], rd}; - prefetch_read(offset); + prefetch_read(offset); } else if (imm[4:0] == 3) { # prefetch.r instruction Bits<12> offset = {imm[11:5], rd}; - prefetch_write(offset); + prefetch_write(offset); } } } @@ -66,7 +66,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sb.yaml b/arch/inst/I/sb.yaml index 06054e650..f0382d77a 100644 --- a/arch/inst/I/sb.yaml +++ b/arch/inst/I/sb.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sd.yaml b/arch/inst/I/sd.yaml index 62feb0693..0875a4966 100644 --- a/arch/inst/I/sd.yaml +++ b/arch/inst/I/sd.yaml @@ -74,7 +74,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sh.yaml b/arch/inst/I/sh.yaml index 5331d4839..8cfee4641 100644 --- a/arch/inst/I/sh.yaml +++ b/arch/inst/I/sh.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sll.yaml b/arch/inst/I/sll.yaml index bdf68a0d2..5695aeaf1 100644 --- a/arch/inst/I/sll.yaml +++ b/arch/inst/I/sll.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slli.yaml b/arch/inst/I/slli.yaml index 1a570568b..81a703f00 100644 --- a/arch/inst/I/slli.yaml +++ b/arch/inst/I/slli.yaml @@ -56,7 +56,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slliw.yaml b/arch/inst/I/slliw.yaml index 43b50fa90..b8092139f 100644 --- a/arch/inst/I/slliw.yaml +++ b/arch/inst/I/slliw.yaml @@ -40,7 +40,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sllw.yaml b/arch/inst/I/sllw.yaml index c745500f4..f540ff056 100644 --- a/arch/inst/I/sllw.yaml +++ b/arch/inst/I/sllw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index d66506891..1d1db5f42 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slti.yaml b/arch/inst/I/slti.yaml index 5b6abcb17..84fd55a48 100644 --- a/arch/inst/I/slti.yaml +++ b/arch/inst/I/slti.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index 4981a7298..14af783bb 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -48,7 +48,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index c1ee3b10d..b7087619b 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sra.yaml b/arch/inst/I/sra.yaml index c088d33a2..55ad5e33f 100644 --- a/arch/inst/I/sra.yaml +++ b/arch/inst/I/sra.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srai.yaml b/arch/inst/I/srai.yaml index e749b3992..862372f2a 100644 --- a/arch/inst/I/srai.yaml +++ b/arch/inst/I/srai.yaml @@ -58,7 +58,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sraiw.yaml b/arch/inst/I/sraiw.yaml index feb39990c..42fd48d10 100644 --- a/arch/inst/I/sraiw.yaml +++ b/arch/inst/I/sraiw.yaml @@ -43,7 +43,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sraw.yaml b/arch/inst/I/sraw.yaml index f64645d96..716fd413d 100644 --- a/arch/inst/I/sraw.yaml +++ b/arch/inst/I/sraw.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srl.yaml b/arch/inst/I/srl.yaml index 2ad1256d6..3219a49ab 100644 --- a/arch/inst/I/srl.yaml +++ b/arch/inst/I/srl.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srli.yaml b/arch/inst/I/srli.yaml index 90a1904fa..376ffc0cc 100644 --- a/arch/inst/I/srli.yaml +++ b/arch/inst/I/srli.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srliw.yaml b/arch/inst/I/srliw.yaml index f28912f01..db87361ea 100644 --- a/arch/inst/I/srliw.yaml +++ b/arch/inst/I/srliw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srlw.yaml b/arch/inst/I/srlw.yaml index 2df6b6721..7945a7285 100644 --- a/arch/inst/I/srlw.yaml +++ b/arch/inst/I/srlw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index a031a7782..85c792159 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 33d7354e0..8bc7e276f 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sw.yaml b/arch/inst/I/sw.yaml index 135995c75..0912e0448 100644 --- a/arch/inst/I/sw.yaml +++ b/arch/inst/I/sw.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/wfi.yaml b/arch/inst/I/wfi.yaml index 0eabdcc63..ce574396e 100644 --- a/arch/inst/I/wfi.yaml +++ b/arch/inst/I/wfi.yaml @@ -16,7 +16,7 @@ description: | .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior h| HS-mode h| U-mode h| VS-mode h| in VU-mode - | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) @@ -63,7 +63,7 @@ access_detail: | .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior h| HS-mode h| U-mode h| VS-mode h| in VU-mode - | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) @@ -121,7 +121,3 @@ sail(): | else { platform_wfi(); RETIRE_SUCCESS }, User => { handle_illegal(); RETIRE_FAIL } } - - - - diff --git a/arch/inst/I/xor.yaml b/arch/inst/I/xor.yaml index cec0aa761..e3438951d 100644 --- a/arch/inst/I/xor.yaml +++ b/arch/inst/I/xor.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index 169f3dfa3..d92c30742 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/M/div.yaml b/arch/inst/M/div.yaml index ebe7d999c..32b003a2d 100644 --- a/arch/inst/M/div.yaml +++ b/arch/inst/M/div.yaml @@ -8,7 +8,7 @@ description: | Divide rs1 by rs2, and store the result in rd. The remainder is discarded. Division by zero will put -1 into rd. - + Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd; definedBy: M @@ -68,7 +68,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divu.yaml b/arch/inst/M/divu.yaml index 0e0543cb6..75c43ff8d 100644 --- a/arch/inst/M/divu.yaml +++ b/arch/inst/M/divu.yaml @@ -6,7 +6,7 @@ name: divu long_name: Unsigned division description: | Divide unsigned values in rs1 by rs2, and store the result in rd. - + The remainder is discarded. If the value in rs2 is zero, rd gets the largest unsigned value. @@ -60,7 +60,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index 693d89a5a..09e928a5b 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -6,7 +6,7 @@ name: divuw long_name: Unsigned 32-bit division description: | Divide the unsigned 32-bit values in rs1 and rs2, and store the sign-extended result in rd. - + The remainder is discarded. If the value in rs2 is zero, rd is written with all 1s. @@ -66,7 +66,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 70b3517be..4a1674859 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -7,11 +7,11 @@ long_name: Signed 32-bit division description: | Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd. - + The remainder is discarded. Division by zero will put -1 into rd. - + Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd; definedBy: M @@ -75,7 +75,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mul.yaml b/arch/inst/M/mul.yaml index b8624a008..26c440799 100644 --- a/arch/inst/M/mul.yaml +++ b/arch/inst/M/mul.yaml @@ -64,7 +64,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulh.yaml b/arch/inst/M/mulh.yaml index 77921b4f0..3bb7d5b0a 100644 --- a/arch/inst/M/mulh.yaml +++ b/arch/inst/M/mulh.yaml @@ -69,7 +69,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulhsu.yaml b/arch/inst/M/mulhsu.yaml index ad58d2f7d..3fc37753b 100644 --- a/arch/inst/M/mulhsu.yaml +++ b/arch/inst/M/mulhsu.yaml @@ -65,7 +65,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulhu.yaml b/arch/inst/M/mulhu.yaml index af3838350..436668a0c 100644 --- a/arch/inst/M/mulhu.yaml +++ b/arch/inst/M/mulhu.yaml @@ -64,7 +64,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index 457ab0bac..bd6573725 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -66,7 +66,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/rem.yaml b/arch/inst/M/rem.yaml index 1f4dfd8c0..06367f68c 100644 --- a/arch/inst/M/rem.yaml +++ b/arch/inst/M/rem.yaml @@ -38,7 +38,7 @@ operation(): | # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined # to be the dividend X[rd] = src1; - + } else if ((src1 == {1'b1, {XLEN-1{1'b0}}}) && (src2 == {XLEN{1'b1}})) { # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined # to be zero @@ -65,7 +65,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remu.yaml b/arch/inst/M/remu.yaml index e3ad1c457..c668b94b5 100644 --- a/arch/inst/M/remu.yaml +++ b/arch/inst/M/remu.yaml @@ -55,7 +55,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index 64a52a1b8..4a4b348fa 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -67,7 +67,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index 9df788d0b..2c2a1500a 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -40,7 +40,7 @@ operation(): | # to be the dividend, sign extended to into the 64-bit register Bits<1> sign_bit = src1[31]; X[rd] = {{32{sign_bit}}, src1}; - + } else if ((src1 == {33'b1, 31'b0}) && (src2 == 32'b1)) { # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined # to be zero @@ -71,7 +71,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/Q/fadd.q.yaml b/arch/inst/Q/fadd.q.yaml index 7eaf4023f..3c9886e77 100644 --- a/arch/inst/Q/fadd.q.yaml +++ b/arch/inst/Q/fadd.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fclass.q.yaml b/arch/inst/Q/fclass.q.yaml index 528c2b469..230ff7773 100644 --- a/arch/inst/Q/fclass.q.yaml +++ b/arch/inst/Q/fclass.q.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.d.q.yaml b/arch/inst/Q/fcvt.d.q.yaml index 4aaa5d951..899950f8a 100644 --- a/arch/inst/Q/fcvt.d.q.yaml +++ b/arch/inst/Q/fcvt.d.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.h.q.yaml b/arch/inst/Q/fcvt.h.q.yaml index b0f9aaf6c..223ed9024 100644 --- a/arch/inst/Q/fcvt.h.q.yaml +++ b/arch/inst/Q/fcvt.h.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.l.q.yaml b/arch/inst/Q/fcvt.l.q.yaml index c6a76dbac..aae2df1a0 100644 --- a/arch/inst/Q/fcvt.l.q.yaml +++ b/arch/inst/Q/fcvt.l.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.lu.q.yaml b/arch/inst/Q/fcvt.lu.q.yaml index 0ee3cf010..1c75d28f0 100644 --- a/arch/inst/Q/fcvt.lu.q.yaml +++ b/arch/inst/Q/fcvt.lu.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.d.yaml b/arch/inst/Q/fcvt.q.d.yaml index a8c00bcd0..ce1ae3943 100644 --- a/arch/inst/Q/fcvt.q.d.yaml +++ b/arch/inst/Q/fcvt.q.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.h.yaml b/arch/inst/Q/fcvt.q.h.yaml index e315ca75c..541f2e10b 100644 --- a/arch/inst/Q/fcvt.q.h.yaml +++ b/arch/inst/Q/fcvt.q.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.l.yaml b/arch/inst/Q/fcvt.q.l.yaml index eff9c9342..092d57110 100644 --- a/arch/inst/Q/fcvt.q.l.yaml +++ b/arch/inst/Q/fcvt.q.l.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.lu.yaml b/arch/inst/Q/fcvt.q.lu.yaml index fcc7555a2..01572ba4a 100644 --- a/arch/inst/Q/fcvt.q.lu.yaml +++ b/arch/inst/Q/fcvt.q.lu.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.s.yaml b/arch/inst/Q/fcvt.q.s.yaml index f01c73066..6f4024c5b 100644 --- a/arch/inst/Q/fcvt.q.s.yaml +++ b/arch/inst/Q/fcvt.q.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.w.yaml b/arch/inst/Q/fcvt.q.w.yaml index e03a6f7af..d92b57d35 100644 --- a/arch/inst/Q/fcvt.q.w.yaml +++ b/arch/inst/Q/fcvt.q.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.wu.yaml b/arch/inst/Q/fcvt.q.wu.yaml index 2dd85ff07..05c0da5e1 100644 --- a/arch/inst/Q/fcvt.q.wu.yaml +++ b/arch/inst/Q/fcvt.q.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.s.q.yaml b/arch/inst/Q/fcvt.s.q.yaml index bb24b7ec7..a772446da 100644 --- a/arch/inst/Q/fcvt.s.q.yaml +++ b/arch/inst/Q/fcvt.s.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.w.q.yaml b/arch/inst/Q/fcvt.w.q.yaml index c414a695a..93b69f624 100644 --- a/arch/inst/Q/fcvt.w.q.yaml +++ b/arch/inst/Q/fcvt.w.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.wu.q.yaml b/arch/inst/Q/fcvt.wu.q.yaml index 54b157cdd..5d66b2af9 100644 --- a/arch/inst/Q/fcvt.wu.q.yaml +++ b/arch/inst/Q/fcvt.wu.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fdiv.q.yaml b/arch/inst/Q/fdiv.q.yaml index 56f1cd7c5..63e3fd2f8 100644 --- a/arch/inst/Q/fdiv.q.yaml +++ b/arch/inst/Q/fdiv.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/feq.q.yaml b/arch/inst/Q/feq.q.yaml index 8522aaa50..14286fb68 100644 --- a/arch/inst/Q/feq.q.yaml +++ b/arch/inst/Q/feq.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fle.q.yaml b/arch/inst/Q/fle.q.yaml index e684af70a..9ad903ba2 100644 --- a/arch/inst/Q/fle.q.yaml +++ b/arch/inst/Q/fle.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fleq.q.yaml b/arch/inst/Q/fleq.q.yaml index 155862a4c..5cb9b831e 100644 --- a/arch/inst/Q/fleq.q.yaml +++ b/arch/inst/Q/fleq.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fli.q.yaml b/arch/inst/Q/fli.q.yaml index 87b4eb709..aa7273830 100644 --- a/arch/inst/Q/fli.q.yaml +++ b/arch/inst/Q/fli.q.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/flq.yaml b/arch/inst/Q/flq.yaml index 4ca374e8d..d013be44a 100644 --- a/arch/inst/Q/flq.yaml +++ b/arch/inst/Q/flq.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/flt.q.yaml b/arch/inst/Q/flt.q.yaml index 404b81da4..5a400c776 100644 --- a/arch/inst/Q/flt.q.yaml +++ b/arch/inst/Q/flt.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fltq.q.yaml b/arch/inst/Q/fltq.q.yaml index 04ba644fb..b80f30f47 100644 --- a/arch/inst/Q/fltq.q.yaml +++ b/arch/inst/Q/fltq.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmadd.q.yaml b/arch/inst/Q/fmadd.q.yaml index 43f288a43..7977f8f95 100644 --- a/arch/inst/Q/fmadd.q.yaml +++ b/arch/inst/Q/fmadd.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmax.q.yaml b/arch/inst/Q/fmax.q.yaml index 5847f13ec..ff2069f09 100644 --- a/arch/inst/Q/fmax.q.yaml +++ b/arch/inst/Q/fmax.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmaxm.q.yaml b/arch/inst/Q/fmaxm.q.yaml index 8805cbb63..9ecca0aec 100644 --- a/arch/inst/Q/fmaxm.q.yaml +++ b/arch/inst/Q/fmaxm.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmin.q.yaml b/arch/inst/Q/fmin.q.yaml index c46d946df..62f30485b 100644 --- a/arch/inst/Q/fmin.q.yaml +++ b/arch/inst/Q/fmin.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fminm.q.yaml b/arch/inst/Q/fminm.q.yaml index 853f02fb6..516edc0bc 100644 --- a/arch/inst/Q/fminm.q.yaml +++ b/arch/inst/Q/fminm.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmsub.q.yaml b/arch/inst/Q/fmsub.q.yaml index f036761a9..c92ed5350 100644 --- a/arch/inst/Q/fmsub.q.yaml +++ b/arch/inst/Q/fmsub.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmul.q.yaml b/arch/inst/Q/fmul.q.yaml index be9d0d85d..c983cf8fb 100644 --- a/arch/inst/Q/fmul.q.yaml +++ b/arch/inst/Q/fmul.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmvh.x.q.yaml b/arch/inst/Q/fmvh.x.q.yaml index 73fbe8c67..f067240ac 100644 --- a/arch/inst/Q/fmvh.x.q.yaml +++ b/arch/inst/Q/fmvh.x.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmvp.q.x.yaml b/arch/inst/Q/fmvp.q.x.yaml index 2f450b0f6..258e7ccc8 100644 --- a/arch/inst/Q/fmvp.q.x.yaml +++ b/arch/inst/Q/fmvp.q.x.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fnmadd.q.yaml b/arch/inst/Q/fnmadd.q.yaml index 714401052..de290b9f3 100644 --- a/arch/inst/Q/fnmadd.q.yaml +++ b/arch/inst/Q/fnmadd.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fnmsub.q.yaml b/arch/inst/Q/fnmsub.q.yaml index a5d3ea469..805f14c42 100644 --- a/arch/inst/Q/fnmsub.q.yaml +++ b/arch/inst/Q/fnmsub.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fround.q.yaml b/arch/inst/Q/fround.q.yaml index 664a7afe8..ea1718ab4 100644 --- a/arch/inst/Q/fround.q.yaml +++ b/arch/inst/Q/fround.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/froundnx.q.yaml b/arch/inst/Q/froundnx.q.yaml index e1a7effcb..ffea7e08c 100644 --- a/arch/inst/Q/froundnx.q.yaml +++ b/arch/inst/Q/froundnx.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsgnj.q.yaml b/arch/inst/Q/fsgnj.q.yaml index 0406484c2..489b84990 100644 --- a/arch/inst/Q/fsgnj.q.yaml +++ b/arch/inst/Q/fsgnj.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fmv.q operation(): | - diff --git a/arch/inst/Q/fsgnjn.q.yaml b/arch/inst/Q/fsgnjn.q.yaml index 732314c79..3dc53bba5 100644 --- a/arch/inst/Q/fsgnjn.q.yaml +++ b/arch/inst/Q/fsgnjn.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fneg.q operation(): | - diff --git a/arch/inst/Q/fsgnjx.q.yaml b/arch/inst/Q/fsgnjx.q.yaml index 82c27a27e..2cec0796a 100644 --- a/arch/inst/Q/fsgnjx.q.yaml +++ b/arch/inst/Q/fsgnjx.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fabs.q operation(): | - diff --git a/arch/inst/Q/fsq.yaml b/arch/inst/Q/fsq.yaml index 564999cb9..1b74624a5 100644 --- a/arch/inst/Q/fsq.yaml +++ b/arch/inst/Q/fsq.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsqrt.q.yaml b/arch/inst/Q/fsqrt.q.yaml index 73c157676..9fa9ab346 100644 --- a/arch/inst/Q/fsqrt.q.yaml +++ b/arch/inst/Q/fsqrt.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsub.q.yaml b/arch/inst/Q/fsub.q.yaml index 7695cd763..0db8b161c 100644 --- a/arch/inst/Q/fsub.q.yaml +++ b/arch/inst/Q/fsub.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/S/sfence.vma.yaml b/arch/inst/S/sfence.vma.yaml index e7e380ddd..8852bf1cf 100644 --- a/arch/inst/S/sfence.vma.yaml +++ b/arch/inst/S/sfence.vma.yaml @@ -321,7 +321,3 @@ sail(): | Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/S/sret.yaml b/arch/inst/S/sret.yaml index f4a3f09e6..3dd2755d1 100644 --- a/arch/inst/S/sret.yaml +++ b/arch/inst/S/sret.yaml @@ -29,7 +29,7 @@ description: | |=== *When the current privlege mode is VS-mode* - + `sret` sets `vsstatus.SPP` = 0, `vsstatus.SIE` = `vstatus.SPIE`, and `vsstatus.SPIE` = 1, changes the privlege mode according to the table below, @@ -54,7 +54,7 @@ access: vs: sometimes vu: never access_detail: | - Access is determined as follows: + Access is determined as follows: [%autowidth] |=== @@ -92,7 +92,7 @@ operation(): | raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } else if (mode() == PrivilegeMode::VU || mode() == PrivilegeMode::VS) { raise (ExceptionCode::VirtualInstruction, mode(), $encoding); - } + } } } else { if (mode() != PrivilegeMode::U) { @@ -143,7 +143,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Sdext/dret.yaml b/arch/inst/Sdext/dret.yaml index e2ddf182c..e8e21a0ea 100644 --- a/arch/inst/Sdext/dret.yaml +++ b/arch/inst/Sdext/dret.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index cb1bf2f08..f5bd33fb3 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Smrnmi/mnret.yaml b/arch/inst/Smrnmi/mnret.yaml index 0b8abd110..5019c47bd 100644 --- a/arch/inst/Smrnmi/mnret.yaml +++ b/arch/inst/Smrnmi/mnret.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Svinval/hinval.gvma.yaml b/arch/inst/Svinval/hinval.gvma.yaml index 5e5da1154..e53479102 100644 --- a/arch/inst/Svinval/hinval.gvma.yaml +++ b/arch/inst/Svinval/hinval.gvma.yaml @@ -85,4 +85,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/Svinval/hinval.vvma.yaml b/arch/inst/Svinval/hinval.vvma.yaml index f987382aa..4b65e53c2 100644 --- a/arch/inst/Svinval/hinval.vvma.yaml +++ b/arch/inst/Svinval/hinval.vvma.yaml @@ -85,4 +85,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/Svinval/sfence.w.inval.yaml b/arch/inst/Svinval/sfence.w.inval.yaml index 3927e4811..037c5d0b3 100644 --- a/arch/inst/Svinval/sfence.w.inval.yaml +++ b/arch/inst/Svinval/sfence.w.inval.yaml @@ -38,4 +38,3 @@ operation(): | vma_type.gstage = true; } order_pgtbl_writes_before_vmafence(vma_type); - \ No newline at end of file diff --git a/arch/inst/Svinval/sinval.vma.yaml b/arch/inst/Svinval/sinval.vma.yaml index 4be763664..76f77099e 100644 --- a/arch/inst/Svinval/sinval.vma.yaml +++ b/arch/inst/Svinval/sinval.vma.yaml @@ -95,4 +95,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/V/vaadd.vv.yaml b/arch/inst/V/vaadd.vv.yaml index 329c014f9..3cbcf1241 100644 --- a/arch/inst/V/vaadd.vv.yaml +++ b/arch/inst/V/vaadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaadd.vx.yaml b/arch/inst/V/vaadd.vx.yaml index 12f3ab53c..e80615613 100644 --- a/arch/inst/V/vaadd.vx.yaml +++ b/arch/inst/V/vaadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaaddu.vv.yaml b/arch/inst/V/vaaddu.vv.yaml index 08fc153ce..6c9876175 100644 --- a/arch/inst/V/vaaddu.vv.yaml +++ b/arch/inst/V/vaaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaaddu.vx.yaml b/arch/inst/V/vaaddu.vx.yaml index e02ff1000..ed14af74b 100644 --- a/arch/inst/V/vaaddu.vx.yaml +++ b/arch/inst/V/vaaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vim.yaml b/arch/inst/V/vadc.vim.yaml index 4979da49e..a071d8dce 100644 --- a/arch/inst/V/vadc.vim.yaml +++ b/arch/inst/V/vadc.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vvm.yaml b/arch/inst/V/vadc.vvm.yaml index db8e26b38..8d3df8a97 100644 --- a/arch/inst/V/vadc.vvm.yaml +++ b/arch/inst/V/vadc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vxm.yaml b/arch/inst/V/vadc.vxm.yaml index 939eee7f2..5ea996a2a 100644 --- a/arch/inst/V/vadc.vxm.yaml +++ b/arch/inst/V/vadc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vi.yaml b/arch/inst/V/vadd.vi.yaml index f0246118a..d1f92d001 100644 --- a/arch/inst/V/vadd.vi.yaml +++ b/arch/inst/V/vadd.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vv.yaml b/arch/inst/V/vadd.vv.yaml index 94fc3d0f3..889991a14 100644 --- a/arch/inst/V/vadd.vv.yaml +++ b/arch/inst/V/vadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vx.yaml b/arch/inst/V/vadd.vx.yaml index 4067105f1..fde718be1 100644 --- a/arch/inst/V/vadd.vx.yaml +++ b/arch/inst/V/vadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vi.yaml b/arch/inst/V/vand.vi.yaml index eabfb2a01..fe43e62fd 100644 --- a/arch/inst/V/vand.vi.yaml +++ b/arch/inst/V/vand.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vv.yaml b/arch/inst/V/vand.vv.yaml index 2efc4a5a0..f01644810 100644 --- a/arch/inst/V/vand.vv.yaml +++ b/arch/inst/V/vand.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vx.yaml b/arch/inst/V/vand.vx.yaml index a0ba15ec1..efeb6977b 100644 --- a/arch/inst/V/vand.vx.yaml +++ b/arch/inst/V/vand.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasub.vv.yaml b/arch/inst/V/vasub.vv.yaml index fd156c277..7d1b7c282 100644 --- a/arch/inst/V/vasub.vv.yaml +++ b/arch/inst/V/vasub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasub.vx.yaml b/arch/inst/V/vasub.vx.yaml index b884f3844..54e8f87c6 100644 --- a/arch/inst/V/vasub.vx.yaml +++ b/arch/inst/V/vasub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasubu.vv.yaml b/arch/inst/V/vasubu.vv.yaml index 1597f0864..bc24e0a97 100644 --- a/arch/inst/V/vasubu.vv.yaml +++ b/arch/inst/V/vasubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasubu.vx.yaml b/arch/inst/V/vasubu.vx.yaml index 7f6f2ee4b..af8d897cc 100644 --- a/arch/inst/V/vasubu.vx.yaml +++ b/arch/inst/V/vasubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vcompress.vm.yaml b/arch/inst/V/vcompress.vm.yaml index b997ea0f3..fd84e7a33 100644 --- a/arch/inst/V/vcompress.vm.yaml +++ b/arch/inst/V/vcompress.vm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,19 +35,19 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + /* vcompress should always be executed with a vstart of 0 */ if start_element != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + /* body elements */ vd_idx : nat = 0; foreach (i from 0 to (num_elem - 1)) { @@ -71,9 +71,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vcpop.m.yaml b/arch/inst/V/vcpop.m.yaml index 788cfbadf..19bea2ad8 100644 --- a/arch/inst/V/vcpop.m.yaml +++ b/arch/inst/V/vcpop.m.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vdiv.vv.yaml b/arch/inst/V/vdiv.vv.yaml index 668b545cd..a11d7fca2 100644 --- a/arch/inst/V/vdiv.vv.yaml +++ b/arch/inst/V/vdiv.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdiv.vx.yaml b/arch/inst/V/vdiv.vx.yaml index 34dbf33f2..88fbb442a 100644 --- a/arch/inst/V/vdiv.vx.yaml +++ b/arch/inst/V/vdiv.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdivu.vv.yaml b/arch/inst/V/vdivu.vv.yaml index dad163f7a..c0f330bb1 100644 --- a/arch/inst/V/vdivu.vv.yaml +++ b/arch/inst/V/vdivu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdivu.vx.yaml b/arch/inst/V/vdivu.vx.yaml index 801e9f8eb..ebf0b05f1 100644 --- a/arch/inst/V/vdivu.vx.yaml +++ b/arch/inst/V/vdivu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfadd.vf.yaml b/arch/inst/V/vfadd.vf.yaml index 218f5ca4c..43a191d64 100644 --- a/arch/inst/V/vfadd.vf.yaml +++ b/arch/inst/V/vfadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfadd.vv.yaml b/arch/inst/V/vfadd.vv.yaml index 3ece00bef..e53b9c030 100644 --- a/arch/inst/V/vfadd.vv.yaml +++ b/arch/inst/V/vfadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfclass.v.yaml b/arch/inst/V/vfclass.v.yaml index 2feaae815..72947448c 100644 --- a/arch/inst/V/vfclass.v.yaml +++ b/arch/inst/V/vfclass.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.f.x.v.yaml b/arch/inst/V/vfcvt.f.x.v.yaml index 5e9165fc7..c94dd1143 100644 --- a/arch/inst/V/vfcvt.f.x.v.yaml +++ b/arch/inst/V/vfcvt.f.x.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.f.xu.v.yaml b/arch/inst/V/vfcvt.f.xu.v.yaml index c4ea16e9e..f0b93c864 100644 --- a/arch/inst/V/vfcvt.f.xu.v.yaml +++ b/arch/inst/V/vfcvt.f.xu.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.rtz.x.f.v.yaml b/arch/inst/V/vfcvt.rtz.x.f.v.yaml index e175d2caf..f2f2d7a34 100644 --- a/arch/inst/V/vfcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml index dd94a1aa6..111c59984 100644 --- a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.x.f.v.yaml b/arch/inst/V/vfcvt.x.f.v.yaml index afd39c892..8cca1f4db 100644 --- a/arch/inst/V/vfcvt.x.f.v.yaml +++ b/arch/inst/V/vfcvt.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.xu.f.v.yaml b/arch/inst/V/vfcvt.xu.f.v.yaml index a7c8b6148..7fa8aae9b 100644 --- a/arch/inst/V/vfcvt.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfdiv.vf.yaml b/arch/inst/V/vfdiv.vf.yaml index f46bae910..131540b4e 100644 --- a/arch/inst/V/vfdiv.vf.yaml +++ b/arch/inst/V/vfdiv.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfdiv.vv.yaml b/arch/inst/V/vfdiv.vv.yaml index 10de2949a..6590ecbf6 100644 --- a/arch/inst/V/vfdiv.vv.yaml +++ b/arch/inst/V/vfdiv.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfirst.m.yaml b/arch/inst/V/vfirst.m.yaml index e899e06e4..c05ebe85c 100644 --- a/arch/inst/V/vfirst.m.yaml +++ b/arch/inst/V/vfirst.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,28 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val); - + index : int = -1; foreach (i from 0 to (num_elem - 1)) { if index == -1 then { if mask[i] & vs2_val[i] then index = i; }; }; - + X(rd) = to_bits(sizeof(xlen), index); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmacc.vf.yaml b/arch/inst/V/vfmacc.vf.yaml index 99ce1b313..9c6529d0c 100644 --- a/arch/inst/V/vfmacc.vf.yaml +++ b/arch/inst/V/vfmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmacc.vv.yaml b/arch/inst/V/vfmacc.vv.yaml index b16c389a2..ae596e3e3 100644 --- a/arch/inst/V/vfmacc.vv.yaml +++ b/arch/inst/V/vfmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmadd.vf.yaml b/arch/inst/V/vfmadd.vf.yaml index 8ebc28dd0..14d73f06f 100644 --- a/arch/inst/V/vfmadd.vf.yaml +++ b/arch/inst/V/vfmadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmadd.vv.yaml b/arch/inst/V/vfmadd.vv.yaml index c4828106e..2541125be 100644 --- a/arch/inst/V/vfmadd.vv.yaml +++ b/arch/inst/V/vfmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmax.vf.yaml b/arch/inst/V/vfmax.vf.yaml index 552c300ef..0cc30b734 100644 --- a/arch/inst/V/vfmax.vf.yaml +++ b/arch/inst/V/vfmax.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmax.vv.yaml b/arch/inst/V/vfmax.vv.yaml index 287666945..743ea0f91 100644 --- a/arch/inst/V/vfmax.vv.yaml +++ b/arch/inst/V/vfmax.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmerge.vfm.yaml b/arch/inst/V/vfmerge.vfm.yaml index 254c60810..86dd3a028 100644 --- a/arch/inst/V/vfmerge.vfm.yaml +++ b/arch/inst/V/vfmerge.vfm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,19 +37,19 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_fp_vd_masked(vd, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -64,9 +64,8 @@ sail(): | result[i] = if vm_val[i] then rs1_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmin.vf.yaml b/arch/inst/V/vfmin.vf.yaml index e6d871cd0..ab540d32b 100644 --- a/arch/inst/V/vfmin.vf.yaml +++ b/arch/inst/V/vfmin.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmin.vv.yaml b/arch/inst/V/vfmin.vv.yaml index abf1b633b..991efa7e8 100644 --- a/arch/inst/V/vfmin.vv.yaml +++ b/arch/inst/V/vfmin.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsac.vf.yaml b/arch/inst/V/vfmsac.vf.yaml index 1f43e1cd8..34c3c371b 100644 --- a/arch/inst/V/vfmsac.vf.yaml +++ b/arch/inst/V/vfmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsac.vv.yaml b/arch/inst/V/vfmsac.vv.yaml index b4215b02e..1e734383a 100644 --- a/arch/inst/V/vfmsac.vv.yaml +++ b/arch/inst/V/vfmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsub.vf.yaml b/arch/inst/V/vfmsub.vf.yaml index 785099841..ced3598cb 100644 --- a/arch/inst/V/vfmsub.vf.yaml +++ b/arch/inst/V/vfmsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsub.vv.yaml b/arch/inst/V/vfmsub.vv.yaml index cf3a1fadb..e33500bb5 100644 --- a/arch/inst/V/vfmsub.vv.yaml +++ b/arch/inst/V/vfmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmul.vf.yaml b/arch/inst/V/vfmul.vf.yaml index 25c1b668d..74a603000 100644 --- a/arch/inst/V/vfmul.vf.yaml +++ b/arch/inst/V/vfmul.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmul.vv.yaml b/arch/inst/V/vfmul.vv.yaml index b569def98..f1cb3a8c7 100644 --- a/arch/inst/V/vfmul.vv.yaml +++ b/arch/inst/V/vfmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.f.s.yaml b/arch/inst/V/vfmv.f.s.yaml index 2a0a9885c..c3f72cd96 100644 --- a/arch/inst/V/vfmv.f.s.yaml +++ b/arch/inst/V/vfmv.f.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,14 +31,14 @@ sail(): | let rm_3b = fcsr.FRM(); let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) | SEW > sizeof(flen) then { handle_illegal(); return RETIRE_FAIL }; assert(num_elem > 0 & SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); match 'm { 16 => F_H(rd) = vs2_val[0], @@ -46,7 +46,6 @@ sail(): | 64 => F_D(rd) = vs2_val[0] }; vstart = zeros(); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.s.f.yaml b/arch/inst/V/vfmv.s.f.yaml index 04ffb840c..80b57dc40 100644 --- a/arch/inst/V/vfmv.s.f.yaml +++ b/arch/inst/V/vfmv.s.f.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,24 +31,24 @@ sail(): | let rm_3b = fcsr.FRM(); let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(num_elem > 0 & SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); - + /* one body element */ if mask[0] then result[0] = rs1_val; - + /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); foreach (i from 1 to (num_elem - 1)) { @@ -57,9 +57,8 @@ sail(): | AGNOSTIC => vd_val[i] /* TODO: configuration support */ } }; - + write_vreg(num_elem, SEW, 0, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.v.f.yaml b/arch/inst/V/vfmv.v.f.yaml index 51b4404e3..e1fe60deb 100644 --- a/arch/inst/V/vfmv.v.f.yaml +++ b/arch/inst/V/vfmv.v.f.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,27 +32,26 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = rs1_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.f.w.yaml b/arch/inst/V/vfncvt.f.f.w.yaml index c193f5a80..d07719336 100644 --- a/arch/inst/V/vfncvt.f.f.w.yaml +++ b/arch/inst/V/vfncvt.f.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.x.w.yaml b/arch/inst/V/vfncvt.f.x.w.yaml index 5c6c764e8..64076200d 100644 --- a/arch/inst/V/vfncvt.f.x.w.yaml +++ b/arch/inst/V/vfncvt.f.x.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.xu.w.yaml b/arch/inst/V/vfncvt.f.xu.w.yaml index 37df32206..1ffb9a8cb 100644 --- a/arch/inst/V/vfncvt.f.xu.w.yaml +++ b/arch/inst/V/vfncvt.f.xu.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rod.f.f.w.yaml b/arch/inst/V/vfncvt.rod.f.f.w.yaml index 574c2c172..7b5c051c7 100644 --- a/arch/inst/V/vfncvt.rod.f.f.w.yaml +++ b/arch/inst/V/vfncvt.rod.f.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rtz.x.f.w.yaml b/arch/inst/V/vfncvt.rtz.x.f.w.yaml index d7ea4bec1..a4537a2e7 100644 --- a/arch/inst/V/vfncvt.rtz.x.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.x.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml index 2bea9fff1..62bede1c4 100644 --- a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.x.f.w.yaml b/arch/inst/V/vfncvt.x.f.w.yaml index f20b998b5..75ff14b03 100644 --- a/arch/inst/V/vfncvt.x.f.w.yaml +++ b/arch/inst/V/vfncvt.x.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.xu.f.w.yaml b/arch/inst/V/vfncvt.xu.f.w.yaml index 6878beea4..37345ccd0 100644 --- a/arch/inst/V/vfncvt.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.xu.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmacc.vf.yaml b/arch/inst/V/vfnmacc.vf.yaml index 56e6ca4f2..b2c079a45 100644 --- a/arch/inst/V/vfnmacc.vf.yaml +++ b/arch/inst/V/vfnmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmacc.vv.yaml b/arch/inst/V/vfnmacc.vv.yaml index e33d710ef..7d09fa94d 100644 --- a/arch/inst/V/vfnmacc.vv.yaml +++ b/arch/inst/V/vfnmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmadd.vf.yaml b/arch/inst/V/vfnmadd.vf.yaml index 4f55a64ea..4023db2a3 100644 --- a/arch/inst/V/vfnmadd.vf.yaml +++ b/arch/inst/V/vfnmadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmadd.vv.yaml b/arch/inst/V/vfnmadd.vv.yaml index adcdaa931..2f25198c4 100644 --- a/arch/inst/V/vfnmadd.vv.yaml +++ b/arch/inst/V/vfnmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsac.vf.yaml b/arch/inst/V/vfnmsac.vf.yaml index bbfd36edd..2e2a4c720 100644 --- a/arch/inst/V/vfnmsac.vf.yaml +++ b/arch/inst/V/vfnmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsac.vv.yaml b/arch/inst/V/vfnmsac.vv.yaml index ebece29cb..28eddb89c 100644 --- a/arch/inst/V/vfnmsac.vv.yaml +++ b/arch/inst/V/vfnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsub.vf.yaml b/arch/inst/V/vfnmsub.vf.yaml index 2af355ef8..efab79dae 100644 --- a/arch/inst/V/vfnmsub.vf.yaml +++ b/arch/inst/V/vfnmsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsub.vv.yaml b/arch/inst/V/vfnmsub.vv.yaml index 3272bacc4..d279ebff9 100644 --- a/arch/inst/V/vfnmsub.vv.yaml +++ b/arch/inst/V/vfnmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrdiv.vf.yaml b/arch/inst/V/vfrdiv.vf.yaml index 2beaafcb7..78f64d7f1 100644 --- a/arch/inst/V/vfrdiv.vf.yaml +++ b/arch/inst/V/vfrdiv.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrec7.v.yaml b/arch/inst/V/vfrec7.v.yaml index e17cc89b4..40a7439bd 100644 --- a/arch/inst/V/vfrec7.v.yaml +++ b/arch/inst/V/vfrec7.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfredmax.vs.yaml b/arch/inst/V/vfredmax.vs.yaml index 9162d9cfd..12277a66b 100644 --- a/arch/inst/V/vfredmax.vs.yaml +++ b/arch/inst/V/vfredmax.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredmin.vs.yaml b/arch/inst/V/vfredmin.vs.yaml index 2421e017f..b4609fd35 100644 --- a/arch/inst/V/vfredmin.vs.yaml +++ b/arch/inst/V/vfredmin.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredosum.vs.yaml b/arch/inst/V/vfredosum.vs.yaml index e343e1628..bea668e79 100644 --- a/arch/inst/V/vfredosum.vs.yaml +++ b/arch/inst/V/vfredosum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredusum.vs.yaml b/arch/inst/V/vfredusum.vs.yaml index 2b6938156..b8e38ee7d 100644 --- a/arch/inst/V/vfredusum.vs.yaml +++ b/arch/inst/V/vfredusum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfrsqrt7.v.yaml b/arch/inst/V/vfrsqrt7.v.yaml index 2276abd0c..fbbf128cd 100644 --- a/arch/inst/V/vfrsqrt7.v.yaml +++ b/arch/inst/V/vfrsqrt7.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrsub.vf.yaml b/arch/inst/V/vfrsub.vf.yaml index 7175d5ea1..1dea2de7e 100644 --- a/arch/inst/V/vfrsub.vf.yaml +++ b/arch/inst/V/vfrsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnj.vf.yaml b/arch/inst/V/vfsgnj.vf.yaml index 46fbfb495..b5bad7a7b 100644 --- a/arch/inst/V/vfsgnj.vf.yaml +++ b/arch/inst/V/vfsgnj.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnj.vv.yaml b/arch/inst/V/vfsgnj.vv.yaml index f256057d4..c62ba75b2 100644 --- a/arch/inst/V/vfsgnj.vv.yaml +++ b/arch/inst/V/vfsgnj.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjn.vf.yaml b/arch/inst/V/vfsgnjn.vf.yaml index 6de073a93..aadd118ee 100644 --- a/arch/inst/V/vfsgnjn.vf.yaml +++ b/arch/inst/V/vfsgnjn.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjn.vv.yaml b/arch/inst/V/vfsgnjn.vv.yaml index 3e4d499fa..f5e6507af 100644 --- a/arch/inst/V/vfsgnjn.vv.yaml +++ b/arch/inst/V/vfsgnjn.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjx.vf.yaml b/arch/inst/V/vfsgnjx.vf.yaml index eb4597bdc..39e3e1bcc 100644 --- a/arch/inst/V/vfsgnjx.vf.yaml +++ b/arch/inst/V/vfsgnjx.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjx.vv.yaml b/arch/inst/V/vfsgnjx.vv.yaml index 3b16d69b6..7f674c9dc 100644 --- a/arch/inst/V/vfsgnjx.vv.yaml +++ b/arch/inst/V/vfsgnjx.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfslide1down.vf.yaml b/arch/inst/V/vfslide1down.vf.yaml index 525f9fb53..e30cfe155 100644 --- a/arch/inst/V/vfslide1down.vf.yaml +++ b/arch/inst/V/vfslide1down.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfslide1up.vf.yaml b/arch/inst/V/vfslide1up.vf.yaml index a76a2c433..eb6f1da87 100644 --- a/arch/inst/V/vfslide1up.vf.yaml +++ b/arch/inst/V/vfslide1up.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsqrt.v.yaml b/arch/inst/V/vfsqrt.v.yaml index f3ddf5924..9fa78136e 100644 --- a/arch/inst/V/vfsqrt.v.yaml +++ b/arch/inst/V/vfsqrt.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsub.vf.yaml b/arch/inst/V/vfsub.vf.yaml index d2ebfd447..d55004891 100644 --- a/arch/inst/V/vfsub.vf.yaml +++ b/arch/inst/V/vfsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsub.vv.yaml b/arch/inst/V/vfsub.vv.yaml index 6a91b4549..099d1ca6e 100644 --- a/arch/inst/V/vfsub.vv.yaml +++ b/arch/inst/V/vfsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.vf.yaml b/arch/inst/V/vfwadd.vf.yaml index 26979ae97..8449fafc3 100644 --- a/arch/inst/V/vfwadd.vf.yaml +++ b/arch/inst/V/vfwadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.vv.yaml b/arch/inst/V/vfwadd.vv.yaml index 2a9d94d13..fdc57af86 100644 --- a/arch/inst/V/vfwadd.vv.yaml +++ b/arch/inst/V/vfwadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.wf.yaml b/arch/inst/V/vfwadd.wf.yaml index 984920924..6a169ba6a 100644 --- a/arch/inst/V/vfwadd.wf.yaml +++ b/arch/inst/V/vfwadd.wf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,24 +38,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.wv.yaml b/arch/inst/V/vfwadd.wv.yaml index 1fd17c23d..668fde563 100644 --- a/arch/inst/V/vfwadd.wv.yaml +++ b/arch/inst/V/vfwadd.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.f.v.yaml b/arch/inst/V/vfwcvt.f.f.v.yaml index 487d919fb..13891efc9 100644 --- a/arch/inst/V/vfwcvt.f.f.v.yaml +++ b/arch/inst/V/vfwcvt.f.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.x.v.yaml b/arch/inst/V/vfwcvt.f.x.v.yaml index f6c784e06..a4cac43c7 100644 --- a/arch/inst/V/vfwcvt.f.x.v.yaml +++ b/arch/inst/V/vfwcvt.f.x.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.xu.v.yaml b/arch/inst/V/vfwcvt.f.xu.v.yaml index da71b1a3b..2451307f0 100644 --- a/arch/inst/V/vfwcvt.f.xu.v.yaml +++ b/arch/inst/V/vfwcvt.f.xu.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml index 751d91c8b..ccd031fbb 100644 --- a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml index 271c14619..2df02a61b 100644 --- a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.x.f.v.yaml b/arch/inst/V/vfwcvt.x.f.v.yaml index e6d8434a4..b6337cd14 100644 --- a/arch/inst/V/vfwcvt.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.xu.f.v.yaml b/arch/inst/V/vfwcvt.xu.f.v.yaml index fe088fcb2..dc47501e7 100644 --- a/arch/inst/V/vfwcvt.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmacc.vf.yaml b/arch/inst/V/vfwmacc.vf.yaml index 0f015804a..bb3c336f8 100644 --- a/arch/inst/V/vfwmacc.vf.yaml +++ b/arch/inst/V/vfwmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmacc.vv.yaml b/arch/inst/V/vfwmacc.vv.yaml index 0875df457..18452f228 100644 --- a/arch/inst/V/vfwmacc.vv.yaml +++ b/arch/inst/V/vfwmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmsac.vf.yaml b/arch/inst/V/vfwmsac.vf.yaml index 0c33d367f..2b4821948 100644 --- a/arch/inst/V/vfwmsac.vf.yaml +++ b/arch/inst/V/vfwmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmsac.vv.yaml b/arch/inst/V/vfwmsac.vv.yaml index d2b52d9c8..06a86bfb5 100644 --- a/arch/inst/V/vfwmsac.vv.yaml +++ b/arch/inst/V/vfwmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmul.vf.yaml b/arch/inst/V/vfwmul.vf.yaml index db717c712..c1b8c8982 100644 --- a/arch/inst/V/vfwmul.vf.yaml +++ b/arch/inst/V/vfwmul.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmul.vv.yaml b/arch/inst/V/vfwmul.vv.yaml index 8e07e64d7..e91a5c378 100644 --- a/arch/inst/V/vfwmul.vv.yaml +++ b/arch/inst/V/vfwmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmacc.vf.yaml b/arch/inst/V/vfwnmacc.vf.yaml index d65aeb070..67e5dcfe6 100644 --- a/arch/inst/V/vfwnmacc.vf.yaml +++ b/arch/inst/V/vfwnmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmacc.vv.yaml b/arch/inst/V/vfwnmacc.vv.yaml index f67004249..396840026 100644 --- a/arch/inst/V/vfwnmacc.vv.yaml +++ b/arch/inst/V/vfwnmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmsac.vf.yaml b/arch/inst/V/vfwnmsac.vf.yaml index 42e73c725..f5dc85df9 100644 --- a/arch/inst/V/vfwnmsac.vf.yaml +++ b/arch/inst/V/vfwnmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmsac.vv.yaml b/arch/inst/V/vfwnmsac.vv.yaml index 4ab4e7dfc..17af8f339 100644 --- a/arch/inst/V/vfwnmsac.vv.yaml +++ b/arch/inst/V/vfwnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwredosum.vs.yaml b/arch/inst/V/vfwredosum.vs.yaml index 86b130f17..ea97af98a 100644 --- a/arch/inst/V/vfwredosum.vs.yaml +++ b/arch/inst/V/vfwredosum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfwredusum.vs.yaml b/arch/inst/V/vfwredusum.vs.yaml index 4e076feea..b0e69de55 100644 --- a/arch/inst/V/vfwredusum.vs.yaml +++ b/arch/inst/V/vfwredusum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfwsub.vf.yaml b/arch/inst/V/vfwsub.vf.yaml index 6ebf50ccd..d06f57f18 100644 --- a/arch/inst/V/vfwsub.vf.yaml +++ b/arch/inst/V/vfwsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.vv.yaml b/arch/inst/V/vfwsub.vv.yaml index 31b111c9e..02b06af2f 100644 --- a/arch/inst/V/vfwsub.vv.yaml +++ b/arch/inst/V/vfwsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.wf.yaml b/arch/inst/V/vfwsub.wf.yaml index 5ec7bd5d3..1ec5f744c 100644 --- a/arch/inst/V/vfwsub.wf.yaml +++ b/arch/inst/V/vfwsub.wf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,24 +38,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.wv.yaml b/arch/inst/V/vfwsub.wv.yaml index f60f19a6a..c60ee91d1 100644 --- a/arch/inst/V/vfwsub.wv.yaml +++ b/arch/inst/V/vfwsub.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vid.v.yaml b/arch/inst/V/vid.v.yaml index 85f143afa..b5c27cc73 100644 --- a/arch/inst/V/vid.v.yaml +++ b/arch/inst/V/vid.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,25 +31,24 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = to_bits(SEW, i) }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/viota.m.yaml b/arch/inst/V/viota.m.yaml index f4b1e376e..1991cdaa9 100644 --- a/arch/inst/V/viota.m.yaml +++ b/arch/inst/V/viota.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + sum : int = 0; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | if vs2_val[i] then sum = sum + 1 } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vl1re16.v.yaml b/arch/inst/V/vl1re16.v.yaml index 2d2c4c2eb..0a6cb1075 100644 --- a/arch/inst/V/vl1re16.v.yaml +++ b/arch/inst/V/vl1re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re32.v.yaml b/arch/inst/V/vl1re32.v.yaml index e04d176d6..294c7203e 100644 --- a/arch/inst/V/vl1re32.v.yaml +++ b/arch/inst/V/vl1re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re64.v.yaml b/arch/inst/V/vl1re64.v.yaml index b45371d96..0c1a4e6a3 100644 --- a/arch/inst/V/vl1re64.v.yaml +++ b/arch/inst/V/vl1re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re8.v.yaml b/arch/inst/V/vl1re8.v.yaml index 8cef1447f..799791033 100644 --- a/arch/inst/V/vl1re8.v.yaml +++ b/arch/inst/V/vl1re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re16.v.yaml b/arch/inst/V/vl2re16.v.yaml index ff73f66ce..e0cab471f 100644 --- a/arch/inst/V/vl2re16.v.yaml +++ b/arch/inst/V/vl2re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re32.v.yaml b/arch/inst/V/vl2re32.v.yaml index 3e258e9cc..e8e6aeb44 100644 --- a/arch/inst/V/vl2re32.v.yaml +++ b/arch/inst/V/vl2re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re64.v.yaml b/arch/inst/V/vl2re64.v.yaml index 06d9c4ba1..785489b92 100644 --- a/arch/inst/V/vl2re64.v.yaml +++ b/arch/inst/V/vl2re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re8.v.yaml b/arch/inst/V/vl2re8.v.yaml index 4820ef3fa..70f528b52 100644 --- a/arch/inst/V/vl2re8.v.yaml +++ b/arch/inst/V/vl2re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re16.v.yaml b/arch/inst/V/vl4re16.v.yaml index 1d091962f..6a8533926 100644 --- a/arch/inst/V/vl4re16.v.yaml +++ b/arch/inst/V/vl4re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re32.v.yaml b/arch/inst/V/vl4re32.v.yaml index e2caa0c2c..50ffcb9b7 100644 --- a/arch/inst/V/vl4re32.v.yaml +++ b/arch/inst/V/vl4re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re64.v.yaml b/arch/inst/V/vl4re64.v.yaml index 01b32c48a..8db40b0c6 100644 --- a/arch/inst/V/vl4re64.v.yaml +++ b/arch/inst/V/vl4re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re8.v.yaml b/arch/inst/V/vl4re8.v.yaml index a56cc57e5..0361ac50a 100644 --- a/arch/inst/V/vl4re8.v.yaml +++ b/arch/inst/V/vl4re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re16.v.yaml b/arch/inst/V/vl8re16.v.yaml index 3a9d1b0ae..26214f47d 100644 --- a/arch/inst/V/vl8re16.v.yaml +++ b/arch/inst/V/vl8re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re32.v.yaml b/arch/inst/V/vl8re32.v.yaml index 747cf5438..b55e4987f 100644 --- a/arch/inst/V/vl8re32.v.yaml +++ b/arch/inst/V/vl8re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re64.v.yaml b/arch/inst/V/vl8re64.v.yaml index 3c32d3562..1d992927d 100644 --- a/arch/inst/V/vl8re64.v.yaml +++ b/arch/inst/V/vl8re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re8.v.yaml b/arch/inst/V/vl8re8.v.yaml index f424ac472..e871bb99d 100644 --- a/arch/inst/V/vl8re8.v.yaml +++ b/arch/inst/V/vl8re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vle16.v.yaml b/arch/inst/V/vle16.v.yaml index 993937d6e..b936f52ac 100644 --- a/arch/inst/V/vle16.v.yaml +++ b/arch/inst/V/vle16.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle16ff.v.yaml b/arch/inst/V/vle16ff.v.yaml index e27dfed29..50b881227 100644 --- a/arch/inst/V/vle16ff.v.yaml +++ b/arch/inst/V/vle16ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle32.v.yaml b/arch/inst/V/vle32.v.yaml index 9106cbb53..492542605 100644 --- a/arch/inst/V/vle32.v.yaml +++ b/arch/inst/V/vle32.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle32ff.v.yaml b/arch/inst/V/vle32ff.v.yaml index c19956a1b..4de0bad43 100644 --- a/arch/inst/V/vle32ff.v.yaml +++ b/arch/inst/V/vle32ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle64.v.yaml b/arch/inst/V/vle64.v.yaml index 5f455f5a7..75a9f9bb0 100644 --- a/arch/inst/V/vle64.v.yaml +++ b/arch/inst/V/vle64.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle64ff.v.yaml b/arch/inst/V/vle64ff.v.yaml index acafd2aa6..d9efeff02 100644 --- a/arch/inst/V/vle64ff.v.yaml +++ b/arch/inst/V/vle64ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle8.v.yaml b/arch/inst/V/vle8.v.yaml index 12169fac5..a36a00ac1 100644 --- a/arch/inst/V/vle8.v.yaml +++ b/arch/inst/V/vle8.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle8ff.v.yaml b/arch/inst/V/vle8ff.v.yaml index 58faf7fe8..e53ade80d 100644 --- a/arch/inst/V/vle8ff.v.yaml +++ b/arch/inst/V/vle8ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlm.v.yaml b/arch/inst/V/vlm.v.yaml index 87096feca..e7b17a708 100644 --- a/arch/inst/V/vlm.v.yaml +++ b/arch/inst/V/vlm.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,10 +33,9 @@ sail(): | let vl_val = unsigned(vl); let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ let num_elem = get_num_elem(EMUL_pow, EEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(evl >= 0); process_vm(vd_or_vs3, rs1, num_elem, evl, op) } - diff --git a/arch/inst/V/vloxei16.v.yaml b/arch/inst/V/vloxei16.v.yaml index 4c080f551..333150bfc 100644 --- a/arch/inst/V/vloxei16.v.yaml +++ b/arch/inst/V/vloxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei32.v.yaml b/arch/inst/V/vloxei32.v.yaml index 61a158182..42334c5ef 100644 --- a/arch/inst/V/vloxei32.v.yaml +++ b/arch/inst/V/vloxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei64.v.yaml b/arch/inst/V/vloxei64.v.yaml index 9e4ed92f7..cc45f490e 100644 --- a/arch/inst/V/vloxei64.v.yaml +++ b/arch/inst/V/vloxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei8.v.yaml b/arch/inst/V/vloxei8.v.yaml index c3dfe99ee..3db6d4ebb 100644 --- a/arch/inst/V/vloxei8.v.yaml +++ b/arch/inst/V/vloxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxseg2ei16.v.yaml b/arch/inst/V/vloxseg2ei16.v.yaml index 5aeb4b87b..8c0275846 100644 --- a/arch/inst/V/vloxseg2ei16.v.yaml +++ b/arch/inst/V/vloxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei32.v.yaml b/arch/inst/V/vloxseg2ei32.v.yaml index 5300087df..8cf8eed09 100644 --- a/arch/inst/V/vloxseg2ei32.v.yaml +++ b/arch/inst/V/vloxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei64.v.yaml b/arch/inst/V/vloxseg2ei64.v.yaml index 31f4736c5..b441647b1 100644 --- a/arch/inst/V/vloxseg2ei64.v.yaml +++ b/arch/inst/V/vloxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei8.v.yaml b/arch/inst/V/vloxseg2ei8.v.yaml index fdbb69faf..507fe4f0a 100644 --- a/arch/inst/V/vloxseg2ei8.v.yaml +++ b/arch/inst/V/vloxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei16.v.yaml b/arch/inst/V/vloxseg3ei16.v.yaml index 7564e9cbb..674b1aa84 100644 --- a/arch/inst/V/vloxseg3ei16.v.yaml +++ b/arch/inst/V/vloxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei32.v.yaml b/arch/inst/V/vloxseg3ei32.v.yaml index c6519f8a4..a2a61f851 100644 --- a/arch/inst/V/vloxseg3ei32.v.yaml +++ b/arch/inst/V/vloxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei64.v.yaml b/arch/inst/V/vloxseg3ei64.v.yaml index fb86e732d..61cc36c82 100644 --- a/arch/inst/V/vloxseg3ei64.v.yaml +++ b/arch/inst/V/vloxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei8.v.yaml b/arch/inst/V/vloxseg3ei8.v.yaml index 5ca294825..cd4398986 100644 --- a/arch/inst/V/vloxseg3ei8.v.yaml +++ b/arch/inst/V/vloxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei16.v.yaml b/arch/inst/V/vloxseg4ei16.v.yaml index 1960fce8d..a62650087 100644 --- a/arch/inst/V/vloxseg4ei16.v.yaml +++ b/arch/inst/V/vloxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei32.v.yaml b/arch/inst/V/vloxseg4ei32.v.yaml index d136ebbc1..d97c7fb95 100644 --- a/arch/inst/V/vloxseg4ei32.v.yaml +++ b/arch/inst/V/vloxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei64.v.yaml b/arch/inst/V/vloxseg4ei64.v.yaml index 296266ecc..fcfb19b82 100644 --- a/arch/inst/V/vloxseg4ei64.v.yaml +++ b/arch/inst/V/vloxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei8.v.yaml b/arch/inst/V/vloxseg4ei8.v.yaml index f59d7f753..d5c0d5054 100644 --- a/arch/inst/V/vloxseg4ei8.v.yaml +++ b/arch/inst/V/vloxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei16.v.yaml b/arch/inst/V/vloxseg5ei16.v.yaml index 3485edbd2..3512fb892 100644 --- a/arch/inst/V/vloxseg5ei16.v.yaml +++ b/arch/inst/V/vloxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei32.v.yaml b/arch/inst/V/vloxseg5ei32.v.yaml index 18afff163..3068b99f0 100644 --- a/arch/inst/V/vloxseg5ei32.v.yaml +++ b/arch/inst/V/vloxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei64.v.yaml b/arch/inst/V/vloxseg5ei64.v.yaml index dbd68647c..4a1e73e51 100644 --- a/arch/inst/V/vloxseg5ei64.v.yaml +++ b/arch/inst/V/vloxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei8.v.yaml b/arch/inst/V/vloxseg5ei8.v.yaml index c7014818a..df2afc27a 100644 --- a/arch/inst/V/vloxseg5ei8.v.yaml +++ b/arch/inst/V/vloxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei16.v.yaml b/arch/inst/V/vloxseg6ei16.v.yaml index 1657012d3..f7b0fbdcc 100644 --- a/arch/inst/V/vloxseg6ei16.v.yaml +++ b/arch/inst/V/vloxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei32.v.yaml b/arch/inst/V/vloxseg6ei32.v.yaml index c6ac3fc24..a42e7f335 100644 --- a/arch/inst/V/vloxseg6ei32.v.yaml +++ b/arch/inst/V/vloxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei64.v.yaml b/arch/inst/V/vloxseg6ei64.v.yaml index 2c0fc1603..24c9a89a1 100644 --- a/arch/inst/V/vloxseg6ei64.v.yaml +++ b/arch/inst/V/vloxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei8.v.yaml b/arch/inst/V/vloxseg6ei8.v.yaml index 5685617fa..af5bc5faa 100644 --- a/arch/inst/V/vloxseg6ei8.v.yaml +++ b/arch/inst/V/vloxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei16.v.yaml b/arch/inst/V/vloxseg7ei16.v.yaml index d250dad20..9f113daec 100644 --- a/arch/inst/V/vloxseg7ei16.v.yaml +++ b/arch/inst/V/vloxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei32.v.yaml b/arch/inst/V/vloxseg7ei32.v.yaml index 5013d140a..dc92014b1 100644 --- a/arch/inst/V/vloxseg7ei32.v.yaml +++ b/arch/inst/V/vloxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei64.v.yaml b/arch/inst/V/vloxseg7ei64.v.yaml index 7fe0ced84..0efc0ce4e 100644 --- a/arch/inst/V/vloxseg7ei64.v.yaml +++ b/arch/inst/V/vloxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei8.v.yaml b/arch/inst/V/vloxseg7ei8.v.yaml index e1c2ead11..a87175475 100644 --- a/arch/inst/V/vloxseg7ei8.v.yaml +++ b/arch/inst/V/vloxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei16.v.yaml b/arch/inst/V/vloxseg8ei16.v.yaml index df6f5db25..820eb7d13 100644 --- a/arch/inst/V/vloxseg8ei16.v.yaml +++ b/arch/inst/V/vloxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei32.v.yaml b/arch/inst/V/vloxseg8ei32.v.yaml index 195c6ea1a..9d733a3e2 100644 --- a/arch/inst/V/vloxseg8ei32.v.yaml +++ b/arch/inst/V/vloxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei64.v.yaml b/arch/inst/V/vloxseg8ei64.v.yaml index f2747cd5b..ff37314bf 100644 --- a/arch/inst/V/vloxseg8ei64.v.yaml +++ b/arch/inst/V/vloxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei8.v.yaml b/arch/inst/V/vloxseg8ei8.v.yaml index f0d5ec5f7..689a55354 100644 --- a/arch/inst/V/vloxseg8ei8.v.yaml +++ b/arch/inst/V/vloxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlse16.v.yaml b/arch/inst/V/vlse16.v.yaml index c5a7f1aa7..f82b34253 100644 --- a/arch/inst/V/vlse16.v.yaml +++ b/arch/inst/V/vlse16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse32.v.yaml b/arch/inst/V/vlse32.v.yaml index 01849349b..6ba2a8abe 100644 --- a/arch/inst/V/vlse32.v.yaml +++ b/arch/inst/V/vlse32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse64.v.yaml b/arch/inst/V/vlse64.v.yaml index d24b18466..76e1be064 100644 --- a/arch/inst/V/vlse64.v.yaml +++ b/arch/inst/V/vlse64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse8.v.yaml b/arch/inst/V/vlse8.v.yaml index bf7896550..ad57806cf 100644 --- a/arch/inst/V/vlse8.v.yaml +++ b/arch/inst/V/vlse8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlseg2e16.v.yaml b/arch/inst/V/vlseg2e16.v.yaml index a2cab4bab..fb571d744 100644 --- a/arch/inst/V/vlseg2e16.v.yaml +++ b/arch/inst/V/vlseg2e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e16ff.v.yaml b/arch/inst/V/vlseg2e16ff.v.yaml index a4014b189..0bcfe9e14 100644 --- a/arch/inst/V/vlseg2e16ff.v.yaml +++ b/arch/inst/V/vlseg2e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e32.v.yaml b/arch/inst/V/vlseg2e32.v.yaml index e5d3ae3c0..d81a1047e 100644 --- a/arch/inst/V/vlseg2e32.v.yaml +++ b/arch/inst/V/vlseg2e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e32ff.v.yaml b/arch/inst/V/vlseg2e32ff.v.yaml index 815814027..d1a6348b5 100644 --- a/arch/inst/V/vlseg2e32ff.v.yaml +++ b/arch/inst/V/vlseg2e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e64.v.yaml b/arch/inst/V/vlseg2e64.v.yaml index bfacab114..2c93a9442 100644 --- a/arch/inst/V/vlseg2e64.v.yaml +++ b/arch/inst/V/vlseg2e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e64ff.v.yaml b/arch/inst/V/vlseg2e64ff.v.yaml index ed5c70bbe..ca5ad1b9d 100644 --- a/arch/inst/V/vlseg2e64ff.v.yaml +++ b/arch/inst/V/vlseg2e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e8.v.yaml b/arch/inst/V/vlseg2e8.v.yaml index 734ecbca9..9d80b185b 100644 --- a/arch/inst/V/vlseg2e8.v.yaml +++ b/arch/inst/V/vlseg2e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e8ff.v.yaml b/arch/inst/V/vlseg2e8ff.v.yaml index 848b4e8f7..427db8eae 100644 --- a/arch/inst/V/vlseg2e8ff.v.yaml +++ b/arch/inst/V/vlseg2e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e16.v.yaml b/arch/inst/V/vlseg3e16.v.yaml index 0a8c6870a..f5d7e5545 100644 --- a/arch/inst/V/vlseg3e16.v.yaml +++ b/arch/inst/V/vlseg3e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e16ff.v.yaml b/arch/inst/V/vlseg3e16ff.v.yaml index 44472d70e..76d8d97c4 100644 --- a/arch/inst/V/vlseg3e16ff.v.yaml +++ b/arch/inst/V/vlseg3e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e32.v.yaml b/arch/inst/V/vlseg3e32.v.yaml index 080f21018..d982464fe 100644 --- a/arch/inst/V/vlseg3e32.v.yaml +++ b/arch/inst/V/vlseg3e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e32ff.v.yaml b/arch/inst/V/vlseg3e32ff.v.yaml index 08bc7cb9d..1634338f1 100644 --- a/arch/inst/V/vlseg3e32ff.v.yaml +++ b/arch/inst/V/vlseg3e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e64.v.yaml b/arch/inst/V/vlseg3e64.v.yaml index a73c8cab7..4de2fb503 100644 --- a/arch/inst/V/vlseg3e64.v.yaml +++ b/arch/inst/V/vlseg3e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e64ff.v.yaml b/arch/inst/V/vlseg3e64ff.v.yaml index f6a23acb4..0f73b786a 100644 --- a/arch/inst/V/vlseg3e64ff.v.yaml +++ b/arch/inst/V/vlseg3e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e8.v.yaml b/arch/inst/V/vlseg3e8.v.yaml index 4679966e0..f858ec9c7 100644 --- a/arch/inst/V/vlseg3e8.v.yaml +++ b/arch/inst/V/vlseg3e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e8ff.v.yaml b/arch/inst/V/vlseg3e8ff.v.yaml index 0474c4bb9..aeed7424b 100644 --- a/arch/inst/V/vlseg3e8ff.v.yaml +++ b/arch/inst/V/vlseg3e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e16.v.yaml b/arch/inst/V/vlseg4e16.v.yaml index ad493e689..e017e0983 100644 --- a/arch/inst/V/vlseg4e16.v.yaml +++ b/arch/inst/V/vlseg4e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e16ff.v.yaml b/arch/inst/V/vlseg4e16ff.v.yaml index 31acfb5a8..3144cc777 100644 --- a/arch/inst/V/vlseg4e16ff.v.yaml +++ b/arch/inst/V/vlseg4e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e32.v.yaml b/arch/inst/V/vlseg4e32.v.yaml index ac08fa060..eaf5e45e9 100644 --- a/arch/inst/V/vlseg4e32.v.yaml +++ b/arch/inst/V/vlseg4e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e32ff.v.yaml b/arch/inst/V/vlseg4e32ff.v.yaml index 03a02f42e..fc92eeb66 100644 --- a/arch/inst/V/vlseg4e32ff.v.yaml +++ b/arch/inst/V/vlseg4e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e64.v.yaml b/arch/inst/V/vlseg4e64.v.yaml index 8915697f5..e7630b5e6 100644 --- a/arch/inst/V/vlseg4e64.v.yaml +++ b/arch/inst/V/vlseg4e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e64ff.v.yaml b/arch/inst/V/vlseg4e64ff.v.yaml index 8190586ee..b64e45fa2 100644 --- a/arch/inst/V/vlseg4e64ff.v.yaml +++ b/arch/inst/V/vlseg4e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e8.v.yaml b/arch/inst/V/vlseg4e8.v.yaml index 91c8f4b8a..471bcc07d 100644 --- a/arch/inst/V/vlseg4e8.v.yaml +++ b/arch/inst/V/vlseg4e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e8ff.v.yaml b/arch/inst/V/vlseg4e8ff.v.yaml index df6e6831e..67165fa3d 100644 --- a/arch/inst/V/vlseg4e8ff.v.yaml +++ b/arch/inst/V/vlseg4e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e16.v.yaml b/arch/inst/V/vlseg5e16.v.yaml index 30f713959..9ba626b4a 100644 --- a/arch/inst/V/vlseg5e16.v.yaml +++ b/arch/inst/V/vlseg5e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e16ff.v.yaml b/arch/inst/V/vlseg5e16ff.v.yaml index 15c3a245a..2f1eaa609 100644 --- a/arch/inst/V/vlseg5e16ff.v.yaml +++ b/arch/inst/V/vlseg5e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e32.v.yaml b/arch/inst/V/vlseg5e32.v.yaml index 13966d00b..eb45144de 100644 --- a/arch/inst/V/vlseg5e32.v.yaml +++ b/arch/inst/V/vlseg5e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e32ff.v.yaml b/arch/inst/V/vlseg5e32ff.v.yaml index 5bae35876..e0cc52c87 100644 --- a/arch/inst/V/vlseg5e32ff.v.yaml +++ b/arch/inst/V/vlseg5e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e64.v.yaml b/arch/inst/V/vlseg5e64.v.yaml index d87028734..e989cc4a4 100644 --- a/arch/inst/V/vlseg5e64.v.yaml +++ b/arch/inst/V/vlseg5e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e64ff.v.yaml b/arch/inst/V/vlseg5e64ff.v.yaml index 7be6eb177..06440b792 100644 --- a/arch/inst/V/vlseg5e64ff.v.yaml +++ b/arch/inst/V/vlseg5e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e8.v.yaml b/arch/inst/V/vlseg5e8.v.yaml index b0ed00bd0..e853590c0 100644 --- a/arch/inst/V/vlseg5e8.v.yaml +++ b/arch/inst/V/vlseg5e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e8ff.v.yaml b/arch/inst/V/vlseg5e8ff.v.yaml index 80e2df81a..e77ecaefe 100644 --- a/arch/inst/V/vlseg5e8ff.v.yaml +++ b/arch/inst/V/vlseg5e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e16.v.yaml b/arch/inst/V/vlseg6e16.v.yaml index 0c051a999..8f546c7db 100644 --- a/arch/inst/V/vlseg6e16.v.yaml +++ b/arch/inst/V/vlseg6e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e16ff.v.yaml b/arch/inst/V/vlseg6e16ff.v.yaml index 54cc9196b..352ed9489 100644 --- a/arch/inst/V/vlseg6e16ff.v.yaml +++ b/arch/inst/V/vlseg6e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e32.v.yaml b/arch/inst/V/vlseg6e32.v.yaml index 888a5c837..3ec853fd6 100644 --- a/arch/inst/V/vlseg6e32.v.yaml +++ b/arch/inst/V/vlseg6e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e32ff.v.yaml b/arch/inst/V/vlseg6e32ff.v.yaml index a0637baed..e6ee66553 100644 --- a/arch/inst/V/vlseg6e32ff.v.yaml +++ b/arch/inst/V/vlseg6e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e64.v.yaml b/arch/inst/V/vlseg6e64.v.yaml index 602d9974a..d281c07ea 100644 --- a/arch/inst/V/vlseg6e64.v.yaml +++ b/arch/inst/V/vlseg6e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e64ff.v.yaml b/arch/inst/V/vlseg6e64ff.v.yaml index f2629c19e..64bccae0b 100644 --- a/arch/inst/V/vlseg6e64ff.v.yaml +++ b/arch/inst/V/vlseg6e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e8.v.yaml b/arch/inst/V/vlseg6e8.v.yaml index a0180b971..6205f7654 100644 --- a/arch/inst/V/vlseg6e8.v.yaml +++ b/arch/inst/V/vlseg6e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e8ff.v.yaml b/arch/inst/V/vlseg6e8ff.v.yaml index b56808326..96772b71f 100644 --- a/arch/inst/V/vlseg6e8ff.v.yaml +++ b/arch/inst/V/vlseg6e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e16.v.yaml b/arch/inst/V/vlseg7e16.v.yaml index 5851806e6..80608625b 100644 --- a/arch/inst/V/vlseg7e16.v.yaml +++ b/arch/inst/V/vlseg7e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e16ff.v.yaml b/arch/inst/V/vlseg7e16ff.v.yaml index 20954ba6c..ad5a0c8e7 100644 --- a/arch/inst/V/vlseg7e16ff.v.yaml +++ b/arch/inst/V/vlseg7e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e32.v.yaml b/arch/inst/V/vlseg7e32.v.yaml index 1cf2c3373..c03e22bd0 100644 --- a/arch/inst/V/vlseg7e32.v.yaml +++ b/arch/inst/V/vlseg7e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e32ff.v.yaml b/arch/inst/V/vlseg7e32ff.v.yaml index e395b063e..502219914 100644 --- a/arch/inst/V/vlseg7e32ff.v.yaml +++ b/arch/inst/V/vlseg7e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e64.v.yaml b/arch/inst/V/vlseg7e64.v.yaml index 05e162830..9198968c5 100644 --- a/arch/inst/V/vlseg7e64.v.yaml +++ b/arch/inst/V/vlseg7e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e64ff.v.yaml b/arch/inst/V/vlseg7e64ff.v.yaml index 565aacb90..f19ae2b3d 100644 --- a/arch/inst/V/vlseg7e64ff.v.yaml +++ b/arch/inst/V/vlseg7e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e8.v.yaml b/arch/inst/V/vlseg7e8.v.yaml index 21de27f84..8d5b00522 100644 --- a/arch/inst/V/vlseg7e8.v.yaml +++ b/arch/inst/V/vlseg7e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e8ff.v.yaml b/arch/inst/V/vlseg7e8ff.v.yaml index 8eec8031c..6b70df5dd 100644 --- a/arch/inst/V/vlseg7e8ff.v.yaml +++ b/arch/inst/V/vlseg7e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e16.v.yaml b/arch/inst/V/vlseg8e16.v.yaml index ec175bb37..123b19b57 100644 --- a/arch/inst/V/vlseg8e16.v.yaml +++ b/arch/inst/V/vlseg8e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e16ff.v.yaml b/arch/inst/V/vlseg8e16ff.v.yaml index 7a99d2402..638b68a82 100644 --- a/arch/inst/V/vlseg8e16ff.v.yaml +++ b/arch/inst/V/vlseg8e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e32.v.yaml b/arch/inst/V/vlseg8e32.v.yaml index 79372ae84..39b89cdad 100644 --- a/arch/inst/V/vlseg8e32.v.yaml +++ b/arch/inst/V/vlseg8e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e32ff.v.yaml b/arch/inst/V/vlseg8e32ff.v.yaml index 9bd0906b5..a2ab52d77 100644 --- a/arch/inst/V/vlseg8e32ff.v.yaml +++ b/arch/inst/V/vlseg8e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e64.v.yaml b/arch/inst/V/vlseg8e64.v.yaml index ed5befa23..f7952833b 100644 --- a/arch/inst/V/vlseg8e64.v.yaml +++ b/arch/inst/V/vlseg8e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e64ff.v.yaml b/arch/inst/V/vlseg8e64ff.v.yaml index af4e15d51..28c0e9a73 100644 --- a/arch/inst/V/vlseg8e64ff.v.yaml +++ b/arch/inst/V/vlseg8e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e8.v.yaml b/arch/inst/V/vlseg8e8.v.yaml index e1937c9ac..7b1c864ae 100644 --- a/arch/inst/V/vlseg8e8.v.yaml +++ b/arch/inst/V/vlseg8e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e8ff.v.yaml b/arch/inst/V/vlseg8e8ff.v.yaml index cb825c00e..503786f11 100644 --- a/arch/inst/V/vlseg8e8ff.v.yaml +++ b/arch/inst/V/vlseg8e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e16.v.yaml b/arch/inst/V/vlsseg2e16.v.yaml index 691eb363b..a8700b96d 100644 --- a/arch/inst/V/vlsseg2e16.v.yaml +++ b/arch/inst/V/vlsseg2e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e32.v.yaml b/arch/inst/V/vlsseg2e32.v.yaml index 8f89e7887..06df364b8 100644 --- a/arch/inst/V/vlsseg2e32.v.yaml +++ b/arch/inst/V/vlsseg2e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e64.v.yaml b/arch/inst/V/vlsseg2e64.v.yaml index fdce27802..ad42e35e3 100644 --- a/arch/inst/V/vlsseg2e64.v.yaml +++ b/arch/inst/V/vlsseg2e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e8.v.yaml b/arch/inst/V/vlsseg2e8.v.yaml index 7edea0e2a..f5d11dfac 100644 --- a/arch/inst/V/vlsseg2e8.v.yaml +++ b/arch/inst/V/vlsseg2e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e16.v.yaml b/arch/inst/V/vlsseg3e16.v.yaml index 7f381ef3b..e56df9143 100644 --- a/arch/inst/V/vlsseg3e16.v.yaml +++ b/arch/inst/V/vlsseg3e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e32.v.yaml b/arch/inst/V/vlsseg3e32.v.yaml index ecb434806..836a5cccc 100644 --- a/arch/inst/V/vlsseg3e32.v.yaml +++ b/arch/inst/V/vlsseg3e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e64.v.yaml b/arch/inst/V/vlsseg3e64.v.yaml index 94d3ad2f3..0fbc2ece1 100644 --- a/arch/inst/V/vlsseg3e64.v.yaml +++ b/arch/inst/V/vlsseg3e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e8.v.yaml b/arch/inst/V/vlsseg3e8.v.yaml index e9569dba2..d9f270297 100644 --- a/arch/inst/V/vlsseg3e8.v.yaml +++ b/arch/inst/V/vlsseg3e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e16.v.yaml b/arch/inst/V/vlsseg4e16.v.yaml index 3bb9ee4a7..2946801a2 100644 --- a/arch/inst/V/vlsseg4e16.v.yaml +++ b/arch/inst/V/vlsseg4e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e32.v.yaml b/arch/inst/V/vlsseg4e32.v.yaml index e63f5c9e2..f9e9adb8e 100644 --- a/arch/inst/V/vlsseg4e32.v.yaml +++ b/arch/inst/V/vlsseg4e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e64.v.yaml b/arch/inst/V/vlsseg4e64.v.yaml index 66f4af48a..7091310b9 100644 --- a/arch/inst/V/vlsseg4e64.v.yaml +++ b/arch/inst/V/vlsseg4e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e8.v.yaml b/arch/inst/V/vlsseg4e8.v.yaml index 6e213656e..e7755782f 100644 --- a/arch/inst/V/vlsseg4e8.v.yaml +++ b/arch/inst/V/vlsseg4e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e16.v.yaml b/arch/inst/V/vlsseg5e16.v.yaml index 9276507db..d96600999 100644 --- a/arch/inst/V/vlsseg5e16.v.yaml +++ b/arch/inst/V/vlsseg5e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e32.v.yaml b/arch/inst/V/vlsseg5e32.v.yaml index 2b41e5682..36dcfda26 100644 --- a/arch/inst/V/vlsseg5e32.v.yaml +++ b/arch/inst/V/vlsseg5e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e64.v.yaml b/arch/inst/V/vlsseg5e64.v.yaml index de46f05e9..43ef731d9 100644 --- a/arch/inst/V/vlsseg5e64.v.yaml +++ b/arch/inst/V/vlsseg5e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e8.v.yaml b/arch/inst/V/vlsseg5e8.v.yaml index c69373c6b..512237dfc 100644 --- a/arch/inst/V/vlsseg5e8.v.yaml +++ b/arch/inst/V/vlsseg5e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e16.v.yaml b/arch/inst/V/vlsseg6e16.v.yaml index f3773952c..fda481b60 100644 --- a/arch/inst/V/vlsseg6e16.v.yaml +++ b/arch/inst/V/vlsseg6e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e32.v.yaml b/arch/inst/V/vlsseg6e32.v.yaml index b610b0ff5..3e4927eb4 100644 --- a/arch/inst/V/vlsseg6e32.v.yaml +++ b/arch/inst/V/vlsseg6e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e64.v.yaml b/arch/inst/V/vlsseg6e64.v.yaml index 2db70cc53..379f481bb 100644 --- a/arch/inst/V/vlsseg6e64.v.yaml +++ b/arch/inst/V/vlsseg6e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e8.v.yaml b/arch/inst/V/vlsseg6e8.v.yaml index 0b849f331..16080240a 100644 --- a/arch/inst/V/vlsseg6e8.v.yaml +++ b/arch/inst/V/vlsseg6e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e16.v.yaml b/arch/inst/V/vlsseg7e16.v.yaml index ced663fe5..464b1013d 100644 --- a/arch/inst/V/vlsseg7e16.v.yaml +++ b/arch/inst/V/vlsseg7e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e32.v.yaml b/arch/inst/V/vlsseg7e32.v.yaml index 3b8367b12..990fcab16 100644 --- a/arch/inst/V/vlsseg7e32.v.yaml +++ b/arch/inst/V/vlsseg7e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e64.v.yaml b/arch/inst/V/vlsseg7e64.v.yaml index 658ed6a20..7dc4459c3 100644 --- a/arch/inst/V/vlsseg7e64.v.yaml +++ b/arch/inst/V/vlsseg7e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e8.v.yaml b/arch/inst/V/vlsseg7e8.v.yaml index 1884be49c..de905eaf9 100644 --- a/arch/inst/V/vlsseg7e8.v.yaml +++ b/arch/inst/V/vlsseg7e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e16.v.yaml b/arch/inst/V/vlsseg8e16.v.yaml index 3f9c32777..d563b2387 100644 --- a/arch/inst/V/vlsseg8e16.v.yaml +++ b/arch/inst/V/vlsseg8e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e32.v.yaml b/arch/inst/V/vlsseg8e32.v.yaml index 895b19938..a37c82d99 100644 --- a/arch/inst/V/vlsseg8e32.v.yaml +++ b/arch/inst/V/vlsseg8e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e64.v.yaml b/arch/inst/V/vlsseg8e64.v.yaml index 74fbb37b1..c9a6e417c 100644 --- a/arch/inst/V/vlsseg8e64.v.yaml +++ b/arch/inst/V/vlsseg8e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e8.v.yaml b/arch/inst/V/vlsseg8e8.v.yaml index a04abb0a9..71d8ed23d 100644 --- a/arch/inst/V/vlsseg8e8.v.yaml +++ b/arch/inst/V/vlsseg8e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxei16.v.yaml b/arch/inst/V/vluxei16.v.yaml index 2d4405c37..69010d3ea 100644 --- a/arch/inst/V/vluxei16.v.yaml +++ b/arch/inst/V/vluxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei32.v.yaml b/arch/inst/V/vluxei32.v.yaml index 617abc17c..eee624fab 100644 --- a/arch/inst/V/vluxei32.v.yaml +++ b/arch/inst/V/vluxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei64.v.yaml b/arch/inst/V/vluxei64.v.yaml index 6889bc85c..3429c2c32 100644 --- a/arch/inst/V/vluxei64.v.yaml +++ b/arch/inst/V/vluxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei8.v.yaml b/arch/inst/V/vluxei8.v.yaml index 7d9422a60..64cffe056 100644 --- a/arch/inst/V/vluxei8.v.yaml +++ b/arch/inst/V/vluxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxseg2ei16.v.yaml b/arch/inst/V/vluxseg2ei16.v.yaml index 0cedd4919..fa80ccdc7 100644 --- a/arch/inst/V/vluxseg2ei16.v.yaml +++ b/arch/inst/V/vluxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei32.v.yaml b/arch/inst/V/vluxseg2ei32.v.yaml index 248a6014d..9d5656f6e 100644 --- a/arch/inst/V/vluxseg2ei32.v.yaml +++ b/arch/inst/V/vluxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei64.v.yaml b/arch/inst/V/vluxseg2ei64.v.yaml index aa44de53f..38996c623 100644 --- a/arch/inst/V/vluxseg2ei64.v.yaml +++ b/arch/inst/V/vluxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei8.v.yaml b/arch/inst/V/vluxseg2ei8.v.yaml index 47d086f24..6c714e570 100644 --- a/arch/inst/V/vluxseg2ei8.v.yaml +++ b/arch/inst/V/vluxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei16.v.yaml b/arch/inst/V/vluxseg3ei16.v.yaml index 63ead2f0b..5d4ba029c 100644 --- a/arch/inst/V/vluxseg3ei16.v.yaml +++ b/arch/inst/V/vluxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei32.v.yaml b/arch/inst/V/vluxseg3ei32.v.yaml index 093273266..6a4ecd498 100644 --- a/arch/inst/V/vluxseg3ei32.v.yaml +++ b/arch/inst/V/vluxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei64.v.yaml b/arch/inst/V/vluxseg3ei64.v.yaml index b5b036c66..dad4d516e 100644 --- a/arch/inst/V/vluxseg3ei64.v.yaml +++ b/arch/inst/V/vluxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei8.v.yaml b/arch/inst/V/vluxseg3ei8.v.yaml index d12058ae9..e162ada5c 100644 --- a/arch/inst/V/vluxseg3ei8.v.yaml +++ b/arch/inst/V/vluxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei16.v.yaml b/arch/inst/V/vluxseg4ei16.v.yaml index 868d2bbe2..e6e85799f 100644 --- a/arch/inst/V/vluxseg4ei16.v.yaml +++ b/arch/inst/V/vluxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei32.v.yaml b/arch/inst/V/vluxseg4ei32.v.yaml index ebcbe075b..16bfdda26 100644 --- a/arch/inst/V/vluxseg4ei32.v.yaml +++ b/arch/inst/V/vluxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei64.v.yaml b/arch/inst/V/vluxseg4ei64.v.yaml index 91c3d60c5..65de58e16 100644 --- a/arch/inst/V/vluxseg4ei64.v.yaml +++ b/arch/inst/V/vluxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei8.v.yaml b/arch/inst/V/vluxseg4ei8.v.yaml index fe4afd3e9..d0ab23954 100644 --- a/arch/inst/V/vluxseg4ei8.v.yaml +++ b/arch/inst/V/vluxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei16.v.yaml b/arch/inst/V/vluxseg5ei16.v.yaml index 4a8948b02..cb8c43f71 100644 --- a/arch/inst/V/vluxseg5ei16.v.yaml +++ b/arch/inst/V/vluxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei32.v.yaml b/arch/inst/V/vluxseg5ei32.v.yaml index c061b297a..3bf89d6af 100644 --- a/arch/inst/V/vluxseg5ei32.v.yaml +++ b/arch/inst/V/vluxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei64.v.yaml b/arch/inst/V/vluxseg5ei64.v.yaml index 6cc02268a..ddb29d4bb 100644 --- a/arch/inst/V/vluxseg5ei64.v.yaml +++ b/arch/inst/V/vluxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei8.v.yaml b/arch/inst/V/vluxseg5ei8.v.yaml index 29c178c47..01870a1c5 100644 --- a/arch/inst/V/vluxseg5ei8.v.yaml +++ b/arch/inst/V/vluxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei16.v.yaml b/arch/inst/V/vluxseg6ei16.v.yaml index 4d652a37f..3326c77ff 100644 --- a/arch/inst/V/vluxseg6ei16.v.yaml +++ b/arch/inst/V/vluxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei32.v.yaml b/arch/inst/V/vluxseg6ei32.v.yaml index 84ba75c8d..596227162 100644 --- a/arch/inst/V/vluxseg6ei32.v.yaml +++ b/arch/inst/V/vluxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei64.v.yaml b/arch/inst/V/vluxseg6ei64.v.yaml index 69446e214..ef5b21469 100644 --- a/arch/inst/V/vluxseg6ei64.v.yaml +++ b/arch/inst/V/vluxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei8.v.yaml b/arch/inst/V/vluxseg6ei8.v.yaml index 599231bca..93db5170d 100644 --- a/arch/inst/V/vluxseg6ei8.v.yaml +++ b/arch/inst/V/vluxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei16.v.yaml b/arch/inst/V/vluxseg7ei16.v.yaml index 8bc62c8fa..0d0d1223b 100644 --- a/arch/inst/V/vluxseg7ei16.v.yaml +++ b/arch/inst/V/vluxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei32.v.yaml b/arch/inst/V/vluxseg7ei32.v.yaml index 39b46639d..09661bd0d 100644 --- a/arch/inst/V/vluxseg7ei32.v.yaml +++ b/arch/inst/V/vluxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei64.v.yaml b/arch/inst/V/vluxseg7ei64.v.yaml index 83c4e97dd..da5490090 100644 --- a/arch/inst/V/vluxseg7ei64.v.yaml +++ b/arch/inst/V/vluxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei8.v.yaml b/arch/inst/V/vluxseg7ei8.v.yaml index aebfab4e8..9bf03adc4 100644 --- a/arch/inst/V/vluxseg7ei8.v.yaml +++ b/arch/inst/V/vluxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei16.v.yaml b/arch/inst/V/vluxseg8ei16.v.yaml index 644010288..b64e783f4 100644 --- a/arch/inst/V/vluxseg8ei16.v.yaml +++ b/arch/inst/V/vluxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei32.v.yaml b/arch/inst/V/vluxseg8ei32.v.yaml index 68b490bee..5f53f3b23 100644 --- a/arch/inst/V/vluxseg8ei32.v.yaml +++ b/arch/inst/V/vluxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei64.v.yaml b/arch/inst/V/vluxseg8ei64.v.yaml index d1b1bc738..6a5eaffaa 100644 --- a/arch/inst/V/vluxseg8ei64.v.yaml +++ b/arch/inst/V/vluxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei8.v.yaml b/arch/inst/V/vluxseg8ei8.v.yaml index 2cce23a75..0775f15d8 100644 --- a/arch/inst/V/vluxseg8ei8.v.yaml +++ b/arch/inst/V/vluxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmacc.vv.yaml b/arch/inst/V/vmacc.vv.yaml index 2f962c1db..2cfaba7c9 100644 --- a/arch/inst/V/vmacc.vv.yaml +++ b/arch/inst/V/vmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmacc.vx.yaml b/arch/inst/V/vmacc.vx.yaml index 6ecc901da..eae603250 100644 --- a/arch/inst/V/vmacc.vx.yaml +++ b/arch/inst/V/vmacc.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vi.yaml b/arch/inst/V/vmadc.vi.yaml index 27249cc47..06f7081b9 100644 --- a/arch/inst/V/vmadc.vi.yaml +++ b/arch/inst/V/vmadc.vi.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -55,9 +55,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vim.yaml b/arch/inst/V/vmadc.vim.yaml index ffb08eb00..f7add6ff8 100644 --- a/arch/inst/V/vmadc.vim.yaml +++ b/arch/inst/V/vmadc.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vv.yaml b/arch/inst/V/vmadc.vv.yaml index f2dfe8614..18f0baafd 100644 --- a/arch/inst/V/vmadc.vv.yaml +++ b/arch/inst/V/vmadc.vv.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vvm.yaml b/arch/inst/V/vmadc.vvm.yaml index 5ad1bc2fe..a367b3624 100644 --- a/arch/inst/V/vmadc.vvm.yaml +++ b/arch/inst/V/vmadc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vx.yaml b/arch/inst/V/vmadc.vx.yaml index 06689d0e7..e216e96b5 100644 --- a/arch/inst/V/vmadc.vx.yaml +++ b/arch/inst/V/vmadc.vx.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vxm.yaml b/arch/inst/V/vmadc.vxm.yaml index 4f9f699ca..42be4e178 100644 --- a/arch/inst/V/vmadc.vxm.yaml +++ b/arch/inst/V/vmadc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadd.vv.yaml b/arch/inst/V/vmadd.vv.yaml index fda328eb3..d126ca055 100644 --- a/arch/inst/V/vmadd.vv.yaml +++ b/arch/inst/V/vmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadd.vx.yaml b/arch/inst/V/vmadd.vx.yaml index 5600d21f1..605641cd1 100644 --- a/arch/inst/V/vmadd.vx.yaml +++ b/arch/inst/V/vmadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmand.mm.yaml b/arch/inst/V/vmand.mm.yaml index 0897e5ad0..71b3d684b 100644 --- a/arch/inst/V/vmand.mm.yaml +++ b/arch/inst/V/vmand.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmandn.mm.yaml b/arch/inst/V/vmandn.mm.yaml index a5dd1ba9a..78e38995c 100644 --- a/arch/inst/V/vmandn.mm.yaml +++ b/arch/inst/V/vmandn.mm.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmax.vv.yaml b/arch/inst/V/vmax.vv.yaml index ed446c2ae..c3047be50 100644 --- a/arch/inst/V/vmax.vv.yaml +++ b/arch/inst/V/vmax.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmax.vx.yaml b/arch/inst/V/vmax.vx.yaml index 796bf3f12..6766e0453 100644 --- a/arch/inst/V/vmax.vx.yaml +++ b/arch/inst/V/vmax.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmaxu.vv.yaml b/arch/inst/V/vmaxu.vv.yaml index 1e3b423da..986712f51 100644 --- a/arch/inst/V/vmaxu.vv.yaml +++ b/arch/inst/V/vmaxu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmaxu.vx.yaml b/arch/inst/V/vmaxu.vx.yaml index 86af7591a..b5c164962 100644 --- a/arch/inst/V/vmaxu.vx.yaml +++ b/arch/inst/V/vmaxu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vim.yaml b/arch/inst/V/vmerge.vim.yaml index a190535f3..80a4b3b5f 100644 --- a/arch/inst/V/vmerge.vim.yaml +++ b/arch/inst/V/vmerge.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then imm_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vvm.yaml b/arch/inst/V/vmerge.vvm.yaml index 12977cc00..ad5f77d97 100644 --- a/arch/inst/V/vmerge.vvm.yaml +++ b/arch/inst/V/vmerge.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then vs1_val[i] else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vxm.yaml b/arch/inst/V/vmerge.vxm.yaml index d40cf5031..1dbddcaba 100644 --- a/arch/inst/V/vmerge.vxm.yaml +++ b/arch/inst/V/vmerge.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then rs1_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfeq.vf.yaml b/arch/inst/V/vmfeq.vf.yaml index cc637854e..3e9412057 100644 --- a/arch/inst/V/vmfeq.vf.yaml +++ b/arch/inst/V/vmfeq.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfeq.vv.yaml b/arch/inst/V/vmfeq.vv.yaml index 131d35caa..2663d6d03 100644 --- a/arch/inst/V/vmfeq.vv.yaml +++ b/arch/inst/V/vmfeq.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfge.vf.yaml b/arch/inst/V/vmfge.vf.yaml index c449201be..2e7cf5ff3 100644 --- a/arch/inst/V/vmfge.vf.yaml +++ b/arch/inst/V/vmfge.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfgt.vf.yaml b/arch/inst/V/vmfgt.vf.yaml index 3a7c121aa..13197e570 100644 --- a/arch/inst/V/vmfgt.vf.yaml +++ b/arch/inst/V/vmfgt.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfle.vf.yaml b/arch/inst/V/vmfle.vf.yaml index 405a2073a..f85b9dbf5 100644 --- a/arch/inst/V/vmfle.vf.yaml +++ b/arch/inst/V/vmfle.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfle.vv.yaml b/arch/inst/V/vmfle.vv.yaml index 7937c5547..318034f10 100644 --- a/arch/inst/V/vmfle.vv.yaml +++ b/arch/inst/V/vmfle.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmflt.vf.yaml b/arch/inst/V/vmflt.vf.yaml index 3260c4d26..77d68c838 100644 --- a/arch/inst/V/vmflt.vf.yaml +++ b/arch/inst/V/vmflt.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmflt.vv.yaml b/arch/inst/V/vmflt.vv.yaml index a89bab6ba..676841f71 100644 --- a/arch/inst/V/vmflt.vv.yaml +++ b/arch/inst/V/vmflt.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfne.vf.yaml b/arch/inst/V/vmfne.vf.yaml index f8dc41881..adf5cd410 100644 --- a/arch/inst/V/vmfne.vf.yaml +++ b/arch/inst/V/vmfne.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfne.vv.yaml b/arch/inst/V/vmfne.vv.yaml index 49052496c..a5078c955 100644 --- a/arch/inst/V/vmfne.vv.yaml +++ b/arch/inst/V/vmfne.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmin.vv.yaml b/arch/inst/V/vmin.vv.yaml index 77b5c4b75..4b5c9cad9 100644 --- a/arch/inst/V/vmin.vv.yaml +++ b/arch/inst/V/vmin.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmin.vx.yaml b/arch/inst/V/vmin.vx.yaml index 93b7149db..12be058ed 100644 --- a/arch/inst/V/vmin.vx.yaml +++ b/arch/inst/V/vmin.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vminu.vv.yaml b/arch/inst/V/vminu.vv.yaml index fb5523ec9..897d4b120 100644 --- a/arch/inst/V/vminu.vv.yaml +++ b/arch/inst/V/vminu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vminu.vx.yaml b/arch/inst/V/vminu.vx.yaml index 25835e6f8..890b56430 100644 --- a/arch/inst/V/vminu.vx.yaml +++ b/arch/inst/V/vminu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmnand.mm.yaml b/arch/inst/V/vmnand.mm.yaml index 8b81cd5e0..e32a80db4 100644 --- a/arch/inst/V/vmnand.mm.yaml +++ b/arch/inst/V/vmnand.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmnor.mm.yaml b/arch/inst/V/vmnor.mm.yaml index 6666bd9a5..e0ccff3e3 100644 --- a/arch/inst/V/vmnor.mm.yaml +++ b/arch/inst/V/vmnor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmor.mm.yaml b/arch/inst/V/vmor.mm.yaml index 4997ebe69..81e64a938 100644 --- a/arch/inst/V/vmor.mm.yaml +++ b/arch/inst/V/vmor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmorn.mm.yaml b/arch/inst/V/vmorn.mm.yaml index 2307206bb..89e53e8fe 100644 --- a/arch/inst/V/vmorn.mm.yaml +++ b/arch/inst/V/vmorn.mm.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmsbc.vv.yaml b/arch/inst/V/vmsbc.vv.yaml index b0e07e910..f7fa84ea2 100644 --- a/arch/inst/V/vmsbc.vv.yaml +++ b/arch/inst/V/vmsbc.vv.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vvm.yaml b/arch/inst/V/vmsbc.vvm.yaml index af3db9f4f..c4837da15 100644 --- a/arch/inst/V/vmsbc.vvm.yaml +++ b/arch/inst/V/vmsbc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vx.yaml b/arch/inst/V/vmsbc.vx.yaml index 3179ccd99..2caf127ca 100644 --- a/arch/inst/V/vmsbc.vx.yaml +++ b/arch/inst/V/vmsbc.vx.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vxm.yaml b/arch/inst/V/vmsbc.vxm.yaml index 2e54d64e2..f0865388b 100644 --- a/arch/inst/V/vmsbc.vxm.yaml +++ b/arch/inst/V/vmsbc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbf.m.yaml b/arch/inst/V/vmsbf.m.yaml index bfc1ab0a3..fe85db16a 100644 --- a/arch/inst/V/vmsbf.m.yaml +++ b/arch/inst/V/vmsbf.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | result[i] = if found_elem then false else true } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vi.yaml b/arch/inst/V/vmseq.vi.yaml index 1111623e5..fc52fa6a6 100644 --- a/arch/inst/V/vmseq.vi.yaml +++ b/arch/inst/V/vmseq.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vv.yaml b/arch/inst/V/vmseq.vv.yaml index 288533e63..cfb1bb786 100644 --- a/arch/inst/V/vmseq.vv.yaml +++ b/arch/inst/V/vmseq.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vx.yaml b/arch/inst/V/vmseq.vx.yaml index 3353ae1f3..55003e0e7 100644 --- a/arch/inst/V/vmseq.vx.yaml +++ b/arch/inst/V/vmseq.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgt.vi.yaml b/arch/inst/V/vmsgt.vi.yaml index 20db0adf9..946b787fb 100644 --- a/arch/inst/V/vmsgt.vi.yaml +++ b/arch/inst/V/vmsgt.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgt.vx.yaml b/arch/inst/V/vmsgt.vx.yaml index b7829e81d..fd878324b 100644 --- a/arch/inst/V/vmsgt.vx.yaml +++ b/arch/inst/V/vmsgt.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgtu.vi.yaml b/arch/inst/V/vmsgtu.vi.yaml index 281acc772..9119f759c 100644 --- a/arch/inst/V/vmsgtu.vi.yaml +++ b/arch/inst/V/vmsgtu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgtu.vx.yaml b/arch/inst/V/vmsgtu.vx.yaml index 2ea8494fb..5943925ef 100644 --- a/arch/inst/V/vmsgtu.vx.yaml +++ b/arch/inst/V/vmsgtu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsif.m.yaml b/arch/inst/V/vmsif.m.yaml index 9b04f46a4..008210658 100644 --- a/arch/inst/V/vmsif.m.yaml +++ b/arch/inst/V/vmsif.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | if vs2_val[i] then found_elem = true } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vi.yaml b/arch/inst/V/vmsle.vi.yaml index 2f0fa5a9b..a7d5d7367 100644 --- a/arch/inst/V/vmsle.vi.yaml +++ b/arch/inst/V/vmsle.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vv.yaml b/arch/inst/V/vmsle.vv.yaml index 12003d18e..6a41afaaa 100644 --- a/arch/inst/V/vmsle.vv.yaml +++ b/arch/inst/V/vmsle.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vx.yaml b/arch/inst/V/vmsle.vx.yaml index f36e30dfe..a8474a388 100644 --- a/arch/inst/V/vmsle.vx.yaml +++ b/arch/inst/V/vmsle.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vi.yaml b/arch/inst/V/vmsleu.vi.yaml index 568e1c966..0adb60845 100644 --- a/arch/inst/V/vmsleu.vi.yaml +++ b/arch/inst/V/vmsleu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vv.yaml b/arch/inst/V/vmsleu.vv.yaml index ce1a24e96..953e32a48 100644 --- a/arch/inst/V/vmsleu.vv.yaml +++ b/arch/inst/V/vmsleu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vx.yaml b/arch/inst/V/vmsleu.vx.yaml index b97fc1f37..7a1122585 100644 --- a/arch/inst/V/vmsleu.vx.yaml +++ b/arch/inst/V/vmsleu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmslt.vv.yaml b/arch/inst/V/vmslt.vv.yaml index 20da4ac03..f275667bd 100644 --- a/arch/inst/V/vmslt.vv.yaml +++ b/arch/inst/V/vmslt.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmslt.vx.yaml b/arch/inst/V/vmslt.vx.yaml index 978a9d5e9..b44cd616b 100644 --- a/arch/inst/V/vmslt.vx.yaml +++ b/arch/inst/V/vmslt.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsltu.vv.yaml b/arch/inst/V/vmsltu.vv.yaml index 99bf21b16..7da2e1662 100644 --- a/arch/inst/V/vmsltu.vv.yaml +++ b/arch/inst/V/vmsltu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsltu.vx.yaml b/arch/inst/V/vmsltu.vx.yaml index d6edc3802..92d8ecbce 100644 --- a/arch/inst/V/vmsltu.vx.yaml +++ b/arch/inst/V/vmsltu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vi.yaml b/arch/inst/V/vmsne.vi.yaml index fb3913dd4..8f9fe39bb 100644 --- a/arch/inst/V/vmsne.vi.yaml +++ b/arch/inst/V/vmsne.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vv.yaml b/arch/inst/V/vmsne.vv.yaml index d4155d0fe..69cb50f33 100644 --- a/arch/inst/V/vmsne.vv.yaml +++ b/arch/inst/V/vmsne.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vx.yaml b/arch/inst/V/vmsne.vx.yaml index fabb8489a..0e642b27e 100644 --- a/arch/inst/V/vmsne.vx.yaml +++ b/arch/inst/V/vmsne.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsof.m.yaml b/arch/inst/V/vmsof.m.yaml index 561216b3c..6d6ff006f 100644 --- a/arch/inst/V/vmsof.m.yaml +++ b/arch/inst/V/vmsof.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -59,9 +59,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmul.vv.yaml b/arch/inst/V/vmul.vv.yaml index 6de1b16ec..7d91cd8a5 100644 --- a/arch/inst/V/vmul.vv.yaml +++ b/arch/inst/V/vmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmul.vx.yaml b/arch/inst/V/vmul.vx.yaml index f75d0e779..e05e8672d 100644 --- a/arch/inst/V/vmul.vx.yaml +++ b/arch/inst/V/vmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulh.vv.yaml b/arch/inst/V/vmulh.vv.yaml index 43469bc27..e189c650e 100644 --- a/arch/inst/V/vmulh.vv.yaml +++ b/arch/inst/V/vmulh.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulh.vx.yaml b/arch/inst/V/vmulh.vx.yaml index 36e429154..4cf640bad 100644 --- a/arch/inst/V/vmulh.vx.yaml +++ b/arch/inst/V/vmulh.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhsu.vv.yaml b/arch/inst/V/vmulhsu.vv.yaml index 0d91b69f6..bb9a147cf 100644 --- a/arch/inst/V/vmulhsu.vv.yaml +++ b/arch/inst/V/vmulhsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhsu.vx.yaml b/arch/inst/V/vmulhsu.vx.yaml index 768b155fa..f81024ed1 100644 --- a/arch/inst/V/vmulhsu.vx.yaml +++ b/arch/inst/V/vmulhsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhu.vv.yaml b/arch/inst/V/vmulhu.vv.yaml index 8d3dc3204..a78c29831 100644 --- a/arch/inst/V/vmulhu.vv.yaml +++ b/arch/inst/V/vmulhu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhu.vx.yaml b/arch/inst/V/vmulhu.vx.yaml index baa34f7ef..1ab5613bb 100644 --- a/arch/inst/V/vmulhu.vx.yaml +++ b/arch/inst/V/vmulhu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.s.x.yaml b/arch/inst/V/vmv.s.x.yaml index bbe68c70a..2d4a35558 100644 --- a/arch/inst/V/vmv.s.x.yaml +++ b/arch/inst/V/vmv.s.x.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -30,24 +30,24 @@ sail(): | { let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(num_elem > 0); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, 'm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); - + /* one body element */ if mask[0] then result[0] = rs1_val; - + /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); foreach (i from 1 to (num_elem - 1)) { @@ -56,9 +56,8 @@ sail(): | AGNOSTIC => vd_val[i] /* TODO: configuration support */ } }; - + write_vreg(num_elem, SEW, 0, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.i.yaml b/arch/inst/V/vmv.v.i.yaml index 6a4f451d8..dee7de9ec 100644 --- a/arch/inst/V/vmv.v.i.yaml +++ b/arch/inst/V/vmv.v.i.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = imm_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.v.yaml b/arch/inst/V/vmv.v.v.yaml index 477036e39..29cdff608 100644 --- a/arch/inst/V/vmv.v.v.yaml +++ b/arch/inst/V/vmv.v.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = vs1_val[i] }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.x.yaml b/arch/inst/V/vmv.v.x.yaml index 0375fa96d..5efb079a0 100644 --- a/arch/inst/V/vmv.v.x.yaml +++ b/arch/inst/V/vmv.v.x.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, 'm); let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = rs1_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.x.s.yaml b/arch/inst/V/vmv.x.s.yaml index 0c126cbb3..40aed3db6 100644 --- a/arch/inst/V/vmv.x.s.yaml +++ b/arch/inst/V/vmv.x.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -30,19 +30,18 @@ sail(): | { let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(num_elem > 0); let 'n = num_elem; let 'm = SEW; - + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen)) else if sizeof(xlen) > SEW then sign_extend(vs2_val[0]) else vs2_val[0]; vstart = zeros(); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv1r.v.yaml b/arch/inst/V/vmv1r.v.yaml index 1a059cec6..4d3d470ed 100644 --- a/arch/inst/V/vmv1r.v.yaml +++ b/arch/inst/V/vmv1r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv2r.v.yaml b/arch/inst/V/vmv2r.v.yaml index 0c4b695e8..88b8705a1 100644 --- a/arch/inst/V/vmv2r.v.yaml +++ b/arch/inst/V/vmv2r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv4r.v.yaml b/arch/inst/V/vmv4r.v.yaml index 5da446a95..99ac5a720 100644 --- a/arch/inst/V/vmv4r.v.yaml +++ b/arch/inst/V/vmv4r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv8r.v.yaml b/arch/inst/V/vmv8r.v.yaml index 1154eb63e..66074274c 100644 --- a/arch/inst/V/vmv8r.v.yaml +++ b/arch/inst/V/vmv8r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmxnor.mm.yaml b/arch/inst/V/vmxnor.mm.yaml index 9701400e8..e4f9dbf04 100644 --- a/arch/inst/V/vmxnor.mm.yaml +++ b/arch/inst/V/vmxnor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmxor.mm.yaml b/arch/inst/V/vmxor.mm.yaml index 1f65ed0e3..ec0ea44ef 100644 --- a/arch/inst/V/vmxor.mm.yaml +++ b/arch/inst/V/vmxor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wi.yaml b/arch/inst/V/vnclip.wi.yaml index ffdc9e4dc..e231052ab 100644 --- a/arch/inst/V/vnclip.wi.yaml +++ b/arch/inst/V/vnclip.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wv.yaml b/arch/inst/V/vnclip.wv.yaml index 29112c838..faca59c93 100644 --- a/arch/inst/V/vnclip.wv.yaml +++ b/arch/inst/V/vnclip.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wx.yaml b/arch/inst/V/vnclip.wx.yaml index adf57842d..ee879075e 100644 --- a/arch/inst/V/vnclip.wx.yaml +++ b/arch/inst/V/vnclip.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wi.yaml b/arch/inst/V/vnclipu.wi.yaml index 9d2789f0b..7cf326ed0 100644 --- a/arch/inst/V/vnclipu.wi.yaml +++ b/arch/inst/V/vnclipu.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wv.yaml b/arch/inst/V/vnclipu.wv.yaml index 075172d52..b4a565a40 100644 --- a/arch/inst/V/vnclipu.wv.yaml +++ b/arch/inst/V/vnclipu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wx.yaml b/arch/inst/V/vnclipu.wx.yaml index 3e102c019..af13d2fe9 100644 --- a/arch/inst/V/vnclipu.wx.yaml +++ b/arch/inst/V/vnclipu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsac.vv.yaml b/arch/inst/V/vnmsac.vv.yaml index 8489b01a0..f9426f75c 100644 --- a/arch/inst/V/vnmsac.vv.yaml +++ b/arch/inst/V/vnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsac.vx.yaml b/arch/inst/V/vnmsac.vx.yaml index dcd3e2aa2..307b1d45a 100644 --- a/arch/inst/V/vnmsac.vx.yaml +++ b/arch/inst/V/vnmsac.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsub.vv.yaml b/arch/inst/V/vnmsub.vv.yaml index 9b34de28d..23c4cfdaf 100644 --- a/arch/inst/V/vnmsub.vv.yaml +++ b/arch/inst/V/vnmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsub.vx.yaml b/arch/inst/V/vnmsub.vx.yaml index 9e1b63f0f..95270f1a9 100644 --- a/arch/inst/V/vnmsub.vx.yaml +++ b/arch/inst/V/vnmsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wi.yaml b/arch/inst/V/vnsra.wi.yaml index bc8a52603..67e6aaa0f 100644 --- a/arch/inst/V/vnsra.wi.yaml +++ b/arch/inst/V/vnsra.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wv.yaml b/arch/inst/V/vnsra.wv.yaml index 678d1b379..a9e6be115 100644 --- a/arch/inst/V/vnsra.wv.yaml +++ b/arch/inst/V/vnsra.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wx.yaml b/arch/inst/V/vnsra.wx.yaml index 61bbe59f2..f8e6b0559 100644 --- a/arch/inst/V/vnsra.wx.yaml +++ b/arch/inst/V/vnsra.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wi.yaml b/arch/inst/V/vnsrl.wi.yaml index 7ab138f44..7b35f84f1 100644 --- a/arch/inst/V/vnsrl.wi.yaml +++ b/arch/inst/V/vnsrl.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wv.yaml b/arch/inst/V/vnsrl.wv.yaml index 4629cfa96..3c8c95679 100644 --- a/arch/inst/V/vnsrl.wv.yaml +++ b/arch/inst/V/vnsrl.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wx.yaml b/arch/inst/V/vnsrl.wx.yaml index 0ece78c6d..92b3679cf 100644 --- a/arch/inst/V/vnsrl.wx.yaml +++ b/arch/inst/V/vnsrl.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vi.yaml b/arch/inst/V/vor.vi.yaml index afccdd98e..99f59df67 100644 --- a/arch/inst/V/vor.vi.yaml +++ b/arch/inst/V/vor.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vv.yaml b/arch/inst/V/vor.vv.yaml index 130894e9b..c83208473 100644 --- a/arch/inst/V/vor.vv.yaml +++ b/arch/inst/V/vor.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vx.yaml b/arch/inst/V/vor.vx.yaml index b38fe6584..9ad6b20d1 100644 --- a/arch/inst/V/vor.vx.yaml +++ b/arch/inst/V/vor.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredand.vs.yaml b/arch/inst/V/vredand.vs.yaml index fa531e5e9..135ed6bb3 100644 --- a/arch/inst/V/vredand.vs.yaml +++ b/arch/inst/V/vredand.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmax.vs.yaml b/arch/inst/V/vredmax.vs.yaml index 428f7dc53..9d1b12a38 100644 --- a/arch/inst/V/vredmax.vs.yaml +++ b/arch/inst/V/vredmax.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmaxu.vs.yaml b/arch/inst/V/vredmaxu.vs.yaml index 548ab1858..977d71dac 100644 --- a/arch/inst/V/vredmaxu.vs.yaml +++ b/arch/inst/V/vredmaxu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmin.vs.yaml b/arch/inst/V/vredmin.vs.yaml index 41ac773bc..df9b4ba46 100644 --- a/arch/inst/V/vredmin.vs.yaml +++ b/arch/inst/V/vredmin.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredminu.vs.yaml b/arch/inst/V/vredminu.vs.yaml index 64c924b88..f3ee165cb 100644 --- a/arch/inst/V/vredminu.vs.yaml +++ b/arch/inst/V/vredminu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredor.vs.yaml b/arch/inst/V/vredor.vs.yaml index 3c54847de..121bee827 100644 --- a/arch/inst/V/vredor.vs.yaml +++ b/arch/inst/V/vredor.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredsum.vs.yaml b/arch/inst/V/vredsum.vs.yaml index d254f4167..be0b41c8b 100644 --- a/arch/inst/V/vredsum.vs.yaml +++ b/arch/inst/V/vredsum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredxor.vs.yaml b/arch/inst/V/vredxor.vs.yaml index bf47cb601..b9500c5ac 100644 --- a/arch/inst/V/vredxor.vs.yaml +++ b/arch/inst/V/vredxor.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrem.vv.yaml b/arch/inst/V/vrem.vv.yaml index 175ce9362..54b445872 100644 --- a/arch/inst/V/vrem.vv.yaml +++ b/arch/inst/V/vrem.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrem.vx.yaml b/arch/inst/V/vrem.vx.yaml index d04de82d6..976f7a73b 100644 --- a/arch/inst/V/vrem.vx.yaml +++ b/arch/inst/V/vrem.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vremu.vv.yaml b/arch/inst/V/vremu.vv.yaml index e0f547263..4262b9e29 100644 --- a/arch/inst/V/vremu.vv.yaml +++ b/arch/inst/V/vremu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vremu.vx.yaml b/arch/inst/V/vremu.vx.yaml index f18797128..3709f7afc 100644 --- a/arch/inst/V/vremu.vx.yaml +++ b/arch/inst/V/vremu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vi.yaml b/arch/inst/V/vrgather.vi.yaml index cce4802a6..8f8c6f157 100644 --- a/arch/inst/V/vrgather.vi.yaml +++ b/arch/inst/V/vrgather.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vv.yaml b/arch/inst/V/vrgather.vv.yaml index 3b902476c..17c92e6d4 100644 --- a/arch/inst/V/vrgather.vv.yaml +++ b/arch/inst/V/vrgather.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vx.yaml b/arch/inst/V/vrgather.vx.yaml index fef288091..10763af3b 100644 --- a/arch/inst/V/vrgather.vx.yaml +++ b/arch/inst/V/vrgather.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgatherei16.vv.yaml b/arch/inst/V/vrgatherei16.vv.yaml index 6588d9cc9..3edfd3f2b 100644 --- a/arch/inst/V/vrgatherei16.vv.yaml +++ b/arch/inst/V/vrgatherei16.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrsub.vi.yaml b/arch/inst/V/vrsub.vi.yaml index c2e1a4fe1..5e369d5e1 100644 --- a/arch/inst/V/vrsub.vi.yaml +++ b/arch/inst/V/vrsub.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrsub.vx.yaml b/arch/inst/V/vrsub.vx.yaml index 28dc3fd33..2981fdbe0 100644 --- a/arch/inst/V/vrsub.vx.yaml +++ b/arch/inst/V/vrsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vs1r.v.yaml b/arch/inst/V/vs1r.v.yaml index 89a88c823..16af81c2f 100644 --- a/arch/inst/V/vs1r.v.yaml +++ b/arch/inst/V/vs1r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs2r.v.yaml b/arch/inst/V/vs2r.v.yaml index 1f8e6a218..ca01f05fd 100644 --- a/arch/inst/V/vs2r.v.yaml +++ b/arch/inst/V/vs2r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs4r.v.yaml b/arch/inst/V/vs4r.v.yaml index 5c2cf8bc2..a035f4cc4 100644 --- a/arch/inst/V/vs4r.v.yaml +++ b/arch/inst/V/vs4r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs8r.v.yaml b/arch/inst/V/vs8r.v.yaml index 2eb6a086e..31126a57f 100644 --- a/arch/inst/V/vs8r.v.yaml +++ b/arch/inst/V/vs8r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsadd.vi.yaml b/arch/inst/V/vsadd.vi.yaml index 0d8078033..59d37d92d 100644 --- a/arch/inst/V/vsadd.vi.yaml +++ b/arch/inst/V/vsadd.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsadd.vv.yaml b/arch/inst/V/vsadd.vv.yaml index d293482c7..6a9e51dc6 100644 --- a/arch/inst/V/vsadd.vv.yaml +++ b/arch/inst/V/vsadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsadd.vx.yaml b/arch/inst/V/vsadd.vx.yaml index cb9ae0d4d..cd4d2f1f5 100644 --- a/arch/inst/V/vsadd.vx.yaml +++ b/arch/inst/V/vsadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vi.yaml b/arch/inst/V/vsaddu.vi.yaml index 5c264d554..0aac71bce 100644 --- a/arch/inst/V/vsaddu.vi.yaml +++ b/arch/inst/V/vsaddu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vv.yaml b/arch/inst/V/vsaddu.vv.yaml index 870e4ab1c..e2514e2c7 100644 --- a/arch/inst/V/vsaddu.vv.yaml +++ b/arch/inst/V/vsaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vx.yaml b/arch/inst/V/vsaddu.vx.yaml index eb1916e2b..5cfbc7fc2 100644 --- a/arch/inst/V/vsaddu.vx.yaml +++ b/arch/inst/V/vsaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsbc.vvm.yaml b/arch/inst/V/vsbc.vvm.yaml index 0ae6c376b..646653fc5 100644 --- a/arch/inst/V/vsbc.vvm.yaml +++ b/arch/inst/V/vsbc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsbc.vxm.yaml b/arch/inst/V/vsbc.vxm.yaml index 5731aed41..f3a6fabcb 100644 --- a/arch/inst/V/vsbc.vxm.yaml +++ b/arch/inst/V/vsbc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vse16.v.yaml b/arch/inst/V/vse16.v.yaml index dfd3b2b0a..46f1bef23 100644 --- a/arch/inst/V/vse16.v.yaml +++ b/arch/inst/V/vse16.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse32.v.yaml b/arch/inst/V/vse32.v.yaml index 9e067d782..9db60760d 100644 --- a/arch/inst/V/vse32.v.yaml +++ b/arch/inst/V/vse32.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse64.v.yaml b/arch/inst/V/vse64.v.yaml index 1744b91e1..3fbfabaed 100644 --- a/arch/inst/V/vse64.v.yaml +++ b/arch/inst/V/vse64.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse8.v.yaml b/arch/inst/V/vse8.v.yaml index fd9223819..b3be72b1e 100644 --- a/arch/inst/V/vse8.v.yaml +++ b/arch/inst/V/vse8.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsetivli.yaml b/arch/inst/V/vsetivli.yaml index f8b35e0b7..623b27b24 100644 --- a/arch/inst/V/vsetivli.yaml +++ b/arch/inst/V/vsetivli.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,10 @@ sail(): | let LMUL_pow_ori = get_lmul_pow(); let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; - + /* set vtype */ vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul; - + /* check legal SEW and LMUL and calculate VLMAX */ let LMUL_pow_new = get_lmul_pow(); let SEW_pow_new = get_sew_pow(); @@ -54,7 +54,7 @@ sail(): | }; let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */ - + /* set vl according to VLMAX and AVL */ vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) @@ -65,11 +65,10 @@ sail(): | X(rd) = vl; print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); print_reg("CSR vl <- " ^ BitStr(vl)); - + /* reset vstart to 0 */ vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsetvl.yaml b/arch/inst/V/vsetvl.yaml index c7341e9da..a66a6759f 100644 --- a/arch/inst/V/vsetvl.yaml +++ b/arch/inst/V/vsetvl.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsetvli.yaml b/arch/inst/V/vsetvli.yaml index ad90125f4..93995b765 100644 --- a/arch/inst/V/vsetvli.yaml +++ b/arch/inst/V/vsetvli.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,7 +35,7 @@ sail(): | let LMUL_pow_ori = get_lmul_pow(); let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; - + /* set vtype */ match op { VSETVLI => { @@ -46,7 +46,7 @@ sail(): | vtype->bits() = X(rs2) } }; - + /* check legal SEW and LMUL and calculate VLMAX */ let LMUL_pow_new = get_lmul_pow(); let SEW_pow_new = get_sew_pow(); @@ -61,7 +61,7 @@ sail(): | return RETIRE_SUCCESS }; let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); - + /* set vl according to VLMAX and AVL */ if (rs1 != 0b00000) then { /* normal stripmining */ let rs1_val = X(rs1); @@ -90,14 +90,10 @@ sail(): | }; print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); print_reg("CSR vl <- " ^ BitStr(vl)); - + /* reset vstart to 0 */ vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); - + RETIRE_SUCCESS } - - - - diff --git a/arch/inst/V/vsext.vf2.yaml b/arch/inst/V/vsext.vf2.yaml index e62d41030..2a16a1202 100644 --- a/arch/inst/V/vsext.vf2.yaml +++ b/arch/inst/V/vsext.vf2.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_half = SEW / 2; let LMUL_pow_half = LMUL_pow - 1; - + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_half; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_half); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsext.vf4.yaml b/arch/inst/V/vsext.vf4.yaml index 93c595aae..430cd84ab 100644 --- a/arch/inst/V/vsext.vf4.yaml +++ b/arch/inst/V/vsext.vf4.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_quart = SEW / 4; let LMUL_pow_quart = LMUL_pow - 2; - + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_quart; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_quart); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsext.vf8.yaml b/arch/inst/V/vsext.vf8.yaml index 14cb8c222..4c1c171a7 100644 --- a/arch/inst/V/vsext.vf8.yaml +++ b/arch/inst/V/vsext.vf8.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_eighth = SEW / 8; let LMUL_pow_eighth = LMUL_pow - 3; - + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_eighth; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_eighth); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslide1down.vx.yaml b/arch/inst/V/vslide1down.vx.yaml index 604c111f9..fdf239d02 100644 --- a/arch/inst/V/vslide1down.vx.yaml +++ b/arch/inst/V/vslide1down.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslide1up.vx.yaml b/arch/inst/V/vslide1up.vx.yaml index 7879c052c..12201fa9d 100644 --- a/arch/inst/V/vslide1up.vx.yaml +++ b/arch/inst/V/vslide1up.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslidedown.vi.yaml b/arch/inst/V/vslidedown.vi.yaml index 2d512fef9..5253fa5aa 100644 --- a/arch/inst/V/vslidedown.vi.yaml +++ b/arch/inst/V/vslidedown.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslidedown.vx.yaml b/arch/inst/V/vslidedown.vx.yaml index 265c9b957..ed5f7b066 100644 --- a/arch/inst/V/vslidedown.vx.yaml +++ b/arch/inst/V/vslidedown.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslideup.vi.yaml b/arch/inst/V/vslideup.vi.yaml index 1f21c090c..cdda8b516 100644 --- a/arch/inst/V/vslideup.vi.yaml +++ b/arch/inst/V/vslideup.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslideup.vx.yaml b/arch/inst/V/vslideup.vx.yaml index 3e7b93e0d..4ac68fa34 100644 --- a/arch/inst/V/vslideup.vx.yaml +++ b/arch/inst/V/vslideup.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vi.yaml b/arch/inst/V/vsll.vi.yaml index 3365ef202..317629bf0 100644 --- a/arch/inst/V/vsll.vi.yaml +++ b/arch/inst/V/vsll.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vv.yaml b/arch/inst/V/vsll.vv.yaml index d3298a000..505eb734f 100644 --- a/arch/inst/V/vsll.vv.yaml +++ b/arch/inst/V/vsll.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vx.yaml b/arch/inst/V/vsll.vx.yaml index 0cd9cceb5..7f9222735 100644 --- a/arch/inst/V/vsll.vx.yaml +++ b/arch/inst/V/vsll.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsm.v.yaml b/arch/inst/V/vsm.v.yaml index 4d9ae9140..a50fe111d 100644 --- a/arch/inst/V/vsm.v.yaml +++ b/arch/inst/V/vsm.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,10 +33,9 @@ sail(): | let vl_val = unsigned(vl); let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ let num_elem = get_num_elem(EMUL_pow, EEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(evl >= 0); process_vm(vd_or_vs3, rs1, num_elem, evl, op) } - diff --git a/arch/inst/V/vsmul.vv.yaml b/arch/inst/V/vsmul.vv.yaml index f920f1bd3..33a0955db 100644 --- a/arch/inst/V/vsmul.vv.yaml +++ b/arch/inst/V/vsmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsmul.vx.yaml b/arch/inst/V/vsmul.vx.yaml index e0e1e8c37..8d76ae1ee 100644 --- a/arch/inst/V/vsmul.vx.yaml +++ b/arch/inst/V/vsmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsoxei16.v.yaml b/arch/inst/V/vsoxei16.v.yaml index afd40f9c8..ded610f65 100644 --- a/arch/inst/V/vsoxei16.v.yaml +++ b/arch/inst/V/vsoxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei32.v.yaml b/arch/inst/V/vsoxei32.v.yaml index 1c95ac6ce..c66fc7baf 100644 --- a/arch/inst/V/vsoxei32.v.yaml +++ b/arch/inst/V/vsoxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei64.v.yaml b/arch/inst/V/vsoxei64.v.yaml index d53f92437..1077b0db4 100644 --- a/arch/inst/V/vsoxei64.v.yaml +++ b/arch/inst/V/vsoxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei8.v.yaml b/arch/inst/V/vsoxei8.v.yaml index e7aca8d1a..a45891a50 100644 --- a/arch/inst/V/vsoxei8.v.yaml +++ b/arch/inst/V/vsoxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxseg2ei16.v.yaml b/arch/inst/V/vsoxseg2ei16.v.yaml index ac714ab24..e86e45ad3 100644 --- a/arch/inst/V/vsoxseg2ei16.v.yaml +++ b/arch/inst/V/vsoxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei32.v.yaml b/arch/inst/V/vsoxseg2ei32.v.yaml index 28784077e..9b45cee7a 100644 --- a/arch/inst/V/vsoxseg2ei32.v.yaml +++ b/arch/inst/V/vsoxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei64.v.yaml b/arch/inst/V/vsoxseg2ei64.v.yaml index 5ff3e3093..95f803fbf 100644 --- a/arch/inst/V/vsoxseg2ei64.v.yaml +++ b/arch/inst/V/vsoxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei8.v.yaml b/arch/inst/V/vsoxseg2ei8.v.yaml index f1e6c2b46..4234761a3 100644 --- a/arch/inst/V/vsoxseg2ei8.v.yaml +++ b/arch/inst/V/vsoxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei16.v.yaml b/arch/inst/V/vsoxseg3ei16.v.yaml index 779e5b3ff..fe32adab1 100644 --- a/arch/inst/V/vsoxseg3ei16.v.yaml +++ b/arch/inst/V/vsoxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei32.v.yaml b/arch/inst/V/vsoxseg3ei32.v.yaml index ea66ccc72..3c66f7a41 100644 --- a/arch/inst/V/vsoxseg3ei32.v.yaml +++ b/arch/inst/V/vsoxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei64.v.yaml b/arch/inst/V/vsoxseg3ei64.v.yaml index bfd680779..ca20fe8fa 100644 --- a/arch/inst/V/vsoxseg3ei64.v.yaml +++ b/arch/inst/V/vsoxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei8.v.yaml b/arch/inst/V/vsoxseg3ei8.v.yaml index f2ed7f223..4df149f00 100644 --- a/arch/inst/V/vsoxseg3ei8.v.yaml +++ b/arch/inst/V/vsoxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei16.v.yaml b/arch/inst/V/vsoxseg4ei16.v.yaml index 5621b133a..9a386ba92 100644 --- a/arch/inst/V/vsoxseg4ei16.v.yaml +++ b/arch/inst/V/vsoxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei32.v.yaml b/arch/inst/V/vsoxseg4ei32.v.yaml index 16968f060..9bf3d9447 100644 --- a/arch/inst/V/vsoxseg4ei32.v.yaml +++ b/arch/inst/V/vsoxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei64.v.yaml b/arch/inst/V/vsoxseg4ei64.v.yaml index 04f00844d..0b1d62d81 100644 --- a/arch/inst/V/vsoxseg4ei64.v.yaml +++ b/arch/inst/V/vsoxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei8.v.yaml b/arch/inst/V/vsoxseg4ei8.v.yaml index eff793012..078aa7a6c 100644 --- a/arch/inst/V/vsoxseg4ei8.v.yaml +++ b/arch/inst/V/vsoxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei16.v.yaml b/arch/inst/V/vsoxseg5ei16.v.yaml index 3b5d82c7e..182b82153 100644 --- a/arch/inst/V/vsoxseg5ei16.v.yaml +++ b/arch/inst/V/vsoxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei32.v.yaml b/arch/inst/V/vsoxseg5ei32.v.yaml index 6956fd4b8..865cd68d7 100644 --- a/arch/inst/V/vsoxseg5ei32.v.yaml +++ b/arch/inst/V/vsoxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei64.v.yaml b/arch/inst/V/vsoxseg5ei64.v.yaml index ad4248d04..ba7330e7b 100644 --- a/arch/inst/V/vsoxseg5ei64.v.yaml +++ b/arch/inst/V/vsoxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei8.v.yaml b/arch/inst/V/vsoxseg5ei8.v.yaml index d0aec1c02..85dcb2bb9 100644 --- a/arch/inst/V/vsoxseg5ei8.v.yaml +++ b/arch/inst/V/vsoxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei16.v.yaml b/arch/inst/V/vsoxseg6ei16.v.yaml index 28ee6c458..6a4630a84 100644 --- a/arch/inst/V/vsoxseg6ei16.v.yaml +++ b/arch/inst/V/vsoxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei32.v.yaml b/arch/inst/V/vsoxseg6ei32.v.yaml index c5ba2071a..1ff23a132 100644 --- a/arch/inst/V/vsoxseg6ei32.v.yaml +++ b/arch/inst/V/vsoxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei64.v.yaml b/arch/inst/V/vsoxseg6ei64.v.yaml index 0b10f9133..3ccbd6450 100644 --- a/arch/inst/V/vsoxseg6ei64.v.yaml +++ b/arch/inst/V/vsoxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei8.v.yaml b/arch/inst/V/vsoxseg6ei8.v.yaml index 17d875acc..a40cae05f 100644 --- a/arch/inst/V/vsoxseg6ei8.v.yaml +++ b/arch/inst/V/vsoxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei16.v.yaml b/arch/inst/V/vsoxseg7ei16.v.yaml index 0206c3b38..f6378ac9c 100644 --- a/arch/inst/V/vsoxseg7ei16.v.yaml +++ b/arch/inst/V/vsoxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei32.v.yaml b/arch/inst/V/vsoxseg7ei32.v.yaml index 5e338157e..3359414cd 100644 --- a/arch/inst/V/vsoxseg7ei32.v.yaml +++ b/arch/inst/V/vsoxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei64.v.yaml b/arch/inst/V/vsoxseg7ei64.v.yaml index c0e2ef20d..c92e97431 100644 --- a/arch/inst/V/vsoxseg7ei64.v.yaml +++ b/arch/inst/V/vsoxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei8.v.yaml b/arch/inst/V/vsoxseg7ei8.v.yaml index b12c9a079..8be28249c 100644 --- a/arch/inst/V/vsoxseg7ei8.v.yaml +++ b/arch/inst/V/vsoxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei16.v.yaml b/arch/inst/V/vsoxseg8ei16.v.yaml index 9dc37142d..7231e6acc 100644 --- a/arch/inst/V/vsoxseg8ei16.v.yaml +++ b/arch/inst/V/vsoxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei32.v.yaml b/arch/inst/V/vsoxseg8ei32.v.yaml index 4aa50321d..f1b306a0f 100644 --- a/arch/inst/V/vsoxseg8ei32.v.yaml +++ b/arch/inst/V/vsoxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei64.v.yaml b/arch/inst/V/vsoxseg8ei64.v.yaml index 404ff34a7..71e1e6404 100644 --- a/arch/inst/V/vsoxseg8ei64.v.yaml +++ b/arch/inst/V/vsoxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei8.v.yaml b/arch/inst/V/vsoxseg8ei8.v.yaml index e27be1e85..f2ae50725 100644 --- a/arch/inst/V/vsoxseg8ei8.v.yaml +++ b/arch/inst/V/vsoxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsra.vi.yaml b/arch/inst/V/vsra.vi.yaml index 0e2ea30cc..794126b65 100644 --- a/arch/inst/V/vsra.vi.yaml +++ b/arch/inst/V/vsra.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsra.vv.yaml b/arch/inst/V/vsra.vv.yaml index 5d2d61969..961684129 100644 --- a/arch/inst/V/vsra.vv.yaml +++ b/arch/inst/V/vsra.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsra.vx.yaml b/arch/inst/V/vsra.vx.yaml index f22bc1767..ce374fd8d 100644 --- a/arch/inst/V/vsra.vx.yaml +++ b/arch/inst/V/vsra.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vi.yaml b/arch/inst/V/vsrl.vi.yaml index 5a3bf199b..a3186c341 100644 --- a/arch/inst/V/vsrl.vi.yaml +++ b/arch/inst/V/vsrl.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vv.yaml b/arch/inst/V/vsrl.vv.yaml index b4414af0a..9ab40d644 100644 --- a/arch/inst/V/vsrl.vv.yaml +++ b/arch/inst/V/vsrl.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vx.yaml b/arch/inst/V/vsrl.vx.yaml index 18b4f1837..dc0fc032f 100644 --- a/arch/inst/V/vsrl.vx.yaml +++ b/arch/inst/V/vsrl.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsse16.v.yaml b/arch/inst/V/vsse16.v.yaml index d65aa432b..2bfe4dcd6 100644 --- a/arch/inst/V/vsse16.v.yaml +++ b/arch/inst/V/vsse16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse32.v.yaml b/arch/inst/V/vsse32.v.yaml index 782458d9b..3f543d07e 100644 --- a/arch/inst/V/vsse32.v.yaml +++ b/arch/inst/V/vsse32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse64.v.yaml b/arch/inst/V/vsse64.v.yaml index 818487762..dbfba2161 100644 --- a/arch/inst/V/vsse64.v.yaml +++ b/arch/inst/V/vsse64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse8.v.yaml b/arch/inst/V/vsse8.v.yaml index 262c0bf44..66257c58e 100644 --- a/arch/inst/V/vsse8.v.yaml +++ b/arch/inst/V/vsse8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsseg2e16.v.yaml b/arch/inst/V/vsseg2e16.v.yaml index 6fcf05567..cd4e5be9d 100644 --- a/arch/inst/V/vsseg2e16.v.yaml +++ b/arch/inst/V/vsseg2e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e32.v.yaml b/arch/inst/V/vsseg2e32.v.yaml index 857a1c32c..601e3b994 100644 --- a/arch/inst/V/vsseg2e32.v.yaml +++ b/arch/inst/V/vsseg2e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e64.v.yaml b/arch/inst/V/vsseg2e64.v.yaml index ed0d637b3..62ed3f80d 100644 --- a/arch/inst/V/vsseg2e64.v.yaml +++ b/arch/inst/V/vsseg2e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e8.v.yaml b/arch/inst/V/vsseg2e8.v.yaml index 6e6b74761..e66d94ecb 100644 --- a/arch/inst/V/vsseg2e8.v.yaml +++ b/arch/inst/V/vsseg2e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e16.v.yaml b/arch/inst/V/vsseg3e16.v.yaml index 9c6596610..ffde8ab7e 100644 --- a/arch/inst/V/vsseg3e16.v.yaml +++ b/arch/inst/V/vsseg3e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e32.v.yaml b/arch/inst/V/vsseg3e32.v.yaml index d67eeb0eb..68e204cc6 100644 --- a/arch/inst/V/vsseg3e32.v.yaml +++ b/arch/inst/V/vsseg3e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e64.v.yaml b/arch/inst/V/vsseg3e64.v.yaml index 4d0506f00..f32e623f2 100644 --- a/arch/inst/V/vsseg3e64.v.yaml +++ b/arch/inst/V/vsseg3e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e8.v.yaml b/arch/inst/V/vsseg3e8.v.yaml index b2c604e67..4816d14c4 100644 --- a/arch/inst/V/vsseg3e8.v.yaml +++ b/arch/inst/V/vsseg3e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e16.v.yaml b/arch/inst/V/vsseg4e16.v.yaml index aaa25044d..538a9b67d 100644 --- a/arch/inst/V/vsseg4e16.v.yaml +++ b/arch/inst/V/vsseg4e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e32.v.yaml b/arch/inst/V/vsseg4e32.v.yaml index b1c3ca1a9..41b149778 100644 --- a/arch/inst/V/vsseg4e32.v.yaml +++ b/arch/inst/V/vsseg4e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e64.v.yaml b/arch/inst/V/vsseg4e64.v.yaml index d15d70a4f..6203e1086 100644 --- a/arch/inst/V/vsseg4e64.v.yaml +++ b/arch/inst/V/vsseg4e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e8.v.yaml b/arch/inst/V/vsseg4e8.v.yaml index 2daa99250..2514dfdbe 100644 --- a/arch/inst/V/vsseg4e8.v.yaml +++ b/arch/inst/V/vsseg4e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e16.v.yaml b/arch/inst/V/vsseg5e16.v.yaml index cc5f8611f..100f59fbf 100644 --- a/arch/inst/V/vsseg5e16.v.yaml +++ b/arch/inst/V/vsseg5e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e32.v.yaml b/arch/inst/V/vsseg5e32.v.yaml index a9e9df1c0..ad3a2cb19 100644 --- a/arch/inst/V/vsseg5e32.v.yaml +++ b/arch/inst/V/vsseg5e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e64.v.yaml b/arch/inst/V/vsseg5e64.v.yaml index 7f43ce73e..ff071f25c 100644 --- a/arch/inst/V/vsseg5e64.v.yaml +++ b/arch/inst/V/vsseg5e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e8.v.yaml b/arch/inst/V/vsseg5e8.v.yaml index aa3a30a97..fda9c36a0 100644 --- a/arch/inst/V/vsseg5e8.v.yaml +++ b/arch/inst/V/vsseg5e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e16.v.yaml b/arch/inst/V/vsseg6e16.v.yaml index a4b52768a..4b2e5983e 100644 --- a/arch/inst/V/vsseg6e16.v.yaml +++ b/arch/inst/V/vsseg6e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e32.v.yaml b/arch/inst/V/vsseg6e32.v.yaml index c52e48bd0..1d08c1db3 100644 --- a/arch/inst/V/vsseg6e32.v.yaml +++ b/arch/inst/V/vsseg6e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e64.v.yaml b/arch/inst/V/vsseg6e64.v.yaml index 3b8da0914..a267cb199 100644 --- a/arch/inst/V/vsseg6e64.v.yaml +++ b/arch/inst/V/vsseg6e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e8.v.yaml b/arch/inst/V/vsseg6e8.v.yaml index b9ba9d472..b5e3a702d 100644 --- a/arch/inst/V/vsseg6e8.v.yaml +++ b/arch/inst/V/vsseg6e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e16.v.yaml b/arch/inst/V/vsseg7e16.v.yaml index 9c10d52f6..e0220080a 100644 --- a/arch/inst/V/vsseg7e16.v.yaml +++ b/arch/inst/V/vsseg7e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e32.v.yaml b/arch/inst/V/vsseg7e32.v.yaml index 7167a70dc..3a6a88528 100644 --- a/arch/inst/V/vsseg7e32.v.yaml +++ b/arch/inst/V/vsseg7e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e64.v.yaml b/arch/inst/V/vsseg7e64.v.yaml index 6872cf1e3..b2935f7d6 100644 --- a/arch/inst/V/vsseg7e64.v.yaml +++ b/arch/inst/V/vsseg7e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e8.v.yaml b/arch/inst/V/vsseg7e8.v.yaml index 30772c55b..1851b32c2 100644 --- a/arch/inst/V/vsseg7e8.v.yaml +++ b/arch/inst/V/vsseg7e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e16.v.yaml b/arch/inst/V/vsseg8e16.v.yaml index 84a60a143..65e45fad9 100644 --- a/arch/inst/V/vsseg8e16.v.yaml +++ b/arch/inst/V/vsseg8e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e32.v.yaml b/arch/inst/V/vsseg8e32.v.yaml index 82924389f..46bc8e9c7 100644 --- a/arch/inst/V/vsseg8e32.v.yaml +++ b/arch/inst/V/vsseg8e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e64.v.yaml b/arch/inst/V/vsseg8e64.v.yaml index 84df8f104..736480a8c 100644 --- a/arch/inst/V/vsseg8e64.v.yaml +++ b/arch/inst/V/vsseg8e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e8.v.yaml b/arch/inst/V/vsseg8e8.v.yaml index 86947bdb8..3903f33c7 100644 --- a/arch/inst/V/vsseg8e8.v.yaml +++ b/arch/inst/V/vsseg8e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssra.vi.yaml b/arch/inst/V/vssra.vi.yaml index 0c662c450..d89c9d999 100644 --- a/arch/inst/V/vssra.vi.yaml +++ b/arch/inst/V/vssra.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssra.vv.yaml b/arch/inst/V/vssra.vv.yaml index 7ff2e9f96..7b8f6aa47 100644 --- a/arch/inst/V/vssra.vv.yaml +++ b/arch/inst/V/vssra.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssra.vx.yaml b/arch/inst/V/vssra.vx.yaml index 0de7ada82..24f3e5821 100644 --- a/arch/inst/V/vssra.vx.yaml +++ b/arch/inst/V/vssra.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vi.yaml b/arch/inst/V/vssrl.vi.yaml index f95b0e46e..c763b4663 100644 --- a/arch/inst/V/vssrl.vi.yaml +++ b/arch/inst/V/vssrl.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vv.yaml b/arch/inst/V/vssrl.vv.yaml index 7ee05c89c..abc1547ff 100644 --- a/arch/inst/V/vssrl.vv.yaml +++ b/arch/inst/V/vssrl.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vx.yaml b/arch/inst/V/vssrl.vx.yaml index 34f7ea8ae..b5f8e4d92 100644 --- a/arch/inst/V/vssrl.vx.yaml +++ b/arch/inst/V/vssrl.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssseg2e16.v.yaml b/arch/inst/V/vssseg2e16.v.yaml index 3b1e6560c..66ef1a90a 100644 --- a/arch/inst/V/vssseg2e16.v.yaml +++ b/arch/inst/V/vssseg2e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e32.v.yaml b/arch/inst/V/vssseg2e32.v.yaml index 068297931..e562929f3 100644 --- a/arch/inst/V/vssseg2e32.v.yaml +++ b/arch/inst/V/vssseg2e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e64.v.yaml b/arch/inst/V/vssseg2e64.v.yaml index 17af81de8..a6914aa38 100644 --- a/arch/inst/V/vssseg2e64.v.yaml +++ b/arch/inst/V/vssseg2e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e8.v.yaml b/arch/inst/V/vssseg2e8.v.yaml index 3f0c872a9..8f70c1648 100644 --- a/arch/inst/V/vssseg2e8.v.yaml +++ b/arch/inst/V/vssseg2e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e16.v.yaml b/arch/inst/V/vssseg3e16.v.yaml index a2be5743f..94d3a0419 100644 --- a/arch/inst/V/vssseg3e16.v.yaml +++ b/arch/inst/V/vssseg3e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e32.v.yaml b/arch/inst/V/vssseg3e32.v.yaml index c23e342ee..16a6827d1 100644 --- a/arch/inst/V/vssseg3e32.v.yaml +++ b/arch/inst/V/vssseg3e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e64.v.yaml b/arch/inst/V/vssseg3e64.v.yaml index e42be34ad..2808af060 100644 --- a/arch/inst/V/vssseg3e64.v.yaml +++ b/arch/inst/V/vssseg3e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e8.v.yaml b/arch/inst/V/vssseg3e8.v.yaml index 5ba1cabdd..0a19eeefd 100644 --- a/arch/inst/V/vssseg3e8.v.yaml +++ b/arch/inst/V/vssseg3e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e16.v.yaml b/arch/inst/V/vssseg4e16.v.yaml index 2dcf2c097..01bce54cc 100644 --- a/arch/inst/V/vssseg4e16.v.yaml +++ b/arch/inst/V/vssseg4e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e32.v.yaml b/arch/inst/V/vssseg4e32.v.yaml index 9152f5384..f506f43e2 100644 --- a/arch/inst/V/vssseg4e32.v.yaml +++ b/arch/inst/V/vssseg4e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e64.v.yaml b/arch/inst/V/vssseg4e64.v.yaml index 4f109fc9a..f4206f314 100644 --- a/arch/inst/V/vssseg4e64.v.yaml +++ b/arch/inst/V/vssseg4e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e8.v.yaml b/arch/inst/V/vssseg4e8.v.yaml index 73145dbdb..ca7215e3b 100644 --- a/arch/inst/V/vssseg4e8.v.yaml +++ b/arch/inst/V/vssseg4e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e16.v.yaml b/arch/inst/V/vssseg5e16.v.yaml index e050b894f..8762c52ab 100644 --- a/arch/inst/V/vssseg5e16.v.yaml +++ b/arch/inst/V/vssseg5e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e32.v.yaml b/arch/inst/V/vssseg5e32.v.yaml index c380333f8..973965755 100644 --- a/arch/inst/V/vssseg5e32.v.yaml +++ b/arch/inst/V/vssseg5e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e64.v.yaml b/arch/inst/V/vssseg5e64.v.yaml index 9c0013b3f..043883ad7 100644 --- a/arch/inst/V/vssseg5e64.v.yaml +++ b/arch/inst/V/vssseg5e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e8.v.yaml b/arch/inst/V/vssseg5e8.v.yaml index 368b767df..2897b4d34 100644 --- a/arch/inst/V/vssseg5e8.v.yaml +++ b/arch/inst/V/vssseg5e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e16.v.yaml b/arch/inst/V/vssseg6e16.v.yaml index 88d3e887d..b28278b12 100644 --- a/arch/inst/V/vssseg6e16.v.yaml +++ b/arch/inst/V/vssseg6e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e32.v.yaml b/arch/inst/V/vssseg6e32.v.yaml index 443a44bb6..81bceee89 100644 --- a/arch/inst/V/vssseg6e32.v.yaml +++ b/arch/inst/V/vssseg6e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e64.v.yaml b/arch/inst/V/vssseg6e64.v.yaml index 316883eff..aa96b349b 100644 --- a/arch/inst/V/vssseg6e64.v.yaml +++ b/arch/inst/V/vssseg6e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e8.v.yaml b/arch/inst/V/vssseg6e8.v.yaml index 6421447d9..893688b91 100644 --- a/arch/inst/V/vssseg6e8.v.yaml +++ b/arch/inst/V/vssseg6e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e16.v.yaml b/arch/inst/V/vssseg7e16.v.yaml index 377909800..4a29f6b36 100644 --- a/arch/inst/V/vssseg7e16.v.yaml +++ b/arch/inst/V/vssseg7e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e32.v.yaml b/arch/inst/V/vssseg7e32.v.yaml index faaa0b21d..9a1c17897 100644 --- a/arch/inst/V/vssseg7e32.v.yaml +++ b/arch/inst/V/vssseg7e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e64.v.yaml b/arch/inst/V/vssseg7e64.v.yaml index 5721de1cc..682f8ed2b 100644 --- a/arch/inst/V/vssseg7e64.v.yaml +++ b/arch/inst/V/vssseg7e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e8.v.yaml b/arch/inst/V/vssseg7e8.v.yaml index 466148402..5be77062c 100644 --- a/arch/inst/V/vssseg7e8.v.yaml +++ b/arch/inst/V/vssseg7e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e16.v.yaml b/arch/inst/V/vssseg8e16.v.yaml index fe68e03f6..bd3acecbb 100644 --- a/arch/inst/V/vssseg8e16.v.yaml +++ b/arch/inst/V/vssseg8e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e32.v.yaml b/arch/inst/V/vssseg8e32.v.yaml index 41ced6eef..3e43ac8e4 100644 --- a/arch/inst/V/vssseg8e32.v.yaml +++ b/arch/inst/V/vssseg8e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e64.v.yaml b/arch/inst/V/vssseg8e64.v.yaml index 3792410a3..ce587b8a6 100644 --- a/arch/inst/V/vssseg8e64.v.yaml +++ b/arch/inst/V/vssseg8e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e8.v.yaml b/arch/inst/V/vssseg8e8.v.yaml index c938f6444..733f17a9c 100644 --- a/arch/inst/V/vssseg8e8.v.yaml +++ b/arch/inst/V/vssseg8e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssub.vv.yaml b/arch/inst/V/vssub.vv.yaml index f714c6895..fe57f480c 100644 --- a/arch/inst/V/vssub.vv.yaml +++ b/arch/inst/V/vssub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssub.vx.yaml b/arch/inst/V/vssub.vx.yaml index 2e0e0e36b..ea715dcbd 100644 --- a/arch/inst/V/vssub.vx.yaml +++ b/arch/inst/V/vssub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssubu.vv.yaml b/arch/inst/V/vssubu.vv.yaml index 9f65cded2..d74a1bbd0 100644 --- a/arch/inst/V/vssubu.vv.yaml +++ b/arch/inst/V/vssubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssubu.vx.yaml b/arch/inst/V/vssubu.vx.yaml index 81e4d6b05..b810030a6 100644 --- a/arch/inst/V/vssubu.vx.yaml +++ b/arch/inst/V/vssubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsub.vv.yaml b/arch/inst/V/vsub.vv.yaml index a257e86d5..9df0336ee 100644 --- a/arch/inst/V/vsub.vv.yaml +++ b/arch/inst/V/vsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsub.vx.yaml b/arch/inst/V/vsub.vx.yaml index 193e7408d..64b319044 100644 --- a/arch/inst/V/vsub.vx.yaml +++ b/arch/inst/V/vsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsuxei16.v.yaml b/arch/inst/V/vsuxei16.v.yaml index c9f0b5388..11de9a7e3 100644 --- a/arch/inst/V/vsuxei16.v.yaml +++ b/arch/inst/V/vsuxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei32.v.yaml b/arch/inst/V/vsuxei32.v.yaml index 07c6bc5a8..8e2587fa3 100644 --- a/arch/inst/V/vsuxei32.v.yaml +++ b/arch/inst/V/vsuxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei64.v.yaml b/arch/inst/V/vsuxei64.v.yaml index 15a59cbc4..690030d76 100644 --- a/arch/inst/V/vsuxei64.v.yaml +++ b/arch/inst/V/vsuxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei8.v.yaml b/arch/inst/V/vsuxei8.v.yaml index 717c6f4fc..26fd5fd07 100644 --- a/arch/inst/V/vsuxei8.v.yaml +++ b/arch/inst/V/vsuxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxseg2ei16.v.yaml b/arch/inst/V/vsuxseg2ei16.v.yaml index c87cde860..c6dd0cc86 100644 --- a/arch/inst/V/vsuxseg2ei16.v.yaml +++ b/arch/inst/V/vsuxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei32.v.yaml b/arch/inst/V/vsuxseg2ei32.v.yaml index 6a4aabb4d..29c958694 100644 --- a/arch/inst/V/vsuxseg2ei32.v.yaml +++ b/arch/inst/V/vsuxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei64.v.yaml b/arch/inst/V/vsuxseg2ei64.v.yaml index 5e08c3e73..1004b0400 100644 --- a/arch/inst/V/vsuxseg2ei64.v.yaml +++ b/arch/inst/V/vsuxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei8.v.yaml b/arch/inst/V/vsuxseg2ei8.v.yaml index de8bb5551..d17af839e 100644 --- a/arch/inst/V/vsuxseg2ei8.v.yaml +++ b/arch/inst/V/vsuxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei16.v.yaml b/arch/inst/V/vsuxseg3ei16.v.yaml index 160f074ea..f996907a8 100644 --- a/arch/inst/V/vsuxseg3ei16.v.yaml +++ b/arch/inst/V/vsuxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei32.v.yaml b/arch/inst/V/vsuxseg3ei32.v.yaml index 3c951c9c2..fa693dce2 100644 --- a/arch/inst/V/vsuxseg3ei32.v.yaml +++ b/arch/inst/V/vsuxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei64.v.yaml b/arch/inst/V/vsuxseg3ei64.v.yaml index 44e633dfd..9402fb997 100644 --- a/arch/inst/V/vsuxseg3ei64.v.yaml +++ b/arch/inst/V/vsuxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei8.v.yaml b/arch/inst/V/vsuxseg3ei8.v.yaml index d4131bea1..a6df38193 100644 --- a/arch/inst/V/vsuxseg3ei8.v.yaml +++ b/arch/inst/V/vsuxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei16.v.yaml b/arch/inst/V/vsuxseg4ei16.v.yaml index 5a2391424..bf4d87142 100644 --- a/arch/inst/V/vsuxseg4ei16.v.yaml +++ b/arch/inst/V/vsuxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei32.v.yaml b/arch/inst/V/vsuxseg4ei32.v.yaml index de1b0e820..c730eff6c 100644 --- a/arch/inst/V/vsuxseg4ei32.v.yaml +++ b/arch/inst/V/vsuxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei64.v.yaml b/arch/inst/V/vsuxseg4ei64.v.yaml index c1c358f12..c263a3317 100644 --- a/arch/inst/V/vsuxseg4ei64.v.yaml +++ b/arch/inst/V/vsuxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei8.v.yaml b/arch/inst/V/vsuxseg4ei8.v.yaml index a69f3e9e4..64bbffc45 100644 --- a/arch/inst/V/vsuxseg4ei8.v.yaml +++ b/arch/inst/V/vsuxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei16.v.yaml b/arch/inst/V/vsuxseg5ei16.v.yaml index d151e28a4..6b7ac97ea 100644 --- a/arch/inst/V/vsuxseg5ei16.v.yaml +++ b/arch/inst/V/vsuxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei32.v.yaml b/arch/inst/V/vsuxseg5ei32.v.yaml index 81abe68b2..a5afbb597 100644 --- a/arch/inst/V/vsuxseg5ei32.v.yaml +++ b/arch/inst/V/vsuxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei64.v.yaml b/arch/inst/V/vsuxseg5ei64.v.yaml index 266d10512..a4c7a1e50 100644 --- a/arch/inst/V/vsuxseg5ei64.v.yaml +++ b/arch/inst/V/vsuxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei8.v.yaml b/arch/inst/V/vsuxseg5ei8.v.yaml index 522b019a4..4e3fa113b 100644 --- a/arch/inst/V/vsuxseg5ei8.v.yaml +++ b/arch/inst/V/vsuxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei16.v.yaml b/arch/inst/V/vsuxseg6ei16.v.yaml index 2d29c3d2d..480cefc65 100644 --- a/arch/inst/V/vsuxseg6ei16.v.yaml +++ b/arch/inst/V/vsuxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei32.v.yaml b/arch/inst/V/vsuxseg6ei32.v.yaml index 3f52d6f71..f504d7402 100644 --- a/arch/inst/V/vsuxseg6ei32.v.yaml +++ b/arch/inst/V/vsuxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei64.v.yaml b/arch/inst/V/vsuxseg6ei64.v.yaml index 9da3f96c5..3dc2a966e 100644 --- a/arch/inst/V/vsuxseg6ei64.v.yaml +++ b/arch/inst/V/vsuxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei8.v.yaml b/arch/inst/V/vsuxseg6ei8.v.yaml index a2d74f76c..2755d986b 100644 --- a/arch/inst/V/vsuxseg6ei8.v.yaml +++ b/arch/inst/V/vsuxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei16.v.yaml b/arch/inst/V/vsuxseg7ei16.v.yaml index aaf2ae980..b741b04f4 100644 --- a/arch/inst/V/vsuxseg7ei16.v.yaml +++ b/arch/inst/V/vsuxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei32.v.yaml b/arch/inst/V/vsuxseg7ei32.v.yaml index 0aa35c109..49ae744ff 100644 --- a/arch/inst/V/vsuxseg7ei32.v.yaml +++ b/arch/inst/V/vsuxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei64.v.yaml b/arch/inst/V/vsuxseg7ei64.v.yaml index da607c1c3..eb7b21ba3 100644 --- a/arch/inst/V/vsuxseg7ei64.v.yaml +++ b/arch/inst/V/vsuxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei8.v.yaml b/arch/inst/V/vsuxseg7ei8.v.yaml index 003994175..dd52ac3d7 100644 --- a/arch/inst/V/vsuxseg7ei8.v.yaml +++ b/arch/inst/V/vsuxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei16.v.yaml b/arch/inst/V/vsuxseg8ei16.v.yaml index d9894ceb2..ed979fec2 100644 --- a/arch/inst/V/vsuxseg8ei16.v.yaml +++ b/arch/inst/V/vsuxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei32.v.yaml b/arch/inst/V/vsuxseg8ei32.v.yaml index bfbe6a963..5ac1dcab0 100644 --- a/arch/inst/V/vsuxseg8ei32.v.yaml +++ b/arch/inst/V/vsuxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei64.v.yaml b/arch/inst/V/vsuxseg8ei64.v.yaml index c7e171677..f7dc31b9e 100644 --- a/arch/inst/V/vsuxseg8ei64.v.yaml +++ b/arch/inst/V/vsuxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei8.v.yaml b/arch/inst/V/vsuxseg8ei8.v.yaml index 225b9ce8b..2099cd741 100644 --- a/arch/inst/V/vsuxseg8ei8.v.yaml +++ b/arch/inst/V/vsuxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vwadd.vv.yaml b/arch/inst/V/vwadd.vv.yaml index 3b237223e..020370730 100644 --- a/arch/inst/V/vwadd.vv.yaml +++ b/arch/inst/V/vwadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.vx.yaml b/arch/inst/V/vwadd.vx.yaml index ed7378983..010532791 100644 --- a/arch/inst/V/vwadd.vx.yaml +++ b/arch/inst/V/vwadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.wv.yaml b/arch/inst/V/vwadd.wv.yaml index 035b42755..a6a851919 100644 --- a/arch/inst/V/vwadd.wv.yaml +++ b/arch/inst/V/vwadd.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.wx.yaml b/arch/inst/V/vwadd.wx.yaml index 07a880ebe..fd78c086a 100644 --- a/arch/inst/V/vwadd.wx.yaml +++ b/arch/inst/V/vwadd.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.vv.yaml b/arch/inst/V/vwaddu.vv.yaml index e2c393361..e0e0e20ab 100644 --- a/arch/inst/V/vwaddu.vv.yaml +++ b/arch/inst/V/vwaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.vx.yaml b/arch/inst/V/vwaddu.vx.yaml index cf58098a2..87870e44e 100644 --- a/arch/inst/V/vwaddu.vx.yaml +++ b/arch/inst/V/vwaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.wv.yaml b/arch/inst/V/vwaddu.wv.yaml index 198b61f01..799fd3761 100644 --- a/arch/inst/V/vwaddu.wv.yaml +++ b/arch/inst/V/vwaddu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.wx.yaml b/arch/inst/V/vwaddu.wx.yaml index 8eb165cdd..8719530b1 100644 --- a/arch/inst/V/vwaddu.wx.yaml +++ b/arch/inst/V/vwaddu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmacc.vv.yaml b/arch/inst/V/vwmacc.vv.yaml index 5d41ec9a8..78246982d 100644 --- a/arch/inst/V/vwmacc.vv.yaml +++ b/arch/inst/V/vwmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmacc.vx.yaml b/arch/inst/V/vwmacc.vx.yaml index 8f1e04ea9..1faf42a62 100644 --- a/arch/inst/V/vwmacc.vx.yaml +++ b/arch/inst/V/vwmacc.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccsu.vv.yaml b/arch/inst/V/vwmaccsu.vv.yaml index a635909f9..347cc21ff 100644 --- a/arch/inst/V/vwmaccsu.vv.yaml +++ b/arch/inst/V/vwmaccsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccsu.vx.yaml b/arch/inst/V/vwmaccsu.vx.yaml index 36901bbac..bbb92960c 100644 --- a/arch/inst/V/vwmaccsu.vx.yaml +++ b/arch/inst/V/vwmaccsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccu.vv.yaml b/arch/inst/V/vwmaccu.vv.yaml index 57612798b..6b2d0406c 100644 --- a/arch/inst/V/vwmaccu.vv.yaml +++ b/arch/inst/V/vwmaccu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccu.vx.yaml b/arch/inst/V/vwmaccu.vx.yaml index edf144908..0e3537eee 100644 --- a/arch/inst/V/vwmaccu.vx.yaml +++ b/arch/inst/V/vwmaccu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccus.vx.yaml b/arch/inst/V/vwmaccus.vx.yaml index 0e3070929..1704aace5 100644 --- a/arch/inst/V/vwmaccus.vx.yaml +++ b/arch/inst/V/vwmaccus.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmul.vv.yaml b/arch/inst/V/vwmul.vv.yaml index a32fda5df..88ffd777c 100644 --- a/arch/inst/V/vwmul.vv.yaml +++ b/arch/inst/V/vwmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmul.vx.yaml b/arch/inst/V/vwmul.vx.yaml index 5dc3c3d25..56b2fdf90 100644 --- a/arch/inst/V/vwmul.vx.yaml +++ b/arch/inst/V/vwmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulsu.vv.yaml b/arch/inst/V/vwmulsu.vv.yaml index d7ee5d18d..32a53d3af 100644 --- a/arch/inst/V/vwmulsu.vv.yaml +++ b/arch/inst/V/vwmulsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulsu.vx.yaml b/arch/inst/V/vwmulsu.vx.yaml index 4bc0ea6f9..6d8b53e9b 100644 --- a/arch/inst/V/vwmulsu.vx.yaml +++ b/arch/inst/V/vwmulsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulu.vv.yaml b/arch/inst/V/vwmulu.vv.yaml index 1d157720d..8686115d5 100644 --- a/arch/inst/V/vwmulu.vv.yaml +++ b/arch/inst/V/vwmulu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulu.vx.yaml b/arch/inst/V/vwmulu.vx.yaml index 191102861..8433bb622 100644 --- a/arch/inst/V/vwmulu.vx.yaml +++ b/arch/inst/V/vwmulu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwredsum.vs.yaml b/arch/inst/V/vwredsum.vs.yaml index 869c4fbef..0032bcfd6 100644 --- a/arch/inst/V/vwredsum.vs.yaml +++ b/arch/inst/V/vwredsum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,21 +38,21 @@ sail(): | let LMUL_pow_widen = LMUL_pow + 1; let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ - + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -63,11 +63,10 @@ sail(): | sum = sum + elem } }; - + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwredsumu.vs.yaml b/arch/inst/V/vwredsumu.vs.yaml index d3739d187..700f88b76 100644 --- a/arch/inst/V/vwredsumu.vs.yaml +++ b/arch/inst/V/vwredsumu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,21 +38,21 @@ sail(): | let LMUL_pow_widen = LMUL_pow + 1; let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ - + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -63,11 +63,10 @@ sail(): | sum = sum + elem } }; - + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.vv.yaml b/arch/inst/V/vwsub.vv.yaml index def690ade..14530949a 100644 --- a/arch/inst/V/vwsub.vv.yaml +++ b/arch/inst/V/vwsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.vx.yaml b/arch/inst/V/vwsub.vx.yaml index 037a57975..66a3c69f0 100644 --- a/arch/inst/V/vwsub.vx.yaml +++ b/arch/inst/V/vwsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.wv.yaml b/arch/inst/V/vwsub.wv.yaml index d295bd785..8af49ee0a 100644 --- a/arch/inst/V/vwsub.wv.yaml +++ b/arch/inst/V/vwsub.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.wx.yaml b/arch/inst/V/vwsub.wx.yaml index 76b836b67..a91894f1b 100644 --- a/arch/inst/V/vwsub.wx.yaml +++ b/arch/inst/V/vwsub.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.vv.yaml b/arch/inst/V/vwsubu.vv.yaml index c2b5c8eb0..2b05bf512 100644 --- a/arch/inst/V/vwsubu.vv.yaml +++ b/arch/inst/V/vwsubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.vx.yaml b/arch/inst/V/vwsubu.vx.yaml index d70695bb2..0838d847b 100644 --- a/arch/inst/V/vwsubu.vx.yaml +++ b/arch/inst/V/vwsubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.wv.yaml b/arch/inst/V/vwsubu.wv.yaml index 5da6b8f10..dec2d0698 100644 --- a/arch/inst/V/vwsubu.wv.yaml +++ b/arch/inst/V/vwsubu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.wx.yaml b/arch/inst/V/vwsubu.wx.yaml index 3aab9d1b1..84243dc45 100644 --- a/arch/inst/V/vwsubu.wx.yaml +++ b/arch/inst/V/vwsubu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vi.yaml b/arch/inst/V/vxor.vi.yaml index 9f1e02491..40c557070 100644 --- a/arch/inst/V/vxor.vi.yaml +++ b/arch/inst/V/vxor.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vv.yaml b/arch/inst/V/vxor.vv.yaml index 32f05d9f8..9e3067f6b 100644 --- a/arch/inst/V/vxor.vv.yaml +++ b/arch/inst/V/vxor.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vx.yaml b/arch/inst/V/vxor.vx.yaml index 405e521ed..8ed77e0db 100644 --- a/arch/inst/V/vxor.vx.yaml +++ b/arch/inst/V/vxor.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf2.yaml b/arch/inst/V/vzext.vf2.yaml index f3ef6b579..c978587ca 100644 --- a/arch/inst/V/vzext.vf2.yaml +++ b/arch/inst/V/vzext.vf2.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_half = SEW / 2; let LMUL_pow_half = LMUL_pow - 1; - + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_half; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_half); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf4.yaml b/arch/inst/V/vzext.vf4.yaml index 70832f506..a39b7b881 100644 --- a/arch/inst/V/vzext.vf4.yaml +++ b/arch/inst/V/vzext.vf4.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_quart = SEW / 4; let LMUL_pow_quart = LMUL_pow - 2; - + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_quart; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_quart); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf8.yaml b/arch/inst/V/vzext.vf8.yaml index 8e0fb1c88..4fce98f03 100644 --- a/arch/inst/V/vzext.vf8.yaml +++ b/arch/inst/V/vzext.vf8.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_eighth = SEW / 8; let LMUL_pow_eighth = LMUL_pow - 3; - + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_eighth; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_eighth); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/Zabha/amoadd.b.yaml b/arch/inst/Zabha/amoadd.b.yaml index 5024808c2..a88fe6b2c 100644 --- a/arch/inst/Zabha/amoadd.b.yaml +++ b/arch/inst/Zabha/amoadd.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoadd.h.yaml b/arch/inst/Zabha/amoadd.h.yaml index 07ef0b18f..5b96e7779 100644 --- a/arch/inst/Zabha/amoadd.h.yaml +++ b/arch/inst/Zabha/amoadd.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoand.b.yaml b/arch/inst/Zabha/amoand.b.yaml index abb64cf26..a8f3e6fc2 100644 --- a/arch/inst/Zabha/amoand.b.yaml +++ b/arch/inst/Zabha/amoand.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoand.h.yaml b/arch/inst/Zabha/amoand.h.yaml index dd21970bb..9be12f711 100644 --- a/arch/inst/Zabha/amoand.h.yaml +++ b/arch/inst/Zabha/amoand.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amocas.b.yaml b/arch/inst/Zabha/amocas.b.yaml index a54fff572..58be77749 100644 --- a/arch/inst/Zabha/amocas.b.yaml +++ b/arch/inst/Zabha/amocas.b.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zabha/amocas.h.yaml b/arch/inst/Zabha/amocas.h.yaml index 7406e4a4f..5ea2e2b72 100644 --- a/arch/inst/Zabha/amocas.h.yaml +++ b/arch/inst/Zabha/amocas.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zabha/amomax.b.yaml b/arch/inst/Zabha/amomax.b.yaml index bb49fc9f3..2ca5f2859 100644 --- a/arch/inst/Zabha/amomax.b.yaml +++ b/arch/inst/Zabha/amomax.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomax.h.yaml b/arch/inst/Zabha/amomax.h.yaml index e89c043a5..b8ae26f1a 100644 --- a/arch/inst/Zabha/amomax.h.yaml +++ b/arch/inst/Zabha/amomax.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomaxu.b.yaml b/arch/inst/Zabha/amomaxu.b.yaml index 5cde35d5d..8fad8f562 100644 --- a/arch/inst/Zabha/amomaxu.b.yaml +++ b/arch/inst/Zabha/amomaxu.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomaxu.h.yaml b/arch/inst/Zabha/amomaxu.h.yaml index ea6538fb5..9952ef356 100644 --- a/arch/inst/Zabha/amomaxu.h.yaml +++ b/arch/inst/Zabha/amomaxu.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomin.b.yaml b/arch/inst/Zabha/amomin.b.yaml index bba1d9afe..58f898f01 100644 --- a/arch/inst/Zabha/amomin.b.yaml +++ b/arch/inst/Zabha/amomin.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomin.h.yaml b/arch/inst/Zabha/amomin.h.yaml index 71164e406..7cb010ba0 100644 --- a/arch/inst/Zabha/amomin.h.yaml +++ b/arch/inst/Zabha/amomin.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amominu.b.yaml b/arch/inst/Zabha/amominu.b.yaml index 1ec23a812..aaf8204d5 100644 --- a/arch/inst/Zabha/amominu.b.yaml +++ b/arch/inst/Zabha/amominu.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amominu.h.yaml b/arch/inst/Zabha/amominu.h.yaml index be68c5947..b805456a5 100644 --- a/arch/inst/Zabha/amominu.h.yaml +++ b/arch/inst/Zabha/amominu.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoor.b.yaml b/arch/inst/Zabha/amoor.b.yaml index 7fc285824..c339a8c1e 100644 --- a/arch/inst/Zabha/amoor.b.yaml +++ b/arch/inst/Zabha/amoor.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoor.h.yaml b/arch/inst/Zabha/amoor.h.yaml index 85d3a704d..5c637e671 100644 --- a/arch/inst/Zabha/amoor.h.yaml +++ b/arch/inst/Zabha/amoor.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoswap.b.yaml b/arch/inst/Zabha/amoswap.b.yaml index 68d63647e..e3370fa27 100644 --- a/arch/inst/Zabha/amoswap.b.yaml +++ b/arch/inst/Zabha/amoswap.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoswap.h.yaml b/arch/inst/Zabha/amoswap.h.yaml index 76cf8d38a..81ad25a56 100644 --- a/arch/inst/Zabha/amoswap.h.yaml +++ b/arch/inst/Zabha/amoswap.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoxor.b.yaml b/arch/inst/Zabha/amoxor.b.yaml index ba29559e2..6cc6b9408 100644 --- a/arch/inst/Zabha/amoxor.b.yaml +++ b/arch/inst/Zabha/amoxor.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoxor.h.yaml b/arch/inst/Zabha/amoxor.h.yaml index 3017d2291..a03c9def1 100644 --- a/arch/inst/Zabha/amoxor.h.yaml +++ b/arch/inst/Zabha/amoxor.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zacas/amocas.d.yaml b/arch/inst/Zacas/amocas.d.yaml index 8b7dfe167..d7adbc8fd 100644 --- a/arch/inst/Zacas/amocas.d.yaml +++ b/arch/inst/Zacas/amocas.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zacas/amocas.q.yaml b/arch/inst/Zacas/amocas.q.yaml index 63fa46f73..7c375ab20 100644 --- a/arch/inst/Zacas/amocas.q.yaml +++ b/arch/inst/Zacas/amocas.q.yaml @@ -29,4 +29,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zacas/amocas.w.yaml b/arch/inst/Zacas/amocas.w.yaml index 0e64eccde..5cb79b0d6 100644 --- a/arch/inst/Zacas/amocas.w.yaml +++ b/arch/inst/Zacas/amocas.w.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zalasr/lb.aq.yaml b/arch/inst/Zalasr/lb.aq.yaml index 8b649b935..c77cff6d4 100644 --- a/arch/inst/Zalasr/lb.aq.yaml +++ b/arch/inst/Zalasr/lb.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/ld.aq.yaml b/arch/inst/Zalasr/ld.aq.yaml index 90a37dad1..227d21844 100644 --- a/arch/inst/Zalasr/ld.aq.yaml +++ b/arch/inst/Zalasr/ld.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/lh.aq.yaml b/arch/inst/Zalasr/lh.aq.yaml index 9d3a81213..34542cece 100644 --- a/arch/inst/Zalasr/lh.aq.yaml +++ b/arch/inst/Zalasr/lh.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/lw.aq.yaml b/arch/inst/Zalasr/lw.aq.yaml index 65a5435e4..b0acbfb8d 100644 --- a/arch/inst/Zalasr/lw.aq.yaml +++ b/arch/inst/Zalasr/lw.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sb.rl.yaml b/arch/inst/Zalasr/sb.rl.yaml index 19b6fd35a..4f2a76c0b 100644 --- a/arch/inst/Zalasr/sb.rl.yaml +++ b/arch/inst/Zalasr/sb.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sd.rl.yaml b/arch/inst/Zalasr/sd.rl.yaml index 49af9816b..ea8d44954 100644 --- a/arch/inst/Zalasr/sd.rl.yaml +++ b/arch/inst/Zalasr/sd.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sh.rl.yaml b/arch/inst/Zalasr/sh.rl.yaml index d28714762..626501309 100644 --- a/arch/inst/Zalasr/sh.rl.yaml +++ b/arch/inst/Zalasr/sh.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sw.rl.yaml b/arch/inst/Zalasr/sw.rl.yaml index 48535507b..f93fa6709 100644 --- a/arch/inst/Zalasr/sw.rl.yaml +++ b/arch/inst/Zalasr/sw.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zawrs/wrs.nto.yaml b/arch/inst/Zawrs/wrs.nto.yaml index 4c130ba85..8ca9e6479 100644 --- a/arch/inst/Zawrs/wrs.nto.yaml +++ b/arch/inst/Zawrs/wrs.nto.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zawrs/wrs.sto.yaml b/arch/inst/Zawrs/wrs.sto.yaml index d623a43ea..7052d117c 100644 --- a/arch/inst/Zawrs/wrs.sto.yaml +++ b/arch/inst/Zawrs/wrs.sto.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkb/brev8.yaml b/arch/inst/Zbkb/brev8.yaml index 2a2d5598d..4993648fc 100644 --- a/arch/inst/Zbkb/brev8.yaml +++ b/arch/inst/Zbkb/brev8.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkb/unzip.yaml b/arch/inst/Zbkb/unzip.yaml index 6927616ea..64bff932a 100644 --- a/arch/inst/Zbkb/unzip.yaml +++ b/arch/inst/Zbkb/unzip.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/Zbkb/zip.yaml b/arch/inst/Zbkb/zip.yaml index a542b172e..b5a3b2733 100644 --- a/arch/inst/Zbkb/zip.yaml +++ b/arch/inst/Zbkb/zip.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/Zbkx/xperm4.yaml b/arch/inst/Zbkx/xperm4.yaml index a422462e2..0e1c05fb7 100644 --- a/arch/inst/Zbkx/xperm4.yaml +++ b/arch/inst/Zbkx/xperm4.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkx/xperm8.yaml b/arch/inst/Zbkx/xperm8.yaml index 5f6bb5a59..a0afff2de 100644 --- a/arch/inst/Zbkx/xperm8.yaml +++ b/arch/inst/Zbkx/xperm8.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbp/gorci.yaml b/arch/inst/Zbp/gorci.yaml index 4b61d319b..1b7037d2c 100644 --- a/arch/inst/Zbp/gorci.yaml +++ b/arch/inst/Zbp/gorci.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/grevi.yaml b/arch/inst/Zbp/grevi.yaml index 89bc7860a..1fa748351 100644 --- a/arch/inst/Zbp/grevi.yaml +++ b/arch/inst/Zbp/grevi.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/shfli.yaml b/arch/inst/Zbp/shfli.yaml index 3b30aae23..c903c6ae8 100644 --- a/arch/inst/Zbp/shfli.yaml +++ b/arch/inst/Zbp/shfli.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/unshfli.yaml b/arch/inst/Zbp/unshfli.yaml index 8038269f7..0f49c5324 100644 --- a/arch/inst/Zbp/unshfli.yaml +++ b/arch/inst/Zbp/unshfli.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/xperm16.yaml b/arch/inst/Zbp/xperm16.yaml index afd0ea3fe..ad079aadb 100644 --- a/arch/inst/Zbp/xperm16.yaml +++ b/arch/inst/Zbp/xperm16.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbp/xperm32.yaml b/arch/inst/Zbp/xperm32.yaml index 8045330db..796b19071 100644 --- a/arch/inst/Zbp/xperm32.yaml +++ b/arch/inst/Zbp/xperm32.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zcb/c.lbu.yaml b/arch/inst/Zcb/c.lbu.yaml index b521eb886..0c0a4a0a9 100644 --- a/arch/inst/Zcb/c.lbu.yaml +++ b/arch/inst/Zcb/c.lbu.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lbu -long_name: Load unsigned byte, 16-bit encoding +long_name: Load unsigned byte, 16-bit encoding description: | Loads a 8-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.lh.yaml b/arch/inst/Zcb/c.lh.yaml index 938bf6936..2c29ba108 100644 --- a/arch/inst/Zcb/c.lh.yaml +++ b/arch/inst/Zcb/c.lh.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lh -long_name: Load signed halfword, 16-bit encoding +long_name: Load signed halfword, 16-bit encoding description: | Loads a 16-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.lhu.yaml b/arch/inst/Zcb/c.lhu.yaml index e4567e26e..1d71ead41 100644 --- a/arch/inst/Zcb/c.lhu.yaml +++ b/arch/inst/Zcb/c.lhu.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lhu -long_name: Load unsigned halfword, 16-bit encoding +long_name: Load unsigned halfword, 16-bit encoding description: | Loads a 16-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.mul.yaml b/arch/inst/Zcb/c.mul.yaml index 60f22a711..f27561dbb 100644 --- a/arch/inst/Zcb/c.mul.yaml +++ b/arch/inst/Zcb/c.mul.yaml @@ -42,7 +42,3 @@ sail(): | X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0]; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.not.yaml b/arch/inst/Zcb/c.not.yaml index 2b1ac3651..8612ca93e 100644 --- a/arch/inst/Zcb/c.not.yaml +++ b/arch/inst/Zcb/c.not.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.not long_name: Bitwise not, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. definedBy: @@ -36,7 +36,3 @@ sail(): | X(rsdc) = X(rsdc) XOR -1; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sb.yaml b/arch/inst/Zcb/c.sb.yaml index 95512638b..f4dcfa76c 100644 --- a/arch/inst/Zcb/c.sb.yaml +++ b/arch/inst/Zcb/c.sb.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sb -long_name: Store unsigned byte, 16-bit encoding +long_name: Store unsigned byte, 16-bit encoding description: | Stores a 8-bit value from register rs2 into memory. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.sext.b.yaml b/arch/inst/Zcb/c.sext.b.yaml index f7d368af7..0bd3c24de 100644 --- a/arch/inst/Zcb/c.sext.b.yaml +++ b/arch/inst/Zcb/c.sext.b.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.sext.b long_name: Sign-extend byte, 16-bit encoding description: | - This instruction takes a single source/destination operand. - This instruction sign-extends the least-significant byte of the source to XLEN by copying + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant byte of the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sext.h.yaml b/arch/inst/Zcb/c.sext.h.yaml index 23e181f5f..8f8061605 100644 --- a/arch/inst/Zcb/c.sext.h.yaml +++ b/arch/inst/Zcb/c.sext.h.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.sext.h long_name: Sign-extend halfword, 16-bit encoding description: | - This instruction takes a single source/destination operand. - This instruction sign-extends the least-significant halfword of the source to XLEN by copying + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant halfword of the source to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sh.yaml b/arch/inst/Zcb/c.sh.yaml index eeb0d9511..39d357048 100644 --- a/arch/inst/Zcb/c.sh.yaml +++ b/arch/inst/Zcb/c.sh.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sh -long_name: Store unsigned halfword, 16-bit encoding +long_name: Store unsigned halfword, 16-bit encoding description: | Stores a 16-bit value from register rs2 into memory. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.zext.b.yaml b/arch/inst/Zcb/c.zext.b.yaml index a59b37ac6..0049b6229 100644 --- a/arch/inst/Zcb/c.zext.b.yaml +++ b/arch/inst/Zcb/c.zext.b.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.b long_name: Zero-extend byte, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction zero-extends the least-significant byte of the source to XLEN by inserting 0's into all of the bits more significant than 7. @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.zext.h.yaml b/arch/inst/Zcb/c.zext.h.yaml index 2be0b9bf3..aeff66ef0 100644 --- a/arch/inst/Zcb/c.zext.h.yaml +++ b/arch/inst/Zcb/c.zext.h.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.h long_name: Zero-extend halfword, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0's into all of the bits more significant than 15. @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.zext.w.yaml b/arch/inst/Zcb/c.zext.w.yaml index fc892c6bf..ea226cd04 100644 --- a/arch/inst/Zcb/c.zext.w.yaml +++ b/arch/inst/Zcb/c.zext.w.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.w long_name: Zero-extend word, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml index 9d31847a5..50e616b59 100644 --- a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml +++ b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml index 70af2004a..c6d2dcb9c 100644 --- a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml +++ b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fadd.h.yaml b/arch/inst/Zfh/fadd.h.yaml index 51ac99df5..8ff9819fe 100644 --- a/arch/inst/Zfh/fadd.h.yaml +++ b/arch/inst/Zfh/fadd.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fclass.h.yaml b/arch/inst/Zfh/fclass.h.yaml index 2943a7184..dff44fbda 100644 --- a/arch/inst/Zfh/fclass.h.yaml +++ b/arch/inst/Zfh/fclass.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.d.h.yaml b/arch/inst/Zfh/fcvt.d.h.yaml index d3f147dfc..5f309dcb2 100644 --- a/arch/inst/Zfh/fcvt.d.h.yaml +++ b/arch/inst/Zfh/fcvt.d.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.d.yaml b/arch/inst/Zfh/fcvt.h.d.yaml index b0d4e2ee2..83d8d53ef 100644 --- a/arch/inst/Zfh/fcvt.h.d.yaml +++ b/arch/inst/Zfh/fcvt.h.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.l.yaml b/arch/inst/Zfh/fcvt.h.l.yaml index c3b75a026..a91e39fe6 100644 --- a/arch/inst/Zfh/fcvt.h.l.yaml +++ b/arch/inst/Zfh/fcvt.h.l.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.lu.yaml b/arch/inst/Zfh/fcvt.h.lu.yaml index 037811c38..8bca31838 100644 --- a/arch/inst/Zfh/fcvt.h.lu.yaml +++ b/arch/inst/Zfh/fcvt.h.lu.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.s.yaml b/arch/inst/Zfh/fcvt.h.s.yaml index 808ef24b6..65f87f4e9 100644 --- a/arch/inst/Zfh/fcvt.h.s.yaml +++ b/arch/inst/Zfh/fcvt.h.s.yaml @@ -24,7 +24,7 @@ encoding: - name: rm location: 14-12 - name: fd - location: 11-7 + location: 11-7 access: s: always u: always @@ -76,14 +76,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_H(rd) = rd_val_H; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/Zfh/fcvt.h.w.yaml b/arch/inst/Zfh/fcvt.h.w.yaml index c17da2a24..435226b96 100644 --- a/arch/inst/Zfh/fcvt.h.w.yaml +++ b/arch/inst/Zfh/fcvt.h.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.wu.yaml b/arch/inst/Zfh/fcvt.h.wu.yaml index 4e0a0b503..d1e3e0793 100644 --- a/arch/inst/Zfh/fcvt.h.wu.yaml +++ b/arch/inst/Zfh/fcvt.h.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.l.h.yaml b/arch/inst/Zfh/fcvt.l.h.yaml index c7efe1383..f024f191d 100644 --- a/arch/inst/Zfh/fcvt.l.h.yaml +++ b/arch/inst/Zfh/fcvt.l.h.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.lu.h.yaml b/arch/inst/Zfh/fcvt.lu.h.yaml index 8d98111e7..24adfb47a 100644 --- a/arch/inst/Zfh/fcvt.lu.h.yaml +++ b/arch/inst/Zfh/fcvt.lu.h.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.s.h.yaml b/arch/inst/Zfh/fcvt.s.h.yaml index 9ebd1fe1d..dc69ea9fb 100644 --- a/arch/inst/Zfh/fcvt.s.h.yaml +++ b/arch/inst/Zfh/fcvt.s.h.yaml @@ -21,7 +21,7 @@ encoding: - name: rm location: 14-12 - name: fd - location: 11-7 + location: 11-7 access: s: always u: always @@ -49,7 +49,7 @@ operation(): | # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice - # is OR-red with the sticky + # is OR-red with the sticky Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0); if ((exp | frac16) == 0) { f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0, 0 )); @@ -73,14 +73,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_H(rd) = rd_val_H; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/Zfh/fcvt.w.h.yaml b/arch/inst/Zfh/fcvt.w.h.yaml index 91734b0f8..03c31e5e9 100644 --- a/arch/inst/Zfh/fcvt.w.h.yaml +++ b/arch/inst/Zfh/fcvt.w.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.wu.h.yaml b/arch/inst/Zfh/fcvt.wu.h.yaml index ed7163ee7..2020304a6 100644 --- a/arch/inst/Zfh/fcvt.wu.h.yaml +++ b/arch/inst/Zfh/fcvt.wu.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fdiv.h.yaml b/arch/inst/Zfh/fdiv.h.yaml index 9d0c7b840..ae879ef05 100644 --- a/arch/inst/Zfh/fdiv.h.yaml +++ b/arch/inst/Zfh/fdiv.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/feq.h.yaml b/arch/inst/Zfh/feq.h.yaml index 77c687a95..a2ca9119e 100644 --- a/arch/inst/Zfh/feq.h.yaml +++ b/arch/inst/Zfh/feq.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fle.h.yaml b/arch/inst/Zfh/fle.h.yaml index 212d00238..0328f9f52 100644 --- a/arch/inst/Zfh/fle.h.yaml +++ b/arch/inst/Zfh/fle.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fleq.h.yaml b/arch/inst/Zfh/fleq.h.yaml index 13dd11363..7a7a35eda 100644 --- a/arch/inst/Zfh/fleq.h.yaml +++ b/arch/inst/Zfh/fleq.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/flh.yaml b/arch/inst/Zfh/flh.yaml index 5a25dc1da..76b99366e 100644 --- a/arch/inst/Zfh/flh.yaml +++ b/arch/inst/Zfh/flh.yaml @@ -69,7 +69,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/Zfh/fli.h.yaml b/arch/inst/Zfh/fli.h.yaml index 28932bea8..fb22d8010 100644 --- a/arch/inst/Zfh/fli.h.yaml +++ b/arch/inst/Zfh/fli.h.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/flt.h.yaml b/arch/inst/Zfh/flt.h.yaml index e379cc4b6..6e90a95ca 100644 --- a/arch/inst/Zfh/flt.h.yaml +++ b/arch/inst/Zfh/flt.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fltq.h.yaml b/arch/inst/Zfh/fltq.h.yaml index 59d17dfad..7b3ce83cb 100644 --- a/arch/inst/Zfh/fltq.h.yaml +++ b/arch/inst/Zfh/fltq.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmadd.h.yaml b/arch/inst/Zfh/fmadd.h.yaml index f8e496d6b..71971aac5 100644 --- a/arch/inst/Zfh/fmadd.h.yaml +++ b/arch/inst/Zfh/fmadd.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmax.h.yaml b/arch/inst/Zfh/fmax.h.yaml index e42b1f096..c4d132a5b 100644 --- a/arch/inst/Zfh/fmax.h.yaml +++ b/arch/inst/Zfh/fmax.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmaxm.h.yaml b/arch/inst/Zfh/fmaxm.h.yaml index 1c8ad0fd3..d75b0d325 100644 --- a/arch/inst/Zfh/fmaxm.h.yaml +++ b/arch/inst/Zfh/fmaxm.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmin.h.yaml b/arch/inst/Zfh/fmin.h.yaml index f132ad6be..84699940c 100644 --- a/arch/inst/Zfh/fmin.h.yaml +++ b/arch/inst/Zfh/fmin.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fminm.h.yaml b/arch/inst/Zfh/fminm.h.yaml index 368564f3b..17ed7b705 100644 --- a/arch/inst/Zfh/fminm.h.yaml +++ b/arch/inst/Zfh/fminm.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmsub.h.yaml b/arch/inst/Zfh/fmsub.h.yaml index 6a04f4513..9b17b7d82 100644 --- a/arch/inst/Zfh/fmsub.h.yaml +++ b/arch/inst/Zfh/fmsub.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmul.h.yaml b/arch/inst/Zfh/fmul.h.yaml index 09ec68e0e..b6185aa0c 100644 --- a/arch/inst/Zfh/fmul.h.yaml +++ b/arch/inst/Zfh/fmul.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmv.h.x.yaml b/arch/inst/Zfh/fmv.h.x.yaml index 701e871f4..e6c8e7648 100644 --- a/arch/inst/Zfh/fmv.h.x.yaml +++ b/arch/inst/Zfh/fmv.h.x.yaml @@ -40,7 +40,3 @@ sail(): | F(rd) = nan_box (rd_val_H); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfh/fmv.x.h.yaml b/arch/inst/Zfh/fmv.x.h.yaml index 269579031..ecd308564 100644 --- a/arch/inst/Zfh/fmv.x.h.yaml +++ b/arch/inst/Zfh/fmv.x.h.yaml @@ -22,7 +22,7 @@ encoding: - name: fs1 location: 19-15 - name: rd - location: 11-7 + location: 11-7 access: s: always u: always @@ -42,7 +42,3 @@ sail(): | F(rd) = nan_box (rd_val_H); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfh/fnmadd.h.yaml b/arch/inst/Zfh/fnmadd.h.yaml index 8598d1233..61b3efbcd 100644 --- a/arch/inst/Zfh/fnmadd.h.yaml +++ b/arch/inst/Zfh/fnmadd.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fnmsub.h.yaml b/arch/inst/Zfh/fnmsub.h.yaml index 226882bdc..1f59bda40 100644 --- a/arch/inst/Zfh/fnmsub.h.yaml +++ b/arch/inst/Zfh/fnmsub.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fround.h.yaml b/arch/inst/Zfh/fround.h.yaml index 4fa3d1d50..027675715 100644 --- a/arch/inst/Zfh/fround.h.yaml +++ b/arch/inst/Zfh/fround.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/froundnx.h.yaml b/arch/inst/Zfh/froundnx.h.yaml index ec5f4fdeb..a2477a504 100644 --- a/arch/inst/Zfh/froundnx.h.yaml +++ b/arch/inst/Zfh/froundnx.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnj.h.yaml b/arch/inst/Zfh/fsgnj.h.yaml index d0f1d6dbe..a3a42471d 100644 --- a/arch/inst/Zfh/fsgnj.h.yaml +++ b/arch/inst/Zfh/fsgnj.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnjn.h.yaml b/arch/inst/Zfh/fsgnjn.h.yaml index 54b4e0d8a..b6454c376 100644 --- a/arch/inst/Zfh/fsgnjn.h.yaml +++ b/arch/inst/Zfh/fsgnjn.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnjx.h.yaml b/arch/inst/Zfh/fsgnjx.h.yaml index b52101aea..8b30873bf 100644 --- a/arch/inst/Zfh/fsgnjx.h.yaml +++ b/arch/inst/Zfh/fsgnjx.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsh.yaml b/arch/inst/Zfh/fsh.yaml index 90d13183d..6edc5d18f 100644 --- a/arch/inst/Zfh/fsh.yaml +++ b/arch/inst/Zfh/fsh.yaml @@ -37,7 +37,7 @@ operation(): | XReg virtual_address = X[rs1] + $signed(imm); Bits<16> hp_value = f[fs2][15:0]; - + write_memory<16>(virtual_address, hp_value, $encoding); @@ -80,7 +80,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/Zfh/fsqrt.h.yaml b/arch/inst/Zfh/fsqrt.h.yaml index d38f24379..61d70bfc8 100644 --- a/arch/inst/Zfh/fsqrt.h.yaml +++ b/arch/inst/Zfh/fsqrt.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsub.h.yaml b/arch/inst/Zfh/fsub.h.yaml index 956661d97..a280c6fa5 100644 --- a/arch/inst/Zfh/fsub.h.yaml +++ b/arch/inst/Zfh/fsub.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicbom/cbo.clean.yaml b/arch/inst/Zicbom/cbo.clean.yaml index 0d933f207..04c8461d7 100644 --- a/arch/inst/Zicbom/cbo.clean.yaml +++ b/arch/inst/Zicbom/cbo.clean.yaml @@ -5,7 +5,7 @@ kind: instruction name: cbo.clean long_name: Cache Block Clean description: | - Cleans an entire cache block globally throughout the system. + Cleans an entire cache block globally throughout the system. Exactly what happens is coherence protocol-dependent, but in general it is expected that after this operation(): @@ -34,7 +34,7 @@ description: | <%- end -%> CBO operations never raise a misaligned address fault. - + definedBy: Zicbom assembly: "TODO" encoding: @@ -59,14 +59,13 @@ access_detail: | 4+^.>h! `cbo.clean` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== # operation(): | # let cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); # CACHE_BLOCK_CLEAN(cache_block_address); - diff --git a/arch/inst/Zicbom/cbo.flush.yaml b/arch/inst/Zicbom/cbo.flush.yaml index 1f9d0e382..068a2d238 100644 --- a/arch/inst/Zicbom/cbo.flush.yaml +++ b/arch/inst/Zicbom/cbo.flush.yaml @@ -26,7 +26,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicbom assembly: "TODO" @@ -52,10 +52,10 @@ access_detail: | 4+^.>h! `cbo.flush` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== # operation(): | @@ -67,4 +67,3 @@ access_detail: | # if (has_fault?) { # raise(code); # } - diff --git a/arch/inst/Zicbom/cbo.inval.yaml b/arch/inst/Zicbom/cbo.inval.yaml index cfd36a767..f0d1d9ac8 100644 --- a/arch/inst/Zicbom/cbo.inval.yaml +++ b/arch/inst/Zicbom/cbo.inval.yaml @@ -25,20 +25,20 @@ description: | 5+^.>h! `cbe.inval` Operation .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01 ! 00 ! 00 ! Invalidate ! Flush ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01 ! 00 ! 01 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 01 ! 00 ! 11 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 00 ! 00 ! Invalidate ! Flush ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 00 ! 01 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 00 ! 11 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 01 ! 01 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 01 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 01 ! 11 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush - ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction` - ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction` + ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 11 ! 01 ! 01 ! Invalidate ! Invalidate ! Flush ! Flush ! Flush ! 11 ! 01 ! 11 ! Invalidate ! Invalidate ! Flush ! Invalidate ! Flush ! 11 ! 11 ! 00 ! Invalidate ! Invalidate ! Invalidate ! `Virtual Instruction` ! `Virtual Instruction` @@ -65,7 +65,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicbom assembly: "TODO" @@ -95,10 +95,10 @@ access_detail: | 4+^.>h! `cbo.inval` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 00 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 00 ! 00 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 01/11 ! 00 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 00 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 00 ! 00 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 01/11 ! 00 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 01/11 ! 01/11 ! 01/11 ! executes ! executes ! executes ! executes !=== # operation(): | diff --git a/arch/inst/Zicboz/cbo.zero.yaml b/arch/inst/Zicboz/cbo.zero.yaml index 476c7b1a6..8457260bd 100644 --- a/arch/inst/Zicboz/cbo.zero.yaml +++ b/arch/inst/Zicboz/cbo.zero.yaml @@ -28,7 +28,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicboz assembly: "TODO" @@ -54,16 +54,16 @@ access_detail: | 4+^.>h! `cbo.zero` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== operation(): | if ((mode() == PrivilegeMode::M && CSR[menvcfg].CBZE == 0) || (mode() == PrivilegeMode::U && CSR[senvcfg].CBZE == 0)) { - raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); } else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].CBZE ==0) || (mode() == PrivilegeMode::VU && (CSR[henvcfg].CBZE | CSR[senvcfg].CBZE) == 0)) { diff --git a/arch/inst/Zicfilp/lpad.yaml b/arch/inst/Zicfilp/lpad.yaml index 376bce829..d06692598 100644 --- a/arch/inst/Zicfilp/lpad.yaml +++ b/arch/inst/Zicfilp/lpad.yaml @@ -21,4 +21,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssamoswap.d.yaml b/arch/inst/Zicfiss/ssamoswap.d.yaml index 6c1ca2738..6c6018c08 100644 --- a/arch/inst/Zicfiss/ssamoswap.d.yaml +++ b/arch/inst/Zicfiss/ssamoswap.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssamoswap.w.yaml b/arch/inst/Zicfiss/ssamoswap.w.yaml index 1c608eef0..df5c208ce 100644 --- a/arch/inst/Zicfiss/ssamoswap.w.yaml +++ b/arch/inst/Zicfiss/ssamoswap.w.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspopchk.x1.yaml b/arch/inst/Zicfiss/sspopchk.x1.yaml index 31d6c20e5..f81089bca 100644 --- a/arch/inst/Zicfiss/sspopchk.x1.yaml +++ b/arch/inst/Zicfiss/sspopchk.x1.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspopchk.x5.yaml b/arch/inst/Zicfiss/sspopchk.x5.yaml index 9f77ca1c1..9fc5f4bfe 100644 --- a/arch/inst/Zicfiss/sspopchk.x5.yaml +++ b/arch/inst/Zicfiss/sspopchk.x5.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspush.x1.yaml b/arch/inst/Zicfiss/sspush.x1.yaml index 6d4a0b880..bb4361007 100644 --- a/arch/inst/Zicfiss/sspush.x1.yaml +++ b/arch/inst/Zicfiss/sspush.x1.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspush.x5.yaml b/arch/inst/Zicfiss/sspush.x5.yaml index e4b7957c1..d2c6e13c0 100644 --- a/arch/inst/Zicfiss/sspush.x5.yaml +++ b/arch/inst/Zicfiss/sspush.x5.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssrdp.yaml b/arch/inst/Zicfiss/ssrdp.yaml index 93597b957..4204bbe1f 100644 --- a/arch/inst/Zicfiss/ssrdp.yaml +++ b/arch/inst/Zicfiss/ssrdp.yaml @@ -21,4 +21,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml index f14e7397b..539e7e422 100644 --- a/arch/inst/Zicond/czero.eqz.yaml +++ b/arch/inst/Zicond/czero.eqz.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,4 +37,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml index c8dcd203d..5dc0a2102 100644 --- a/arch/inst/Zicond/czero.nez.yaml +++ b/arch/inst/Zicond/czero.nez.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,4 +37,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index c03fda2b8..283cccab7 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index 3473497ef..95b2a1625 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 38b1ca38a..5a5ea9f9c 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -68,7 +68,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 2ad946d19..67f2cd171 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 0e4ba92c7..9625c3895 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -31,7 +31,7 @@ access: operation(): | if (rd != 0) { X[rd] = CSR[csr].sw_read(); - } + } # writes the value in X[rs1] to the CSR, # performing any WARL transformations first @@ -64,7 +64,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index 7a304af4f..1da44ef62 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -31,7 +31,7 @@ access: operation(): | if (rd != 0) { X[rd] = CSR[csr].sw_read(); - } + } # writes the zero-extended immediate to the CSR, # performing any WARL transformations first @@ -64,7 +64,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zifencei/fence.i.yaml b/arch/inst/Zifencei/fence.i.yaml index f829bb961..63793c2f9 100644 --- a/arch/inst/Zifencei/fence.i.yaml +++ b/arch/inst/Zifencei/fence.i.yaml @@ -53,7 +53,3 @@ operation(): | sail(): | { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zimop/mop.r.n.yaml b/arch/inst/Zimop/mop.r.n.yaml index bc90d9beb..dcce06e56 100644 --- a/arch/inst/Zimop/mop.r.n.yaml +++ b/arch/inst/Zimop/mop.r.n.yaml @@ -93,4 +93,3 @@ pseudoinstructions: - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) to: mop.r.31 operation(): | - diff --git a/arch/inst/Zimop/mop.rr.n.yaml b/arch/inst/Zimop/mop.rr.n.yaml index e8de57ec7..4681771f1 100644 --- a/arch/inst/Zimop/mop.rr.n.yaml +++ b/arch/inst/Zimop/mop.rr.n.yaml @@ -45,4 +45,3 @@ pseudoinstructions: - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) to: mop.rr.7 operation(): | - diff --git a/arch/inst/Zk/aes32dsi.yaml b/arch/inst/Zk/aes32dsi.yaml index 4c6a4b8fe..e192c720b 100644 --- a/arch/inst/Zk/aes32dsi.yaml +++ b/arch/inst/Zk/aes32dsi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32dsmi.yaml b/arch/inst/Zk/aes32dsmi.yaml index d94fef7d4..760aa8056 100644 --- a/arch/inst/Zk/aes32dsmi.yaml +++ b/arch/inst/Zk/aes32dsmi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32esi.yaml b/arch/inst/Zk/aes32esi.yaml index 378aa0670..dde581325 100644 --- a/arch/inst/Zk/aes32esi.yaml +++ b/arch/inst/Zk/aes32esi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32esmi.yaml b/arch/inst/Zk/aes32esmi.yaml index 879bf4114..39a54cf93 100644 --- a/arch/inst/Zk/aes32esmi.yaml +++ b/arch/inst/Zk/aes32esmi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ds.yaml b/arch/inst/Zk/aes64ds.yaml index 07ebdac8c..61dfb89de 100644 --- a/arch/inst/Zk/aes64ds.yaml +++ b/arch/inst/Zk/aes64ds.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64dsm.yaml b/arch/inst/Zk/aes64dsm.yaml index b4f744fd0..eef0dbbcb 100644 --- a/arch/inst/Zk/aes64dsm.yaml +++ b/arch/inst/Zk/aes64dsm.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64es.yaml b/arch/inst/Zk/aes64es.yaml index 4e50e4062..5963c7a06 100644 --- a/arch/inst/Zk/aes64es.yaml +++ b/arch/inst/Zk/aes64es.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64esm.yaml b/arch/inst/Zk/aes64esm.yaml index af29db499..3013b2a06 100644 --- a/arch/inst/Zk/aes64esm.yaml +++ b/arch/inst/Zk/aes64esm.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64im.yaml b/arch/inst/Zk/aes64im.yaml index d0ab1847c..3b5a5388b 100644 --- a/arch/inst/Zk/aes64im.yaml +++ b/arch/inst/Zk/aes64im.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ks1i.yaml b/arch/inst/Zk/aes64ks1i.yaml index 30b9e1cfc..48520c22d 100644 --- a/arch/inst/Zk/aes64ks1i.yaml +++ b/arch/inst/Zk/aes64ks1i.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ks2.yaml b/arch/inst/Zk/aes64ks2.yaml index a332f844c..e2189ca92 100644 --- a/arch/inst/Zk/aes64ks2.yaml +++ b/arch/inst/Zk/aes64ks2.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/pack.yaml b/arch/inst/Zk/pack.yaml index 49e915a75..1a4a5d048 100644 --- a/arch/inst/Zk/pack.yaml +++ b/arch/inst/Zk/pack.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/packh.yaml b/arch/inst/Zk/packh.yaml index 3e8b5f79e..6101e75fc 100644 --- a/arch/inst/Zk/packh.yaml +++ b/arch/inst/Zk/packh.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/packw.yaml b/arch/inst/Zk/packw.yaml index 12b2f0eb6..b7a986491 100644 --- a/arch/inst/Zk/packw.yaml +++ b/arch/inst/Zk/packw.yaml @@ -29,4 +29,3 @@ pseudoinstructions: - when: (rs2 == 0x0) to: zext.h operation(): | - diff --git a/arch/inst/Zk/sha256sig0.yaml b/arch/inst/Zk/sha256sig0.yaml index 8a6ac1cb6..2ec32995d 100644 --- a/arch/inst/Zk/sha256sig0.yaml +++ b/arch/inst/Zk/sha256sig0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sig1.yaml b/arch/inst/Zk/sha256sig1.yaml index 377612933..5534e2678 100644 --- a/arch/inst/Zk/sha256sig1.yaml +++ b/arch/inst/Zk/sha256sig1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sum0.yaml b/arch/inst/Zk/sha256sum0.yaml index eda4a5c35..c80507c04 100644 --- a/arch/inst/Zk/sha256sum0.yaml +++ b/arch/inst/Zk/sha256sum0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sum1.yaml b/arch/inst/Zk/sha256sum1.yaml index fa4876685..94849b65e 100644 --- a/arch/inst/Zk/sha256sum1.yaml +++ b/arch/inst/Zk/sha256sum1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0.yaml b/arch/inst/Zk/sha512sig0.yaml index f7d4f909a..65e4fecda 100644 --- a/arch/inst/Zk/sha512sig0.yaml +++ b/arch/inst/Zk/sha512sig0.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0h.yaml b/arch/inst/Zk/sha512sig0h.yaml index 872046027..36e442d5e 100644 --- a/arch/inst/Zk/sha512sig0h.yaml +++ b/arch/inst/Zk/sha512sig0h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0l.yaml b/arch/inst/Zk/sha512sig0l.yaml index df86a0356..b45759fe5 100644 --- a/arch/inst/Zk/sha512sig0l.yaml +++ b/arch/inst/Zk/sha512sig0l.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1.yaml b/arch/inst/Zk/sha512sig1.yaml index e75977bb4..83965f0fe 100644 --- a/arch/inst/Zk/sha512sig1.yaml +++ b/arch/inst/Zk/sha512sig1.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1h.yaml b/arch/inst/Zk/sha512sig1h.yaml index 2ae02b4e3..6dacd3aad 100644 --- a/arch/inst/Zk/sha512sig1h.yaml +++ b/arch/inst/Zk/sha512sig1h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1l.yaml b/arch/inst/Zk/sha512sig1l.yaml index c1f26069d..e9312f90e 100644 --- a/arch/inst/Zk/sha512sig1l.yaml +++ b/arch/inst/Zk/sha512sig1l.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum0.yaml b/arch/inst/Zk/sha512sum0.yaml index 3d8c409c6..86ab00438 100644 --- a/arch/inst/Zk/sha512sum0.yaml +++ b/arch/inst/Zk/sha512sum0.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum0r.yaml b/arch/inst/Zk/sha512sum0r.yaml index db81f95f5..c535ac091 100644 --- a/arch/inst/Zk/sha512sum0r.yaml +++ b/arch/inst/Zk/sha512sum0r.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum1.yaml b/arch/inst/Zk/sha512sum1.yaml index ddc243d7d..ab6ab69de 100644 --- a/arch/inst/Zk/sha512sum1.yaml +++ b/arch/inst/Zk/sha512sum1.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum1r.yaml b/arch/inst/Zk/sha512sum1r.yaml index b4fb002ac..e1d04a9ab 100644 --- a/arch/inst/Zk/sha512sum1r.yaml +++ b/arch/inst/Zk/sha512sum1r.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zks/sm3p0.yaml b/arch/inst/Zks/sm3p0.yaml index 9c42bf2e9..b0fbadc4a 100644 --- a/arch/inst/Zks/sm3p0.yaml +++ b/arch/inst/Zks/sm3p0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm3p1.yaml b/arch/inst/Zks/sm3p1.yaml index 6a51a96a1..993184605 100644 --- a/arch/inst/Zks/sm3p1.yaml +++ b/arch/inst/Zks/sm3p1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm4ed.yaml b/arch/inst/Zks/sm4ed.yaml index b8512294c..df729eb2f 100644 --- a/arch/inst/Zks/sm4ed.yaml +++ b/arch/inst/Zks/sm4ed.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm4ks.yaml b/arch/inst/Zks/sm4ks.yaml index 9854e61b5..6ae18d806 100644 --- a/arch/inst/Zks/sm4ks.yaml +++ b/arch/inst/Zks/sm4ks.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vandn.vv.yaml b/arch/inst/Zvbb/vandn.vv.yaml index 27667b63e..4da0076e0 100644 --- a/arch/inst/Zvbb/vandn.vv.yaml +++ b/arch/inst/Zvbb/vandn.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vandn.vx.yaml b/arch/inst/Zvbb/vandn.vx.yaml index 252b3444c..2ffe56347 100644 --- a/arch/inst/Zvbb/vandn.vx.yaml +++ b/arch/inst/Zvbb/vandn.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vbrev.v.yaml b/arch/inst/Zvbb/vbrev.v.yaml index 175e50f27..71cebe309 100644 --- a/arch/inst/Zvbb/vbrev.v.yaml +++ b/arch/inst/Zvbb/vbrev.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vbrev8.v.yaml b/arch/inst/Zvbb/vbrev8.v.yaml index 14df079e2..4a4007d42 100644 --- a/arch/inst/Zvbb/vbrev8.v.yaml +++ b/arch/inst/Zvbb/vbrev8.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vclz.v.yaml b/arch/inst/Zvbb/vclz.v.yaml index 52776b73d..4365156a7 100644 --- a/arch/inst/Zvbb/vclz.v.yaml +++ b/arch/inst/Zvbb/vclz.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vcpop.v.yaml b/arch/inst/Zvbb/vcpop.v.yaml index 0145035e4..fefb67c38 100644 --- a/arch/inst/Zvbb/vcpop.v.yaml +++ b/arch/inst/Zvbb/vcpop.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vctz.v.yaml b/arch/inst/Zvbb/vctz.v.yaml index 0b03fbad5..d05953576 100644 --- a/arch/inst/Zvbb/vctz.v.yaml +++ b/arch/inst/Zvbb/vctz.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrev8.v.yaml b/arch/inst/Zvbb/vrev8.v.yaml index 79477546e..6fad0de88 100644 --- a/arch/inst/Zvbb/vrev8.v.yaml +++ b/arch/inst/Zvbb/vrev8.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrol.vv.yaml b/arch/inst/Zvbb/vrol.vv.yaml index 1c54fa104..cd07d39b1 100644 --- a/arch/inst/Zvbb/vrol.vv.yaml +++ b/arch/inst/Zvbb/vrol.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrol.vx.yaml b/arch/inst/Zvbb/vrol.vx.yaml index 395871d9e..1210af58e 100644 --- a/arch/inst/Zvbb/vrol.vx.yaml +++ b/arch/inst/Zvbb/vrol.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vi.yaml b/arch/inst/Zvbb/vror.vi.yaml index f2dc45e56..78eebbb5a 100644 --- a/arch/inst/Zvbb/vror.vi.yaml +++ b/arch/inst/Zvbb/vror.vi.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vv.yaml b/arch/inst/Zvbb/vror.vv.yaml index 5289f2f82..f2f40fe91 100644 --- a/arch/inst/Zvbb/vror.vv.yaml +++ b/arch/inst/Zvbb/vror.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vx.yaml b/arch/inst/Zvbb/vror.vx.yaml index 40a3469c7..d2a77d6b7 100644 --- a/arch/inst/Zvbb/vror.vx.yaml +++ b/arch/inst/Zvbb/vror.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vi.yaml b/arch/inst/Zvbb/vwsll.vi.yaml index 86264addb..591c1bed5 100644 --- a/arch/inst/Zvbb/vwsll.vi.yaml +++ b/arch/inst/Zvbb/vwsll.vi.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vv.yaml b/arch/inst/Zvbb/vwsll.vv.yaml index 4e6c43fd1..2b3a21c37 100644 --- a/arch/inst/Zvbb/vwsll.vv.yaml +++ b/arch/inst/Zvbb/vwsll.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vx.yaml b/arch/inst/Zvbb/vwsll.vx.yaml index 56c02f818..bee40592d 100644 --- a/arch/inst/Zvbb/vwsll.vx.yaml +++ b/arch/inst/Zvbb/vwsll.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmul.vv.yaml b/arch/inst/Zvbc/vclmul.vv.yaml index bb69c75ef..5546905fe 100644 --- a/arch/inst/Zvbc/vclmul.vv.yaml +++ b/arch/inst/Zvbc/vclmul.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmul.vx.yaml b/arch/inst/Zvbc/vclmul.vx.yaml index 550a28392..9e965b1be 100644 --- a/arch/inst/Zvbc/vclmul.vx.yaml +++ b/arch/inst/Zvbc/vclmul.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmulh.vv.yaml b/arch/inst/Zvbc/vclmulh.vv.yaml index bce6dbdcf..4a077cfc0 100644 --- a/arch/inst/Zvbc/vclmulh.vv.yaml +++ b/arch/inst/Zvbc/vclmulh.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmulh.vx.yaml b/arch/inst/Zvbc/vclmulh.vx.yaml index 5bd7e1ae3..ff4ed9467 100644 --- a/arch/inst/Zvbc/vclmulh.vx.yaml +++ b/arch/inst/Zvbc/vclmulh.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml index b1ee08cf4..c6e7afbed 100644 --- a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +++ b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml index 0da2a89c2..c5300811c 100644 --- a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +++ b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml index a80a38513..fa975d1b4 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml index d50b3db0d..dc775e29b 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkg/vghsh.vv.yaml b/arch/inst/Zvkg/vghsh.vv.yaml index ffaa78827..25cf67cf7 100644 --- a/arch/inst/Zvkg/vghsh.vv.yaml +++ b/arch/inst/Zvkg/vghsh.vv.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkg/vgmul.vv.yaml b/arch/inst/Zvkg/vgmul.vv.yaml index a1d2dc1ed..c4e1a173f 100644 --- a/arch/inst/Zvkg/vgmul.vv.yaml +++ b/arch/inst/Zvkg/vgmul.vv.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdf.vs.yaml b/arch/inst/Zvkn/vaesdf.vs.yaml index 0996304f1..9a870b3d7 100644 --- a/arch/inst/Zvkn/vaesdf.vs.yaml +++ b/arch/inst/Zvkn/vaesdf.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdf.vv.yaml b/arch/inst/Zvkn/vaesdf.vv.yaml index aa4a6c059..7ecb3e260 100644 --- a/arch/inst/Zvkn/vaesdf.vv.yaml +++ b/arch/inst/Zvkn/vaesdf.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdm.vs.yaml b/arch/inst/Zvkn/vaesdm.vs.yaml index 68f3a3004..4f6ba265c 100644 --- a/arch/inst/Zvkn/vaesdm.vs.yaml +++ b/arch/inst/Zvkn/vaesdm.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdm.vv.yaml b/arch/inst/Zvkn/vaesdm.vv.yaml index c3c043f20..3fc90fcec 100644 --- a/arch/inst/Zvkn/vaesdm.vv.yaml +++ b/arch/inst/Zvkn/vaesdm.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesef.vs.yaml b/arch/inst/Zvkn/vaesef.vs.yaml index c335467b3..b3d18719d 100644 --- a/arch/inst/Zvkn/vaesef.vs.yaml +++ b/arch/inst/Zvkn/vaesef.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesef.vv.yaml b/arch/inst/Zvkn/vaesef.vv.yaml index 07d123a8f..0e692cf83 100644 --- a/arch/inst/Zvkn/vaesef.vv.yaml +++ b/arch/inst/Zvkn/vaesef.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesem.vs.yaml b/arch/inst/Zvkn/vaesem.vs.yaml index 574400752..7010af1bb 100644 --- a/arch/inst/Zvkn/vaesem.vs.yaml +++ b/arch/inst/Zvkn/vaesem.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesem.vv.yaml b/arch/inst/Zvkn/vaesem.vv.yaml index cb29270c0..ae5618f1d 100644 --- a/arch/inst/Zvkn/vaesem.vv.yaml +++ b/arch/inst/Zvkn/vaesem.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaeskf1.vi.yaml b/arch/inst/Zvkn/vaeskf1.vi.yaml index acfc9c1f4..ea88d6459 100644 --- a/arch/inst/Zvkn/vaeskf1.vi.yaml +++ b/arch/inst/Zvkn/vaeskf1.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaeskf2.vi.yaml b/arch/inst/Zvkn/vaeskf2.vi.yaml index bb5e68084..c00b3621d 100644 --- a/arch/inst/Zvkn/vaeskf2.vi.yaml +++ b/arch/inst/Zvkn/vaeskf2.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesz.vs.yaml b/arch/inst/Zvkn/vaesz.vs.yaml index 8d471a615..970a9bae8 100644 --- a/arch/inst/Zvkn/vaesz.vs.yaml +++ b/arch/inst/Zvkn/vaesz.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2ch.vv.yaml b/arch/inst/Zvkn/vsha2ch.vv.yaml index c7c307289..d29bd4d82 100644 --- a/arch/inst/Zvkn/vsha2ch.vv.yaml +++ b/arch/inst/Zvkn/vsha2ch.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2cl.vv.yaml b/arch/inst/Zvkn/vsha2cl.vv.yaml index af0a15046..9aa0dd3c2 100644 --- a/arch/inst/Zvkn/vsha2cl.vv.yaml +++ b/arch/inst/Zvkn/vsha2cl.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2ms.vv.yaml b/arch/inst/Zvkn/vsha2ms.vv.yaml index 3ed25d80f..57e5cea2c 100644 --- a/arch/inst/Zvkn/vsha2ms.vv.yaml +++ b/arch/inst/Zvkn/vsha2ms.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm3c.vi.yaml b/arch/inst/Zvks/vsm3c.vi.yaml index ce7ee47ad..03d5de481 100644 --- a/arch/inst/Zvks/vsm3c.vi.yaml +++ b/arch/inst/Zvks/vsm3c.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm3me.vv.yaml b/arch/inst/Zvks/vsm3me.vv.yaml index 083bc526b..25b76850b 100644 --- a/arch/inst/Zvks/vsm3me.vv.yaml +++ b/arch/inst/Zvks/vsm3me.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4k.vi.yaml b/arch/inst/Zvks/vsm4k.vi.yaml index fb641d68f..14056756f 100644 --- a/arch/inst/Zvks/vsm4k.vi.yaml +++ b/arch/inst/Zvks/vsm4k.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4r.vs.yaml b/arch/inst/Zvks/vsm4r.vs.yaml index 9fa81255a..e21b71637 100644 --- a/arch/inst/Zvks/vsm4r.vs.yaml +++ b/arch/inst/Zvks/vsm4r.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4r.vv.yaml b/arch/inst/Zvks/vsm4r.vv.yaml index 40f6c8b67..e1d60fd3d 100644 --- a/arch/inst/Zvks/vsm4r.vv.yaml +++ b/arch/inst/Zvks/vsm4r.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index 076984752..9c47a0cb4 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -422,11 +422,11 @@ builtin function atomically_set_pte_a { U32 pte_len description { Atomically: - + * Reads the _pte_len_ value at _pte_addr_ ** If the read value does not exactly equal pte_value, returns false * Sets the 'A' bit and writes the result to _pte_addr_ - * return true + * return true Preconditions: @@ -442,7 +442,7 @@ builtin function atomically_set_pte_a_d { U32 pte_len description { Atomically: - + * Reads the _pte_len_ value at _pte_addr_ ** If the read value does not exactly equal pte_value, returns false * Sets the 'A' and 'D' bits and writes the result to _pte_addr_ diff --git a/arch/isa/fp.idl b/arch/isa/fp.idl index fcaeb70d2..62c018d1c 100644 --- a/arch/isa/fp.idl +++ b/arch/isa/fp.idl @@ -314,7 +314,7 @@ function softfloat_shiftRightJam64 { be zero. If any nonzero bits are shifted off, they are "jammed" into the least-significant bit of the shifted value by setting the least-significant bit to 1. This shifted-and-jammed value is returned. - + The value of 'dist' can be arbitrarily large. In particular, if +dist+ is greater than 64, the result will be either 0 or 1, depending on whether +a+ is zero or nonzero. @@ -484,4 +484,4 @@ function softfloat_normRoundPackToF32 { return softfloat_roundPackToF32(sign, exp, sig << shiftDist, mode); } } -} \ No newline at end of file +} diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa index 4145e7391..1c47f1772 100644 --- a/arch/isa/globals.isa +++ b/arch/isa/globals.isa @@ -887,7 +887,7 @@ function pmp_match_64 { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -955,7 +955,7 @@ function pmp_match_32 { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -1023,7 +1023,7 @@ function pmp_match { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -1423,7 +1423,7 @@ function translate_gstage { raise_guest_page_fault(op, gpaddr, vaddr, tinst_value_for_guest_page_fault(op, encoding, true), effective_mode); } } - } + } } function tinst_value_for_guest_page_fault { @@ -1715,7 +1715,7 @@ function gstage_page_walk { # first level is x4 for G-stage, so add two bits to the vpn size U32 this_vpn_size = (i == (LEVELS - 1)) ? VPN_SIZE + 2 : VPN_SIZE; U32 vpn = (gpaddr >> (12 + VPN_SIZE*i)) & ((1 << this_vpn_size) - 1); - + Bits pte_paddr = (ppn << 12) + (vpn * (PTESIZE/8)); # check hw page table access permission @@ -2219,7 +2219,7 @@ function translate { +effective_mode+. The translation will depend on the effective privilege mode. - + May raise a Page Fault or Access Fault. The final physical address is *not* access checked (for PMP, PMA, etc., violations). @@ -2251,7 +2251,7 @@ function translate { # there is no translation in M-mode return vaddr; } - + SatpMode translation_mode = current_translation_mode(effective_mode); @@ -2317,7 +2317,7 @@ function canonical_vaddr? { return true; } else if (satp_mode == SatpMode::Sv32) { # Sv32 uses all 32 bits of the VA - return true; + return true; } else if (satp_mode == SatpMode::Sv39) { return eaddr[63:39] == {25{eaddr[38]}}; } else if (satp_mode == SatpMode::Sv48) { @@ -2343,7 +2343,7 @@ function canonical_gpaddr? { return true; } else if (satp_mode == SatpMode::Sv32) { # Sv32 uses all 32 bits of the VA - return true; + return true; } else if ((XLEN > 32) && (satp_mode == SatpMode::Sv39)) { return gpaddr[63:39] == {25{gpaddr[38]}}; } else if ((XLEN > 32) && (satp_mode == SatpMode::Sv48)) { @@ -2430,7 +2430,7 @@ function read_memory { if (aligned) { return read_memory_aligned(virtual_address, encoding); } - + # access isn't naturally aligned, but it still might be atomic if this hart supports # Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs # apply to physical addresses @@ -2754,7 +2754,7 @@ function write_memory { if (aligned) { write_memory_aligned(virtual_address, value, encoding); } - + # access isn't naturally aligned, but it still might be atomic if this hart supports # Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs # apply to physical addresses diff --git a/arch/isa/util.idl b/arch/isa/util.idl index 3b8370c89..097b51ccb 100644 --- a/arch/isa/util.idl +++ b/arch/isa/util.idl @@ -177,7 +177,7 @@ function in_naturally_aligned_region? { } body { XReg Mask = (N/8) - 1; - + return (address & ~Mask) == ((address + length - 1) & ~Mask); } } @@ -199,4 +199,4 @@ function contains? { target_start >= region_start && (target_start + target_size) <= (region_start + region_size); } -} \ No newline at end of file +} diff --git a/arch/manual/isa/20240411/contents.yaml b/arch/manual/isa/20240411/contents.yaml index 91901d70a..3ade2dea1 100644 --- a/arch/manual/isa/20240411/contents.yaml +++ b/arch/manual/isa/20240411/contents.yaml @@ -218,4 +218,4 @@ volumes: - [Svvptc, "1.0.0"] - [Sstc, "1.0.0"] - [Sscofpmf, "1.0.0"] - - [H, "1.0.0"] \ No newline at end of file + - [H, "1.0.0"] diff --git a/arch/manual/isa/isa.yaml b/arch/manual/isa/isa.yaml index ed762ec09..7d573628b 100644 --- a/arch/manual/isa/isa.yaml +++ b/arch/manual/isa/isa.yaml @@ -5,4 +5,4 @@ license: id: CC-BY-4.0 name: Creative Commons Attribution 4.0 International Public License url: https://creativecommons.org/licenses/by/4.0/legalcode -# versions are found in by search all subdirectories for "contents.yaml" \ No newline at end of file +# versions are found in by search all subdirectories for "contents.yaml" diff --git a/arch/profile_class/MockProfileClass.yaml b/arch/profile_class/MockProfileClass.yaml index d7f2af6e7..613e4460b 100644 --- a/arch/profile_class/MockProfileClass.yaml +++ b/arch/profile_class/MockProfileClass.yaml @@ -12,4 +12,4 @@ MockProfileClass: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVA.yaml b/arch/profile_class/RVA.yaml index db88fc9cc..9c0df8d1a 100644 --- a/arch/profile_class/RVA.yaml +++ b/arch/profile_class/RVA.yaml @@ -18,18 +18,18 @@ RVA: substantial fraction of software to be delivered to end-customers in binary form, compatibility across multiple implementations from different RISC-V vendors is required. - + The RVIA ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present. However, by themselves, the ISA extension specifications do not guarantee that a certain set of standard extensions will be present in all implementations. - + *The primary goal of the RVA profiles is to align processor vendors targeting binary software markets, so software can rely on the existence of a certain set of ISA features in a particular generation of RISC-V implementations.* - + Alignment is not only for compatibility, but also to ensure RISC-V is competitive in these markets. The binary app markets are also generally those with the most competitive performance requirements @@ -48,7 +48,7 @@ RVA: for certain limited cases, and binary app markets will not support a wide range of optional features, particularly for the nascent RISC-V binary app ecosystems. - + To maintain alignment and increase RISC-V competitiveness over time, the mandatory set of extensions must increase over time in successive generations of RVA profile. (RVA profiles may eventually have to @@ -63,11 +63,11 @@ RVA: considerable investment, and no single binary app ecosystem can justify the development costs of these processors, especially for RISC-V in its early stage of adoption. - + While the heart of the profile is the set of mandatory extensions, there are several kinds of optional extension that serve important roles in the profile. - + The first kind are _localized_ _options_, whose presence or use necessarily differs along geo-political and/or jurisdictional boundaries, with crypto being the obvious example. These will always @@ -75,7 +75,7 @@ RVA: perfectly acceptable to handle this optionality on other architectures, as the use of the extensions is well contained in certain libraries. - + The second kind of optional extension is a _development_ _option_, which represents a new ISA extension in an early part of its lifecycle but which is intended to become mandatory in a later generation of the @@ -87,7 +87,7 @@ RVA: Denoting an extension as a _development_ _option_ signals to the community that development should be prioritized for such extensions as they will become mandatory. - + The third kind of optional extension are _expansion_ _options_, which are those that may have a large implementation cost but are not always needed in a particular platform, and which can be readily handled by @@ -99,7 +99,7 @@ RVA: future matrix extensions. These have large implementation costs, and use of matrix instructions can be readily supported with discovery and alternate math libraries. - + The fourth kind of optional extensions are _transitory_ _options_, where it is not clear if the extension will change to a mandatory, localized, or expansion option, or be possibly dropped over time. @@ -113,7 +113,7 @@ RVA: term. Denoting an option as transitory signals to the community that this extension may be removed in a future profile, though the time scale may span many years. - + Except for the localized options, it could be argued that other three kinds of option could be left out of profiles. Binary distributions of applications willing to invest in discovery can use an optional @@ -142,4 +142,4 @@ RVA: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVB.yaml b/arch/profile_class/RVB.yaml index f9529ef1d..ea4239f69 100644 --- a/arch/profile_class/RVB.yaml +++ b/arch/profile_class/RVB.yaml @@ -47,4 +47,4 @@ RVB: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVI.yaml b/arch/profile_class/RVI.yaml index ed900ef3d..daad9e90c 100644 --- a/arch/profile_class/RVI.yaml +++ b/arch/profile_class/RVI.yaml @@ -3,7 +3,7 @@ RVI: introduction: The RVI profile class documents the initial set of unprivileged instructions. description: | The RVI profile class provides a generic target for software toolchains - and represent the minimum level of compatibility with RISC-V ratified standards. + and represent the minimum level of compatibility with RISC-V ratified standards. NOTE: Profiles in this class are designated as _unprivileged_ profiles as opposed to _user_-_mode_ profiles. Code using this profile class can run in any @@ -25,4 +25,4 @@ RVI: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 45104cdec..6b18b173d 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -4,7 +4,7 @@ MockProfileRelease: class: MockProfileClass release: 20 state: ratified # current status ["ratified", "development"] - versions: + versions: - version: "1.0" ratification_date: "2024-01-01" introduction: Here's the Mock Profile Release introduction. @@ -50,21 +50,21 @@ MockProfileRelease: presence: mandatory note: This should be listed as mandatory in MP-S-64 and optional in MP-U-64. S: - presence: + presence: optional: localized version: "~> 1.12" Zifencei: - presence: + presence: optional: development version: "~> 2.0" - note: + note: Zihpm: - presence: + presence: optional: expansion version: "~> 2.0" note: Made this a expansion option Sv48: - presence: + presence: optional: transitory version: "~> 1.11" note: Made this a transitory option @@ -78,23 +78,23 @@ MockProfileRelease: Here's the first extra note for the optional extensions section. In this case, we don't differentiate between optional types. This note is multiple lines. - - presence: + - presence: optional: localized text: Here's the first extra note for the localized optional extensions section. - - presence: + - presence: optional: localized text: Here's the second extra note for the localized optional extensions section. - - presence: + - presence: optional: development text: Here's the first extra note for the development optional extensions section. - - presence: + - presence: optional: expansion text: Here's the first extra note for the expansion optional extensions section. - - presence: + - presence: optional: transitory text: Here's the first extra note for the transitory optional extensions section. recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes. - - text: Micky should give Pluto an extra treat \ No newline at end of file + - text: Micky should give Pluto an extra treat diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index 279024c2c..b920ef717 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -7,7 +7,7 @@ RVA20: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -162,7 +162,7 @@ RVA20: version: "~> 1.0" note: | Svbare is a new extension name introduced with RVA20. - + It is subsequently defined in more detail with the ratification of `Svadu`. Ssccptr: @@ -187,4 +187,4 @@ RVA20: presence: optional version: "~> 1.0" note: | - Ssu64xl is a new extension name introduced with RVA20. \ No newline at end of file + Ssu64xl is a new extension name introduced with RVA20. diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 9cf0c14e9..3df820062 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -7,7 +7,7 @@ RVA22: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -124,7 +124,7 @@ RVA22: The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, Zve64x) are not provided as separately supported profile options. The full V extension is specified as the only supported profile option. - + A future profile might mandate V. Zkn: presence: optional @@ -255,7 +255,7 @@ RVA22: version: "~> 1.0" note: | The following extensions become mandatory when H is implemented: - + * Ssstateen * Shcounterenw * Shvstvala @@ -265,4 +265,4 @@ RVA22: recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. \ No newline at end of file + exceptions on attempts to execute unimplemented opcodes. diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 07e8e1081..3bd5b6750 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -7,7 +7,7 @@ RVI20: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -31,14 +31,14 @@ RVI20: version: "~> 2.1" note: | RVI is the mandatory base ISA for RVA, and is little-endian. - + As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment. - + Misaligned loads and stores might not be supported. - + The `fence.tso` instruction is mandatory. - + NOTE: The `fence.tso` instruction was incorrectly described as optional in the 2019 ratified specifications. However, `fence.tso` is encoded within the standard `fence` encoding such that implementations @@ -86,4 +86,4 @@ RVI20: RVI20U64: $inherits: "#/RVI20/profiles/RVI20U32" base: 64 - marketing_name: RVI20U64 \ No newline at end of file + marketing_name: RVI20U64 diff --git a/arch/prose/idl.adoc b/arch/prose/idl.adoc index d8f4bdb24..a67cdbadb 100644 --- a/arch/prose/idl.adoc +++ b/arch/prose/idl.adoc @@ -367,7 +367,7 @@ Literals may contain any number of underscores after the initial digit for clari # gotcha -17 # 15 decimal: the literal is 17, unsigned, in 5-bits. when negated, the sign bit lost --13 # 3 decimal: the literal is 13, unsigned, in 4-bits. when negated, the sign bit is lost +-13 # 3 decimal: the literal is 13, unsigned, in 4-bits. when negated, the sign bit is lost ---- @@ -425,7 +425,7 @@ The result of a binary operation is signed if both operands are signed; otherwis .2+| 0 | `i[idx]` | `Bits<1>` | Extract a single bit from bit position `idx`. + `i` must be an integral type or an array. + Result is unsigned, regardless of the sign of `i`. - + | `i[msb:lsb]` | `Bits` | Extract a range of bits between `msb` and `lsb`, inclusive. + `i` must be an integral type. + Result is unsigned, regardless of the sign of `i`. @@ -470,19 +470,19 @@ The result of a binary operation is signed if both operands are signed; otherwis | `i - j` | `Bits` | Subtraction + The carry bit is discarded. + - If the carry bit is needed, the operands can be widened prior to subtraction. + If the carry bit is needed, the operands can be widened prior to subtraction. -.3+| 8 | `i << j` a| +.3+| 8 | `i << j` a| [%autowidth] !=== ! When ! Then ! `j` is literal ! `Bits` ! `j` is variable ! `typeof(i)` -!=== +!=== | Left logical shift. + When the shift amount is known at compile time, the result is widened to not lose any data. + When the shift amount is not known at compile time, the shifted bits are discarded. - + | `i >> j` | `typeof(i)` | Right logical shift. | `i >>> j` | `typeof(i)` | Right arithmetic shift. @@ -519,7 +519,7 @@ The result of a binary operation is signed if both operands are signed; otherwis === Mutable variables -Variables must be declared with a type. Variable names must begin with a lowercase letter and can be followed by any number of letters (any case), numbers, or an underscore. +Variables must be declared with a type. Variable names must begin with a lowercase letter and can be followed by any number of letters (any case), numbers, or an underscore. Variables may be optionally initialized when they are declared using the assignment operator. Variables that are not explicitly initialized are implicitly initialized to zero (for Bits) or false (for Boolean). @@ -553,7 +553,7 @@ Two builtin variables exist: | Name | Type | Scope | Description | `$pc` | `Bits` | Global | The current program counter of the hart -| `$encoding` | `Bits`, where VARIABLE is the length of the last fetched insruction | Instruction, Csr | The encoding of the last fetched instruction. Only accessible in Instruction scope and Csr scope (cannot be used in functions). +| `$encoding` | `Bits`, where VARIABLE is the length of the last fetched insruction | Instruction, Csr | The encoding of the last fetched instruction. Only accessible in Instruction scope and Csr scope (cannot be used in functions). |=== === Constants @@ -590,7 +590,7 @@ All configuration parameters are added to Global scope for compilation. == Type conversions -Type conversions occur when dissimilar types are used in some binary operators or assignments. +Type conversions occur when dissimilar types are used in some binary operators or assignments. `Bits` types are converted as follows: @@ -767,7 +767,7 @@ Functions must be given a textual description; this is to promote IDL as an exec All arguments and return values are passed by value. There are no references or variable addresses in IDL. -Functions must live in global scope. Functions cannot be nested. +Functions must live in global scope. Functions cannot be nested. A function may return zero or more values of any valid type. A function may accept zero or more arguments of any valid type. @@ -781,7 +781,7 @@ IDL supports templated functions that take a compile-time-known constant as an a IDL only supports template values (_i.e._, you cannot pass a type as a template argument). Template values must be a Bits type. -Template functions are called using C++-style syntax, with the template argument enclosed in angle brackets. +Template functions are called using C++-style syntax, with the template argument enclosed in angle brackets. IDL cannot infer template arguments; they must be provided explictly. @@ -939,7 +939,7 @@ instret: field.sw_write(csr_value):: -The "sw_write(csr_value)" function of a CSR field executes when a software write (via a `Zicsr` instruction) occurs. It takes a single value, `csr_value`, that is an implicitly-defined bitfield of the CSR populated with the values software is trying to write. It returns a Bits value repsenting what hardware is actually going to write into the field, where N is the width of the field. sw_write may also return the special value `UNDEFINED_LEGAL_DETERMINISTIC` to indicate that the written value is undefined, but it will be a legal value for the field and is deterministically determined based on the sequence of instructions leading to the write. +The "sw_write(csr_value)" function of a CSR field executes when a software write (via a `Zicsr` instruction) occurs. It takes a single value, `csr_value`, that is an implicitly-defined bitfield of the CSR populated with the values software is trying to write. It returns a Bits value repsenting what hardware is actually going to write into the field, where N is the width of the field. sw_write may also return the special value `UNDEFINED_LEGAL_DETERMINISTIC` to indicate that the written value is undefined, but it will be a legal value for the field and is deterministically determined based on the sequence of instructions leading to the write. [NOTE] Note that the sw_read is specified for the entire CSR and the sw_write is specified for a CSR field. diff --git a/arch/prose/interrupts.adoc b/arch/prose/interrupts.adoc index 935c96cab..82571cac8 100644 --- a/arch/prose/interrupts.adoc +++ b/arch/prose/interrupts.adoc @@ -1,7 +1,7 @@ [[sec:interrupts]] = Interrupts -== Machine Interrupt (`mip` and `mie`) Registers +== Machine Interrupt (`mip` and `mie`) Registers The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding @@ -179,4 +179,4 @@ Restricted views of the `mip` and `mie` registers appear as the `sip` and `sie` registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the `mideleg` register, it becomes visible in the `sip` register and is maskable using the `sie` register. -Otherwise, the corresponding bits in `sip` and `sie` are read-only zero. \ No newline at end of file +Otherwise, the corresponding bits in `sip` and `sie` are read-only zero. diff --git a/backends/arch_gen/lib/arch_gen.rb b/backends/arch_gen/lib/arch_gen.rb index 7f424fd6f..e88857923 100644 --- a/backends/arch_gen/lib/arch_gen.rb +++ b/backends/arch_gen/lib/arch_gen.rb @@ -165,7 +165,7 @@ def params_extra_validation private :params_extra_validation # validate the params.yaml file of a config. - # + # # This does several things: # # * Generates a config-specific schmea based on: @@ -314,13 +314,13 @@ def gen_arch_def manual_info_files = Dir.glob($root / "arch" / "manual" / "**" / "#{manual_id}.yaml") raise "Could not find manual info '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.empty? raise "Found multiple manual infos '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.size > 1 - + manual_info_file = manual_info_files.first manual_hash[manual_id] = YamlLoader.load(manual_info_file, permitted_classes:[Date]) manual_hash[manual_id]["__source"] = manual_info_file # TODO: schema validation end - + manual_hash[manual_id]["versions"] ||= [] manual_hash[manual_id]["versions"] << YamlLoader.load(f, permitted_classes:[Date]) # TODO: schema validation @@ -645,7 +645,7 @@ def maybe_add_csr(csr_name, extra_env = {}) end belongs = csr_obj.exists_in_cfg?(arch_def_mock) - + @implemented_csrs ||= [] @implemented_csrs << csr_name if belongs diff --git a/backends/arch_gen/tasks.rake b/backends/arch_gen/tasks.rake index e8ebbf40d..fca19e28e 100644 --- a/backends/arch_gen/tasks.rake +++ b/backends/arch_gen/tasks.rake @@ -134,7 +134,7 @@ rule %r{#{$root}/\.stamps/arch-gen-.*\.stamp} => proc { |tname| "#{ARCH_GEN_DIR}/tasks.rake", arch_files, config_files, - + # the stamp file is not actually dependent on the Ruby object model, # but in general we want to rebuild anything using this stamp when the object model changes obj_model_files.map(&:to_s) diff --git a/backends/certificate_doc/tasks.rake b/backends/certificate_doc/tasks.rake index 106c38c11..33c3d0d29 100644 --- a/backends/certificate_doc/tasks.rake +++ b/backends/certificate_doc/tasks.rake @@ -17,7 +17,7 @@ Dir.glob("#{$root}/arch/certificate_model/*.yaml") do |f| base = cert_model_obj["base"] raise "Missing certificate model base" if base.nil? - + file "#{$root}/gen/certificate_doc/adoc/#{cert_model_name}.adoc" => [ "#{$root}/arch/certificate_model/#{cert_model_name}.yaml", "#{$root}/arch/certificate_class/#{cert_class_name}.yaml", @@ -40,7 +40,7 @@ Dir.glob("#{$root}/arch/certificate_model/*.yaml") do |f| erb = ERB.new(File.read("#{CERT_DOC_DIR}/templates/certificate.adoc.erb"), trim_mode: "-") erb.filename = "#{CERT_DOC_DIR}/templates/certificate.adoc.erb" - + FileUtils.mkdir_p File.dirname(t.name) File.write t.name, AsciidocUtils.resolve_links(arch_def.find_replace_links(erb.result(binding))) puts "Generated adoc source at #{t.name}" @@ -122,4 +122,4 @@ namespace :gen do Rake::Task["#{$root}/gen/certificate_doc/html/#{args[:cert_model_name]}.html"].invoke end -end \ No newline at end of file +end diff --git a/backends/certificate_doc/templates/certificate.adoc.erb b/backends/certificate_doc/templates/certificate.adoc.erb index b71e4d1d4..740a98f76 100644 --- a/backends/certificate_doc/templates/certificate.adoc.erb +++ b/backends/certificate_doc/templates/certificate.adoc.erb @@ -1,5 +1,5 @@ // Number heading sections (e.g., 1.0, 1.1, etc.) -:sectnums: +:sectnums: // Add a table of contents for HTML (and VSCode adoc preview) :toc: left @@ -27,7 +27,7 @@ History of documentation changes that eventually lead to releases. | Date | Revision | Changes <% cert_model.revision_history.each do |rev| -%> -| <%= rev.date %> +| <%= rev.date %> | <%= rev.revision %> a| <% rev.changes.each do |change| %> * <%= change %> @@ -118,8 +118,8 @@ None <% ext_reqs.sort.each do |ext_req| -%> <% ext = arch_def.extension(ext_req.name) -%> -| <%= ext_req.req_id %> -| <-def,<%= ext_req.name %>>> +| <%= ext_req.req_id %> +| <-def,<%= ext_req.name %>>> | <%= ext_req.version_requirement %> | <%= ext.nil? ? "" : ext.long_name %> | <%= ext_req.note.nil? ? "" : ext_req.note %> @@ -153,7 +153,7 @@ not provided in the associated standard. === IN-SCOPE Parameters -These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are IN-SCOPE. +These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are IN-SCOPE. An implementation must abide by the "Allowed Value(s)" to obtain a certificate. If the "Allowed Value(s)" is "Any" then any value allowed by the type is acceptable. @@ -178,8 +178,8 @@ a| <%= in_scope_ext_param.note %> === OUT-OF-SCOPE Parameters -These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are OUT-OF-SCOPE. -There are no restrictions on their values for certification purposes because the certificate +These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are OUT-OF-SCOPE. +There are no restrictions on their values for certification purposes because the certificate doesn't cover the behavior of the associated RISC-V standard as a function of these parameters. <% if cert_model.all_out_of_scope_params.empty? -%> @@ -309,7 +309,7 @@ Requirement <%= req.name %> only apply when <%= req.when_pretty %>. Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <% end -%> @@ -413,20 +413,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <% else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <% end -%> @@ -689,4 +689,4 @@ This CSR may return a value that is different from what is stored in hardware. ---- <%- end -%> -<% end # do csrs -%> \ No newline at end of file +<% end # do csrs -%> diff --git a/backends/cfg_html_doc/templates/ext.adoc.erb b/backends/cfg_html_doc/templates/ext.adoc.erb index 1808e4941..eaa8d34ef 100644 --- a/backends/cfg_html_doc/templates/ext.adoc.erb +++ b/backends/cfg_html_doc/templates/ext.adoc.erb @@ -15,7 +15,7 @@ Implemented Version:: <%= ext_version.version %> Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> @@ -62,4 +62,4 @@ This extension has the following implementation options: -- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/cfg_html_doc/templates/func.adoc.erb b/backends/cfg_html_doc/templates/func.adoc.erb index 83eb37aaf..3c281bbff 100644 --- a/backends/cfg_html_doc/templates/func.adoc.erb +++ b/backends/cfg_html_doc/templates/func.adoc.erb @@ -35,4 +35,4 @@ Pruned:: ==== <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/cfg_html_doc/templates/inst.adoc.erb b/backends/cfg_html_doc/templates/inst.adoc.erb index 7159fdced..dd0a2c5a1 100644 --- a/backends/cfg_html_doc/templates/inst.adoc.erb +++ b/backends/cfg_html_doc/templates/inst.adoc.erb @@ -20,20 +20,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <%- else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(arch_def.param_values["XLEN"]) %> .... <%- end -%> @@ -132,4 +132,3 @@ This instruction may result in the following synchronous exceptions: <%- end -%> <%- end -%> - diff --git a/backends/cfg_html_doc/templates/landing.adoc.erb b/backends/cfg_html_doc/templates/landing.adoc.erb index 6f30dbe50..6f66fa3ce 100644 --- a/backends/cfg_html_doc/templates/landing.adoc.erb +++ b/backends/cfg_html_doc/templates/landing.adoc.erb @@ -14,4 +14,4 @@ Additionally, the following documentation is also included: * xref:prose:idl.adoc[IDL language reference] This site was generated using -https://github.com/riscv-software-src/riscv-unified-db[the RISC-V Unified Database]. \ No newline at end of file +https://github.com/riscv-software-src/riscv-unified-db[the RISC-V Unified Database]. diff --git a/backends/cfg_html_doc/templates/toc.adoc.erb b/backends/cfg_html_doc/templates/toc.adoc.erb index 0282723d5..6c951bccc 100644 --- a/backends/cfg_html_doc/templates/toc.adoc.erb +++ b/backends/cfg_html_doc/templates/toc.adoc.erb @@ -19,4 +19,4 @@ * xref:funcs:funcs.adoc[Global function defintions] .Appendix -* xref:prose:idl.adoc[IDL guide] \ No newline at end of file +* xref:prose:idl.adoc[IDL guide] diff --git a/backends/ext_pdf_doc/idl_lexer.rb b/backends/ext_pdf_doc/idl_lexer.rb index c9998e930..c89af9fe0 100644 --- a/backends/ext_pdf_doc/idl_lexer.rb +++ b/backends/ext_pdf_doc/idl_lexer.rb @@ -5,7 +5,7 @@ module Lexers class Idl < RegexLexer tag "idl" filenames "idl", "isa" - + title "IDL" desc "ISA Description Language" diff --git a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb index 44501d85b..faf81fae8 100644 --- a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb +++ b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb @@ -167,7 +167,7 @@ Design document:: <%= version.url %> Changes:: <% version.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> diff --git a/backends/manual/templates/csr.adoc.erb b/backends/manual/templates/csr.adoc.erb index 23e1205a9..b5e59f47f 100644 --- a/backends/manual/templates/csr.adoc.erb +++ b/backends/manual/templates/csr.adoc.erb @@ -167,4 +167,3 @@ This CSR may return a value that is different from what is stored in hardware. <%= csr.sw_read_ast(arch_def.symtab).gen_adoc %> ---- <%- end -%> - diff --git a/backends/manual/templates/ext.adoc.erb b/backends/manual/templates/ext.adoc.erb index 410576a9c..a3e5fdfa1 100644 --- a/backends/manual/templates/ext.adoc.erb +++ b/backends/manual/templates/ext.adoc.erb @@ -67,4 +67,4 @@ h| Description a| <%= param.desc %> -- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/manual/templates/func.adoc.erb b/backends/manual/templates/func.adoc.erb index 9c723b238..a725f3014 100644 --- a/backends/manual/templates/func.adoc.erb +++ b/backends/manual/templates/func.adoc.erb @@ -39,4 +39,4 @@ None ---- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/manual/templates/instruction.adoc.erb b/backends/manual/templates/instruction.adoc.erb index 32d9af233..c1339a432 100644 --- a/backends/manual/templates/instruction.adoc.erb +++ b/backends/manual/templates/instruction.adoc.erb @@ -40,20 +40,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <%- else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <%- end -%> @@ -153,4 +153,3 @@ This instruction may result in the following synchronous exceptions: <%- end -%> <%- end -%> - diff --git a/backends/manual/templates/isa_version_index.adoc.erb b/backends/manual/templates/isa_version_index.adoc.erb index 4f68f1a89..59037e3fc 100644 --- a/backends/manual/templates/isa_version_index.adoc.erb +++ b/backends/manual/templates/isa_version_index.adoc.erb @@ -7,4 +7,3 @@ This version is RATIFIED. It will not change. <%- else -%> This version is a DRAFT. It may change. <%- end -%> - diff --git a/backends/manual/templates/param_list.adoc.erb b/backends/manual/templates/param_list.adoc.erb index 518e38253..dd273b85b 100644 --- a/backends/manual/templates/param_list.adoc.erb +++ b/backends/manual/templates/param_list.adoc.erb @@ -15,4 +15,4 @@ The following <%= params.size %> parameters are defined in this manual: | <%= param.exts.map { |ext| "`#{ext.name}`"}.join(", ") %> a| <%= param.desc %> <%- end -%> -|=== \ No newline at end of file +|=== diff --git a/backends/manual/templates/playbook.yml.erb b/backends/manual/templates/playbook.yml.erb index fddeaf637..3ffafdf7a 100644 --- a/backends/manual/templates/playbook.yml.erb +++ b/backends/manual/templates/playbook.yml.erb @@ -102,4 +102,4 @@ ui: .doc .admonitionblock td.icon i.icon-when::after { text-transform: none; - } \ No newline at end of file + } diff --git a/backends/portfolio_doc/templates/family_intro.erb b/backends/portfolio_doc/templates/family_intro.erb index 30314419c..837125fb6 100644 --- a/backends/portfolio_doc/templates/family_intro.erb +++ b/backends/portfolio_doc/templates/family_intro.erb @@ -8,4 +8,4 @@ === <%= portfolio_class.name %> Class Description -<%= portfolio_class.description %> \ No newline at end of file +<%= portfolio_class.description %> diff --git a/backends/profile_doc/templates/profile.adoc.erb b/backends/profile_doc/templates/profile.adoc.erb index 166ec08b7..e310413d0 100644 --- a/backends/profile_doc/templates/profile.adoc.erb +++ b/backends/profile_doc/templates/profile.adoc.erb @@ -363,7 +363,7 @@ The <%= profile_class.marketing_name %> Profile Class references <%= profile_release.introduction %> -<%= profile_release.marketing_name %> has <%= profile_release.referenced_extensions.reduce(0) { |sum, ext| sum + ext.params.size } %> +<%= profile_release.marketing_name %> has <%= profile_release.referenced_extensions.reduce(0) { |sum, ext| sum + ext.params.size } %> associated implementation-defined parameters across all its defined profiles. <% unless profile_release.description.nil? -%> @@ -438,7 +438,7 @@ associated implementation-defined parameters. Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> @@ -524,20 +524,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <% else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <% end -%> @@ -698,4 +698,4 @@ This CSR format changes dynamically with XLEN. <% end -%> -<% end -%> \ No newline at end of file +<% end -%> diff --git a/bin/pre-commit b/bin/pre-commit index b7b56416c..ccf0660f4 100755 --- a/bin/pre-commit +++ b/bin/pre-commit @@ -3,4 +3,3 @@ ROOT=$(dirname $(dirname $(realpath $BASH_SOURCE[0]))) ${ROOT}/bin/bash -c "source ${ROOT}/.home/.venv/bin/activate && pre-commit $@" - diff --git a/cfgs/_32/implemented_exts.yaml b/cfgs/_32/implemented_exts.yaml index 11151c245..a532cca51 100644 --- a/cfgs/_32/implemented_exts.yaml +++ b/cfgs/_32/implemented_exts.yaml @@ -1 +1 @@ -implemented_extensions: [] \ No newline at end of file +implemented_extensions: [] diff --git a/cfgs/_64/implemented_exts.yaml b/cfgs/_64/implemented_exts.yaml index 11151c245..a532cca51 100644 --- a/cfgs/_64/implemented_exts.yaml +++ b/cfgs/_64/implemented_exts.yaml @@ -1 +1 @@ -implemented_extensions: [] \ No newline at end of file +implemented_extensions: [] diff --git a/cfgs/config_validation.rb b/cfgs/config_validation.rb index 40d428d3f..23d582890 100644 --- a/cfgs/config_validation.rb +++ b/cfgs/config_validation.rb @@ -22,7 +22,7 @@ assert [nil, 32].include?(UXLEN) if ext?(:S) && ext?(:U) && SXLEN == 32 max_va_width = - if ext?(:Sv57) + if ext?(:Sv57) 57 elsif ext?(:Sv48) 48 diff --git a/cfgs/generic_rv64/params.yaml b/cfgs/generic_rv64/params.yaml index 4ed77881a..ace3ee74d 100644 --- a/cfgs/generic_rv64/params.yaml +++ b/cfgs/generic_rv64/params.yaml @@ -448,8 +448,8 @@ params: # Strategy used to handle reservation sets # - # * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address - # * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address + # * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address + # * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address # * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more # * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC LRSC_RESERVATION_STRATEGY: reserve naturally-aligned 64-byte region diff --git a/docs/index.html b/docs/index.html index 4b05e2f88..9786ceb70 100644 --- a/docs/index.html +++ b/docs/index.html @@ -13,4 +13,4 @@

Ruby documentation

- \ No newline at end of file + diff --git a/lib/DB_MODEL.README.adoc b/lib/DB_MODEL.README.adoc index 6c08061d8..982562fb4 100644 --- a/lib/DB_MODEL.README.adoc +++ b/lib/DB_MODEL.README.adoc @@ -2,7 +2,7 @@ A Ruby interface for https://github.com/riscv-software-src/riscv-unified-db[`riscv-unified-db`] is located in the `lib` directory. It can be used to query the database in the context of a configuration through a set of object models. -The main class is `ArchDef`, which represents all of the database information plus any known configuration parameters. An `ArchDef` must be initialized from a configuration in the `cfg` directory. Two configurations are provided -- _32 and _64 -- that represent generic RV32/RV64 machines (_i.e._, the only known configuration parameter is `MXLEN`). +The main class is `ArchDef`, which represents all of the database information plus any known configuration parameters. An `ArchDef` must be initialized from a configuration in the `cfg` directory. Two configurations are provided -- _32 and _64 -- that represent generic RV32/RV64 machines (_i.e._, the only known configuration parameter is `MXLEN`). == Configuration files @@ -13,7 +13,7 @@ A configuration consists of a folder under `cfgs`. Inside that folder, there are `cfg.yaml`:: A YAML object (hash) that currently contains only one field `type`. `type` can be one of: -* "partially configured": The configuration has some parameters and/or implemented extensions known, but others are not known. Examples of a _partially configured_ configuration are the generic _32/_64 configs and a profile (which has some known/mandatory extensions, but also many unknown/optional extensions). +* "partially configured": The configuration has some parameters and/or implemented extensions known, but others are not known. Examples of a _partially configured_ configuration are the generic _32/_64 configs and a profile (which has some known/mandatory extensions, but also many unknown/optional extensions). * "fully configured": The configuration exhaustively lists a set of implmented extensions and parameters. An example of a _fully configured_ configuration is the `generic_rv64` example, which represents a theoritical implementation of RV64. In a _fully configured_ configuration, any extension that isn't known to be implemented is treated as unimplmented, and will be pruned out of the database for certain operations. `implemented_exts.yaml`:: @@ -96,4 +96,4 @@ arch_def.implemented_csrs # the `mstatus.MPRV` CSR field arch_def.csr("mstatus").field("MPRV") #=> CsrField ----- \ No newline at end of file +---- diff --git a/lib/arch_def.rb b/lib/arch_def.rb index 8a297af7f..3c6821531 100644 --- a/lib/arch_def.rb +++ b/lib/arch_def.rb @@ -1,8 +1,8 @@ # frozen_string_literal: true # Many classes have an "arch_def" member which is an ArchDef (not ArchDefObject) class. -# The "arch_def" member contains the "database" of RISC-V standards including extensions, instructions, -# CSRs, Profiles, and Certificates. +# The "arch_def" member contains the "database" of RISC-V standards including extensions, instructions, +# CSRs, Profiles, and Certificates. # # The arch_def member has methods such as: # extensions() Array of all extensions known to the database (even if not implemented). @@ -179,7 +179,7 @@ def type_check(show_progress: true, io: $stdout) unless field.type_ast(@symtab).nil? if ((possible_xlens.include?(32) && csr.defined_in_base32? && field.defined_in_base32?) || (possible_xlens.include?(64) && csr.defined_in_base64? && field.defined_in_base64?)) - field.type_checked_type_ast(@symtab) + field.type_checked_type_ast(@symtab) end end unless field.reset_value_ast(@symtab).nil? @@ -911,7 +911,7 @@ def ref(uri) def implemented_csrs return @implemented_csrs unless @implemented_csrs.nil? - @implemented_csrs = + @implemented_csrs = if @arch_def.key?("implemented_csrs") csrs.select { |c| @arch_def["implemented_csrs"].include?(c.name) } else diff --git a/lib/arch_obj_models/certificate.rb b/lib/arch_obj_models/certificate.rb index 5b8f0552a..833c2f172 100644 --- a/lib/arch_obj_models/certificate.rb +++ b/lib/arch_obj_models/certificate.rb @@ -136,4 +136,4 @@ def requirement_groups end @requirement_groups end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index 77613e8ee..4747e05b3 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -272,7 +272,7 @@ def length_cond64 # @return [String] Pretty-printed length string def length_pretty(arch_def, effective_xlen=nil) if dynamic_length?(arch_def) - cond = + cond = case @data["length"] when "MXLEN" "CSR[misa].MXL == %%" diff --git a/lib/arch_obj_models/csr_field.rb b/lib/arch_obj_models/csr_field.rb index 8ee73555e..a793ba088 100644 --- a/lib/arch_obj_models/csr_field.rb +++ b/lib/arch_obj_models/csr_field.rb @@ -174,7 +174,7 @@ def type(symtab) idl = @data["type()"] raise "type() is nil for #{csr.name}.#{name} #{@data}?" if idl.nil? - + # value_result = Idl::AstNode.value_try do ast = type_checked_type_ast(symtab) @@ -786,4 +786,4 @@ def location_pretty(arch_def, effective_xlen = nil) def type_desc(arch_def) TYPE_DESC_MAP[type(arch_def.symtab)] end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/extension.rb b/lib/arch_obj_models/extension.rb index b40aff3c5..1d978c39b 100644 --- a/lib/arch_obj_models/extension.rb +++ b/lib/arch_obj_models/extension.rb @@ -77,7 +77,7 @@ def name_potentially_with_link(exts) if exts.size == 1 "<>" - else + else "#{name}" end end @@ -462,7 +462,7 @@ def initialize(data) data.each do |key, value| if key == "optional" raise ArgumentError, "Extension presence hash #{data} missing type of optional" if value.nil? - raise ArgumentError, "Unknown extension presence optional #{value} for type of optional" unless + raise ArgumentError, "Unknown extension presence optional #{value} for type of optional" unless ["localized", "development", "expansion", "transitory"].include?(value) @presence = key @@ -476,7 +476,7 @@ def initialize(data) end end - def mandatory? = (@presence == mandatory) + def mandatory? = (@presence == mandatory) def optional? = (@presence == optional) # Class methods diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb index 8daaa54be..ee347bb4b 100644 --- a/lib/arch_obj_models/instruction.rb +++ b/lib/arch_obj_models/instruction.rb @@ -259,7 +259,7 @@ def size @range.size end end - + # decode field constructions from YAML file, rather than riscv-opcodes # eventually, we will move so that all instructions use the YAML file, class DecodeVariable @@ -524,7 +524,7 @@ def initialize(format, decode_vars) @format.chars.each_with_index do |c, idx| if c == "-" next if field_chars.empty? - + field_text = field_chars.join("") field_lsb = @format.size - idx field_msb = @format.size - idx - 1 + field_text.size diff --git a/lib/arch_obj_models/obj.rb b/lib/arch_obj_models/obj.rb index 215c4ec47..2e6b62176 100644 --- a/lib/arch_obj_models/obj.rb +++ b/lib/arch_obj_models/obj.rb @@ -68,7 +68,7 @@ def inspect # @return [Array] List of keys added by this ArchDefObject def keys = @data.keys - + # @param k (see Hash#key?) # @return (see Hash#key?) def key?(k) = @data.key?(k) @@ -106,7 +106,7 @@ def defined_by?(*args) end elsif args.size == 2 raise ArgumentError, "First parameter must be an extension name" unless args[0].respond_to?(:to_s) - version = args[1].is_a?(Gem::Version) ? args[1] : Gem::Version.new(args[1]) + version = args[1].is_a?(Gem::Version) ? args[1] : Gem::Version.new(args[1]) defined_by.satisfied_by? do |r| r.name == args[0] && r.version_requirement.satisfied_by?(version) @@ -365,7 +365,7 @@ def self.all_of(*conds) cond = SchemaCondition.new({ "allOf" => conds }) - + SchemaCondition.new(cond.minimize) end @@ -474,7 +474,7 @@ def satisfied_by?(&block) class AlwaysTrueSchemaCondition def to_rb = "true" - + def satisfied_by? = true def empty? = true diff --git a/lib/arch_obj_models/portfolio.rb b/lib/arch_obj_models/portfolio.rb index e378cdc01..3ad3306d5 100644 --- a/lib/arch_obj_models/portfolio.rb +++ b/lib/arch_obj_models/portfolio.rb @@ -2,7 +2,7 @@ # A "Portfolio" is a named & versioned grouping of extensions (each with a name and version). # Each Portfolio Instance is a member of a Portfolio Class: # RVA20U64 and MC100 are examples of portfolio instances -# RVA and MC are examples of portfolio classes +# RVA and MC are examples of portfolio classes # # Many classes inherit from the ArchDefObject class. This provides facilities for accessing the contents of a # Portfolio Class YAML or Portfolio Model YAML file via the "data" member (hash holding releated YAML file contents). @@ -76,7 +76,7 @@ def extension_presence(ext_name) # @return [Array] def version_strongest_presence(ext_name, ext_versions) presences = [] - + # See if any extension requirement in this profile lists this version as either mandatory or optional. ext_versions.map do |v| mandatory = mandatory_ext_reqs.any? { |ext_req| ext_req.satisfied_by?(ext_name, v.version) } @@ -113,8 +113,8 @@ def in_scope_ext_reqs(desired_presence = nil) in_scope_ext_reqs = [] # Convert desired_present argument to ExtensionPresence object if not nil. - desired_presence_converted = - desired_presence.nil? ? nil : + desired_presence_converted = + desired_presence.nil? ? nil : desired_presence.is_a?(String) ? desired_presence : desired_presence.is_a?(ExtensionPresence) ? desired_presence : ExtensionPresence.new(desired_presence) @@ -134,7 +134,7 @@ def in_scope_ext_reqs(desired_presence = nil) end if match - in_scope_ext_reqs << + in_scope_ext_reqs << ExtensionRequirement.new(ext_name, ext_data["version"], presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-" + ext_name) end @@ -253,7 +253,7 @@ def allowed_values # sorts by name def <=>(other) - raise ArgumentError, + raise ArgumentError, "InScopeExtensionParameter are only comparable to other parameter constraints" unless other.is_a?(InScopeExtensionParameter) @param.name <=> other.param.name end @@ -272,7 +272,7 @@ def all_in_scope_ext_params @all_in_scope_ext_params = [] - @data["extensions"].each do |ext_name, ext_data| + @data["extensions"].each do |ext_name, ext_data| # Find Extension object from database ext = @arch_def.extension(ext_name) raise "Cannot find extension named #{ext_name}" if ext.nil? @@ -286,7 +286,7 @@ def all_in_scope_ext_params param.defined_in_extension_version?(ext_ver.version) end - @all_in_scope_ext_params << + @all_in_scope_ext_params << InScopeExtensionParameter.new(param, param_data["schema"], param_data["note"]) end end @@ -303,7 +303,7 @@ def in_scope_ext_params(ext_req) # Get extension information from portfolio YAML for passed in extension requirement. ext_data = @data["extensions"][ext_req.name] raise "Cannot find extension named #{ext_req.name}" if ext_data.nil? - + # Find Extension object from database ext = @arch_def.extension(ext_req.name) raise "Cannot find extension named #{ext_req.name}" if ext.nil? @@ -330,7 +330,7 @@ def in_scope_ext_params(ext_req) # @return [Array] Parameters out of scope across all in scope extensions (those listed in the portfolio). def all_out_of_scope_params return @all_out_of_scope_params unless @all_out_of_scope_params.nil? - + @all_out_of_scope_params = [] in_scope_ext_reqs.each do |ext_req| ext = @arch_def.extension(ext_req.name) @@ -350,11 +350,11 @@ def all_out_of_scope_params # @return [Array] Parameters that are out of scope for named extension. def out_of_scope_params(ext_name) - all_out_of_scope_params.select{|param| param.exts.any? {|ext| ext.name == ext_name} } + all_out_of_scope_params.select{|param| param.exts.any? {|ext| ext.name == ext_name} } end # @return [Array] - # All the in-scope extensions (those in the portfolio) that define this parameter in the database + # All the in-scope extensions (those in the portfolio) that define this parameter in the database # and the parameter is in-scope (listed in that extension's list of parameters in the portfolio). def all_in_scope_exts_with_param(param) raise ArgumentError, "Expecting ExtensionParameter" unless param.is_a?(ExtensionParameter) @@ -383,7 +383,7 @@ def all_in_scope_exts_with_param(param) end # @return [Array] - # All the in-scope extensions (those in the portfolio) that define this parameter in the database + # All the in-scope extensions (those in the portfolio) that define this parameter in the database # but the parameter is out-of-scope (not listed in that extension's list of parameters in the portfolio). def all_in_scope_exts_without_param(param) raise ArgumentError, "Expecting ExtensionParameter" unless param.is_a?(ExtensionParameter) @@ -444,7 +444,7 @@ def revision_history class ExtraNote < ArchDefObject def initialize(data) - super(data) + super(data) @presence_obj = ExtensionPresence.new(@data["presence"]) end @@ -463,7 +463,7 @@ def extra_notes @extra_notes end - # @param desired_presence [ExtensionPresence] + # @param desired_presence [ExtensionPresence] # @return [String] Note for desired_presence # @return [nil] No note for desired_presence def extra_notes_for_presence(desired_presence_obj) @@ -493,4 +493,4 @@ def recommendations end @recommendations end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/profile.rb b/lib/arch_obj_models/profile.rb index 44d63f3b4..c63be19a2 100644 --- a/lib/arch_obj_models/profile.rb +++ b/lib/arch_obj_models/profile.rb @@ -231,7 +231,7 @@ def ext_req_to_adoc(ext_req) # @return [Array] def ext_note_to_adoc(ext_name) ret = [] - + unless extension_note(ext_name).nil? ret << "+" ret << "[NOTE]" @@ -239,7 +239,7 @@ def ext_note_to_adoc(ext_name) ret << extension_note(ext_name) ret << "--" end - + ret end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/schema.rb b/lib/arch_obj_models/schema.rb index c5cbbc998..041e1da7c 100644 --- a/lib/arch_obj_models/schema.rb +++ b/lib/arch_obj_models/schema.rb @@ -6,7 +6,7 @@ # # Used when an object in the database specifies a constraint using JSON schema # For example, extension parameters -class Schema +class Schema def initialize(schema_hash) raise ArgumentError, "Expecting hash" unless schema_hash.is_a?(Hash) @@ -77,9 +77,9 @@ def to_pretty_s(schema_hash = @schema_hash) "" end - array_str = if items.nil? + array_str = if items.nil? size_str + "array" - else + else if items.is_a?(Hash) "#{size_str}array of #{to_pretty_s(items)}" elsif items.is_a?(Array) @@ -89,7 +89,7 @@ def to_pretty_s(schema_hash = @schema_hash) end additional_items = schema_hash["additionalItems"] if additional_items - str = str + "additional items are: +\n  " + + str = str + "additional items are: +\n  " + to_pretty_s(additional_items) end str @@ -161,4 +161,3 @@ def to_idl_type Idl::Type.from_json_schema(@schema_hash) end end - diff --git a/lib/asciidoc_extensions.js b/lib/asciidoc_extensions.js index 7da2f377b..91520a803 100644 --- a/lib/asciidoc_extensions.js +++ b/lib/asciidoc_extensions.js @@ -1,3 +1,3 @@ const asciidoctor = require('asciidoctor')() const registry = asciidoctor.Extensions.create() -require('./asciidoc_when_extension.js')(registry) \ No newline at end of file +require('./asciidoc_when_extension.js')(registry) diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index e113b0ee1..7059b9be2 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -1266,7 +1266,7 @@ def freeze_tree(global_symtab) type(global_symtab) freeze end - + # @return [Integer] The number of bits in the Bitfield def size(symtab) @size.value(symtab) @@ -1834,7 +1834,7 @@ def execute_unknown(symtab) end when :bits var = symtab.get(lhs.text_value) - value_result = value_try do + value_result = value_try do v = rhs.value(symtab) var.value = (lhs.value & ~0) | ((v & 1) << idx.value(symtab)) end @@ -2559,7 +2559,7 @@ def to_ast # # This will result in a BitsCaseAst: # - # $bits(ExceptionCode::LoadAccessFault) + # $bits(ExceptionCode::LoadAccessFault) class BitsCastAst < AstNode include Rvalue @@ -2826,7 +2826,7 @@ def value(symtab) # cached_value = @value_cache[symtab] # return cached_value unless cached_value.nil? - value = + value = if op == ">>>" lhs_value = lhs.value(symtab) if lhs_value & (1 << (lhs.type(symtab).width - 1)).zero? @@ -2995,7 +2995,7 @@ def value(symtab) else v end - + warn "WARNING: The value of '#{text_value}' (#{lhs.type(symtab).const?}, #{rhs.type(symtab).const?}) is truncated from #{v} to #{v_trunc} because the result is only #{type(symtab).width} bits" if v != v_trunc v_trunc end @@ -3445,7 +3445,7 @@ def freeze_tree(global_symtab) # @!macro type_check def type_check(symtab) enum_def_type = @enum_def_type - + type_error "No symbol #{@enum_class_name} has been defined" if enum_def_type.nil? type_error "#{@enum_class_name} is not an enum type" unless enum_def_type.is_a?(EnumerationType) @@ -4526,7 +4526,7 @@ def template_arg_nodes def template_values(symtab, unknown_ok: false) return EMPTY_ARRAY unless template? - if unknown_ok + if unknown_ok template_arg_nodes.map do |e| val = nil value_result = value_try do @@ -4954,7 +4954,7 @@ def return_type(symtab) rtype = rtype.ref_type if rtype.kind == :enum rtype end - + Type.new(:tuple, tuple_types:) end diff --git a/lib/idl/idl.treetop b/lib/idl/idl.treetop index a054cb2d5..43e9dae44 100644 --- a/lib/idl/idl.treetop +++ b/lib/idl/idl.treetop @@ -15,7 +15,7 @@ grammar Idl struct_definition / function_definition - / + / space+ )+ end @@ -298,7 +298,7 @@ grammar Idl / concatenation_expression / - field_access_expression + field_access_expression / function_call # Ast is assigned in function_call rule / diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index fdf2c4306..21ddb8be1 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -301,7 +301,7 @@ def gen_adoc(indent = 0, indent_spaces: 2) if idx_text =~ /[0-9]+/ "#{' '*indent}#{csr_text}" else - if @archdef.csr(csr_text).nil? + if @archdef.csr(csr_text).nil? "#{' '*indent}#{csr_text}" else "#{' '*indent}%%LINK%csr_field;#{idx_text}.#{@field_name};#{csr_text}%%" diff --git a/lib/idl/passes/gen_option_adoc.rb b/lib/idl/passes/gen_option_adoc.rb index 5557dfc44..059530ce7 100644 --- a/lib/idl/passes/gen_option_adoc.rb +++ b/lib/idl/passes/gen_option_adoc.rb @@ -26,7 +26,7 @@ def gen_option_adoc class IfAst def gen_option_adoc - adoc = + adoc = <<~ADOC [when,"#{if_cond.to_idl}"] #{if_body.gen_option_adoc} diff --git a/lib/idl/passes/reachable_functions.rb b/lib/idl/passes/reachable_functions.rb index 2c9472bab..ca4379501 100644 --- a/lib/idl/passes/reachable_functions.rb +++ b/lib/idl/passes/reachable_functions.rb @@ -146,7 +146,7 @@ def reachable_functions(symtab) # condition not known fns = fns.concat action.reachable_functions(symtab) if action.is_a?(FunctionCallExpressionAst) end - + fns end end diff --git a/lib/idl/symbol_table.rb b/lib/idl/symbol_table.rb index 1fe9a3fe8..f78acd9a2 100644 --- a/lib/idl/symbol_table.rb +++ b/lib/idl/symbol_table.rb @@ -196,7 +196,7 @@ def deep_freeze # set up the global clone that be used as a mutable table @global_clone_pool = [] - 5.times do + 5.times do copy = SymbolTable.allocate copy.instance_variable_set(:@scopes, [@scopes[0]]) copy.instance_variable_set(:@callstack, [@callstack[0]]) @@ -335,7 +335,7 @@ def add_at!(level, name, var) raise "Level #{level} is too large #{@scopes.size}" if level >= @scopes.size raise "Symbol #{name} already defined" unless @scopes[0...level].select { |h| h.key? name }.empty? - + @scopes[level][name] = var end diff --git a/lib/idl/tests/helpers.rb b/lib/idl/tests/helpers.rb index ca26eb4ab..8ef30e6c0 100644 --- a/lib/idl/tests/helpers.rb +++ b/lib/idl/tests/helpers.rb @@ -39,4 +39,4 @@ def setup @symtab = Idl::SymbolTable.new(@archdef, 32) @compiler = Idl::Compiler.new(@archdef) end -end \ No newline at end of file +end diff --git a/lib/idl/tests/test_lexer.rb b/lib/idl/tests/test_lexer.rb index b69cfc8bf..a279b6cde 100644 --- a/lib/idl/tests/test_lexer.rb +++ b/lib/idl/tests/test_lexer.rb @@ -24,11 +24,11 @@ def test_function } XReg index = shamt & (xlen() - 1); FUNC - + tokens.each do |token, chunk| puts token puts chunk end end -end \ No newline at end of file +end diff --git a/lib/resolver.rb b/lib/resolver.rb index 2427ff5b9..494d7c9f5 100644 --- a/lib/resolver.rb +++ b/lib/resolver.rb @@ -17,4 +17,4 @@ def resolve(input_file, output_file) obj = YamlLoader.load(input_file, permitted_classes: [Date]) File.write(output_file, YAML::dump(obj)) end -end \ No newline at end of file +end diff --git a/lib/test/test_yaml_loader.rb b/lib/test/test_yaml_loader.rb index 562d93d41..c7285fa44 100644 --- a/lib/test/test_yaml_loader.rb +++ b/lib/test/test_yaml_loader.rb @@ -42,7 +42,7 @@ def test_multiple_remove - key3 key4: value4 YAML - + f = Tempfile.new("yml") f.write(yaml) f.flush @@ -346,10 +346,10 @@ def test_copy_in_the_same_document obj1: target10: abc - target11: + target11: $copy: "#/$defs/target1" target12: def - target13: + target13: $copy: "#/$defs/target3" YAML @@ -359,11 +359,11 @@ def test_copy_in_the_same_document f.flush doc = YamlLoader.load(f.path) - assert_equal({ - "target10" => "abc", - "target11" => "A string", - "target12" => "def", - "target13" => "Another string" + assert_equal({ + "target10" => "abc", + "target11" => "A string", + "target12" => "def", + "target13" => "Another string" }, doc["obj1"]) end @@ -384,10 +384,10 @@ def test_copy_in_the_different_document yaml2 = <<~YAML obj1: target10: abc - target11: + target11: $copy: "#{f1_path.basename}#/$defs/target1" target12: def - target13: + target13: $copy: "#{f1_path.basename}#/$defs/target3" YAML @@ -396,11 +396,11 @@ def test_copy_in_the_different_document f2.flush doc = YamlLoader.load(f2.path) - assert_equal({ - "target10" => "abc", - "target11" => "A string", - "target12" => "def", - "target13" => "Another string" + assert_equal({ + "target10" => "abc", + "target11" => "A string", + "target12" => "def", + "target13" => "Another string" }, doc["obj1"]) end diff --git a/lib/validate.rb b/lib/validate.rb index c2215b433..3375922d2 100644 --- a/lib/validate.rb +++ b/lib/validate.rb @@ -245,7 +245,7 @@ def validate_instruction_encoding(inst_name, encoding) vars_match = variables.count { |variable| ary_from_location(variable["location"]).include?(i) } if vars_match.zero? raise ValidationError, "In instruction #{inst_name}, no variable or encoding bit covers bit #{i}" - elsif vars_match != 1 + elsif vars_match != 1 raise ValidationError, "In instruction, #{inst_name}, bit #{i} is covered by more than one variable" end else diff --git a/lib/yaml_loader.rb b/lib/yaml_loader.rb index 06f994865..691ab45f3 100644 --- a/lib/yaml_loader.rb +++ b/lib/yaml_loader.rb @@ -48,7 +48,7 @@ def self.expand(filename, obj, yaml_opts = {}) obj_doc else obj_doc.dig(*(obj_path.split("/")[1..])) - + end raise "#{obj['$ref']} cannot be found" if target_obj.nil? @@ -92,7 +92,7 @@ def self.expand(filename, obj, yaml_opts = {}) inherits_target_suffix = inherits_target.split("#/")[1] inherits_target_path = inherits_target_suffix.split("/") begin - target_obj = target_obj.dig(*inherits_target_path) + target_obj = target_obj.dig(*inherits_target_path) rescue TypeError => e if e.message == "no implicit conversion of String into Integer" warn "$inherits: \"#{inherits_target}\" found in file #{filename} references an Array but needs to reference a Hash" diff --git a/lib/yaml_resolver.py b/lib/yaml_resolver.py index 47e6c87f3..3b9b1ab5c 100644 --- a/lib/yaml_resolver.py +++ b/lib/yaml_resolver.py @@ -34,7 +34,7 @@ def dig(obj, *keys): return dig(next_obj, *keys[1:]) except KeyError: return None - + resolved_objs = {} def resolve(path, rel_path, arch_root): if path in resolved_objs: diff --git a/schemas/cert_class_schema.json b/schemas/cert_class_schema.json index d7f7ff80c..c7cd83438 100644 --- a/schemas/cert_class_schema.json +++ b/schemas/cert_class_schema.json @@ -44,4 +44,4 @@ "$ref": "schema_defs.json#/$defs/__source" } } -} \ No newline at end of file +} diff --git a/schemas/cert_model_schema.json b/schemas/cert_model_schema.json index b20551445..65d514106 100644 --- a/schemas/cert_model_schema.json +++ b/schemas/cert_model_schema.json @@ -196,4 +196,4 @@ "$ref": "schema_defs.json#/$defs/__source" } } -} \ No newline at end of file +} diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 16ef9686c..78ee09fee 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -193,7 +193,7 @@ "description": "Descriptive name for the CSR" }, "description": { - "oneOf": [ + "oneOf": [ { "type": "string", "description": "A full Asciidoc description of the CSR, intended to be used as documentation." diff --git a/schemas/ext_schema.json b/schemas/ext_schema.json index 724e93128..79c38d4b4 100644 --- a/schemas/ext_schema.json +++ b/schemas/ext_schema.json @@ -145,9 +145,9 @@ "additionalProperties": false } }, - "ratification_date": { + "ratification_date": { "oneOf": [ - {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", + {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", "description": "A specific year and month in YYYY-MM format", "examples": ["2019-01", "2024-12"] }, {"type": "string", "pattern": "^unknown$", "$comment": "When ratification date is unknown" }, {"type": "null", "$comment": "When version isn't ratified" } @@ -289,4 +289,4 @@ }, "$ref": "#/$defs/ext_data" -} \ No newline at end of file +} diff --git a/schemas/manual_version_schema.json b/schemas/manual_version_schema.json index 9557413ff..e6b6320d5 100644 --- a/schemas/manual_version_schema.json +++ b/schemas/manual_version_schema.json @@ -95,4 +95,4 @@ } }, "additionalProperties": false -} \ No newline at end of file +} diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 1b954ba32..86d57b404 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -226,4 +226,4 @@ } } } -} \ No newline at end of file +}