diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index 9c20d5344..e3fd23d18 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -35,7 +35,5 @@ ] } }, - "forwardPorts": [ - 8000, 8080 - ] + "forwardPorts": [8000, 8080] } diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index 084687ad4..73c2dfd92 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -2,7 +2,7 @@ name: Regression test on: schedule: - - cron: '30 2 * * *' + - cron: "30 2 * * *" workflow_dispatch: jobs: @@ -27,28 +27,28 @@ jobs: if: ${{ needs.check_date.outputs.should_run != 'false' }} runs-on: ubuntu-latest steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Setup project - run: ./bin/setup - - name: Run regression - run: ./do test:nightly + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Run regression + run: ./do test:nightly diff --git a/.github/workflows/pages.yml b/.github/workflows/pages.yml index 37213d4ca..fd5001665 100644 --- a/.github/workflows/pages.yml +++ b/.github/workflows/pages.yml @@ -2,7 +2,7 @@ name: Deploy pages on: push: branches: - - main + - main workflow_dispatch: permissions: contents: read @@ -18,73 +18,73 @@ jobs: name: github-pages url: ${{ steps.deployment.outputs.page_url }} steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Setup project - run: ./bin/setup - - name: Build manual - run: ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all - - name: Build html documentation for generic_rv64 - run: ./do gen:html[generic_rv64] - - name: Generate YARD docs - run: ./do gen:tool_doc - - name: Create _site/example_cfg - run: mkdir -p _site/example_cfg - - name: Create _site/manual - run: mkdir -p _site/manual - - name: Create _site/pdfs - run: mkdir -p _site/pdfs - - name: Create _site/htmls - run: mkdir -p _site/htmls - - name: Copy cfg html - run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg - - name: Create RVA20 Profile Release PDF Spec - run: ./do gen:profile[RVA20] - - name: Copy RVA20 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVA20.pdf - - name: Create RVA22 Profile Release PDF Spec - run: ./do gen:profile[RVA22] - - name: Copy RVA22 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA22.pdf _site/pdfs/RVA22.pdf - - name: Create RVI20 Profile Release PDF Spec - run: ./do gen:profile[RVI20] - - name: Copy RVI20 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVI20.pdf - - name: Create MC100 PDF Spec - run: ./do gen:cert_model_pdf[MC100] - - name: Copy MC100 PDF - run: cp gen/certificate_doc/pdf/MC100.pdf _site/pdfs/MC100.pdf - - name: Create MC100 HTML Spec - run: ./do gen:cert_model_html[MC100] - - name: Copy MC100 HTML - run: cp gen/certificate_doc/html/MC100.html _site/htmls/MC100.html - - name: Copy manual html - run: cp -R gen/manual/isa/top/all/html _site/manual - - name: Setup Pages - uses: actions/configure-pages@v5 - - name: Upload artifact - uses: actions/upload-pages-artifact@v3 - with: - path: '_site' - - name: Deploy to GitHub Pages - id: deployment - uses: actions/deploy-pages@v4 + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Build manual + run: ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all + - name: Build html documentation for generic_rv64 + run: ./do gen:html[generic_rv64] + - name: Generate YARD docs + run: ./do gen:tool_doc + - name: Create _site/example_cfg + run: mkdir -p _site/example_cfg + - name: Create _site/manual + run: mkdir -p _site/manual + - name: Create _site/pdfs + run: mkdir -p _site/pdfs + - name: Create _site/htmls + run: mkdir -p _site/htmls + - name: Copy cfg html + run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg + - name: Create RVA20 Profile Release PDF Spec + run: ./do gen:profile[RVA20] + - name: Copy RVA20 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVA20.pdf + - name: Create RVA22 Profile Release PDF Spec + run: ./do gen:profile[RVA22] + - name: Copy RVA22 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA22.pdf _site/pdfs/RVA22.pdf + - name: Create RVI20 Profile Release PDF Spec + run: ./do gen:profile[RVI20] + - name: Copy RVI20 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVI20.pdf + - name: Create MC100 PDF Spec + run: ./do gen:cert_model_pdf[MC100] + - name: Copy MC100 PDF + run: cp gen/certificate_doc/pdf/MC100.pdf _site/pdfs/MC100.pdf + - name: Create MC100 HTML Spec + run: ./do gen:cert_model_html[MC100] + - name: Copy MC100 HTML + run: cp gen/certificate_doc/html/MC100.html _site/htmls/MC100.html + - name: Copy manual html + run: cp -R gen/manual/isa/top/all/html _site/manual + - name: Setup Pages + uses: actions/configure-pages@v5 + - name: Upload artifact + uses: actions/upload-pages-artifact@v3 + with: + path: "_site" + - name: Deploy to GitHub Pages + id: deployment + uses: actions/deploy-pages@v4 diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index 9f3fa519c..e089c74fe 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -2,7 +2,7 @@ name: Regression test on: pull_request: branches: - - main + - main workflow_dispatch: jobs: regress-smoke: @@ -31,119 +31,5 @@ jobs: run: ./bin/build_container - name: Setup project run: ./bin/setup - - name: Run smoke - run: ./do test:smoke - regress-gen-isa-manual: - runs-on: ubuntu-latest - needs: regress-smoke - env: - MANUAL_NAME: isa - VERSIONS: all - steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate HTML ISA manual - run: ./do gen:html_manual - regress-gen-ext-pdf: - runs-on: ubuntu-latest - needs: regress-smoke - env: - EXT: B - VERSION: latest - steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:ext_pdf - regress-gen-certificate: - runs-on: ubuntu-latest - needs: regress-smoke - steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:cert_model_pdf[MockCertificateModel] - regress-gen-profile: - runs-on: ubuntu-latest - needs: regress-smoke - steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:profile[MockProfileRelease] + - name: Run regression + run: ./do regress diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 3063481e8..2b5bca32e 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,5 +1,5 @@ --- -exclude: ^docs/ruby/ # All generated code +exclude: ^docs/ruby/ repos: - repo: https://github.com/pre-commit/pre-commit-hooks @@ -9,6 +9,41 @@ repos: - id: end-of-file-fixer - id: trailing-whitespace args: [--markdown-linebreak-ext=md] - - id: check-merge-conflict - args: ["--assume-in-merge"] - exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise + - id: check-json + exclude: ^\.devcontainer/ # Uses JSONC (comments) + - id: check-yaml + + - repo: https://github.com/rbubley/mirrors-prettier + rev: v3.3.3 + hooks: + - id: prettier + files: \.(json|yml|yaml)$ + + - repo: https://github.com/python-jsonschema/check-jsonschema + rev: 0.29.4 + hooks: + - id: check-jsonschema + alias: check-jsonschema-inst + files: ^arch/inst/.*\.(yaml|yml)$ + args: ["--schemafile", "schemas/inst_schema.json"] + - id: check-jsonschema + alias: check-jsonschema-csr + files: ^arch/csr/.*\.(yaml|yml)$ + args: ["--schemafile", "schemas/csr_schema.json"] + - id: check-jsonschema + alias: check-jsonschema-ext + files: ^arch/ext/.*\.(yaml|yml)$ + args: ["--schemafile", "schemas/ext_schema.json"] + - id: check-jsonschema + alias: check-jsonschema-cert-model + files: ^arch/certificate_model/.*\.(yaml|yml)$ + args: ["--schemafile", "schemas/cert_model_schema.json"] + - id: check-jsonschema + alias: check-jsonschema-cert-class + files: ^arch/certificate_class/.*\.(yaml|yml)$ + args: ["--schemafile", "schemas/cert_class_schema.json"] + # Commenting because throwing errors and not sure this is complete yet + # - id: check-jsonschema + # alias: check-jsonschema-manual-version + # files: ^arch/manual/.*\.(yaml|yml)$ + # args: ["--schemafile", "schemas/manual_version_schema.json"] diff --git a/.solargraph.yml b/.solargraph.yml index ecddf8a95..864b4acc8 100644 --- a/.solargraph.yml +++ b/.solargraph.yml @@ -1,17 +1,17 @@ --- include: -- "lib/**/*.rb" -- "tasks/**/*.rake" + - "lib/**/*.rb" + - "tasks/**/*.rake" exclude: -- spec/**/* -- test/**/* -- vendor/**/* -- ".home/**/*" + - spec/**/* + - test/**/* + - vendor/**/* + - ".home/**/*" require: [] domains: [] reporters: -- rubocop -- require_not_found + - rubocop + - require_not_found formatter: rubocop: cops: safe @@ -19,6 +19,6 @@ formatter: only: [] extra_args: [] require_paths: -- /usr/lib/ruby/3.2.0 + - /usr/lib/ruby/3.2.0 plugins: [] max_files: 5000 diff --git a/arch/certificate_class/MC.yaml b/arch/certificate_class/MC.yaml index d31c7a25f..5650ea203 100644 --- a/arch/certificate_class/MC.yaml +++ b/arch/certificate_class/MC.yaml @@ -35,4 +35,4 @@ naming_scheme: | ** A release indicates just CRD specification changes without any difference in functional behavior mandatory_priv_modes: -- M + - M diff --git a/arch/certificate_class/MockCertificateClass.yaml b/arch/certificate_class/MockCertificateClass.yaml index eebbbbbac..4dc404972 100644 --- a/arch/certificate_class/MockCertificateClass.yaml +++ b/arch/certificate_class/MockCertificateClass.yaml @@ -13,4 +13,4 @@ naming_scheme: | A Mock certificate class or model can have any name as long as it can be a hash key. mandatory_priv_modes: -- M + - M diff --git a/arch/certificate_model/MC100.yaml b/arch/certificate_model/MC100.yaml index 4589f965f..4fdad7097 100644 --- a/arch/certificate_model/MC100.yaml +++ b/arch/certificate_model/MC100.yaml @@ -9,63 +9,63 @@ class: # Semantic versions within the model versions: -- version: "1.0.0" + - version: "1.0.0" # XLEN used by rakefile base: 32 revision_history: -- revision: "0.7.0" - date: 2024-07-29 - changes: - - First version after moving non-microcontroller content in this document to a new document - called "RISC-V CRDs (Certification Requirement Documents)" - - Change MC100 Unpriv ISA spec from - "https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31, - 2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the - former isn't ratified by the latter is the oldest ratified version. - - Added requirements for WFI instruction - - Added requirements related to msip memory-mapped register -- revision: "0.6.0" - date: 2024-07-11 - changes: - - Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards. - - Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor. - - Added a table showing the mapping from MC version to ISA manuals. - - Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller - was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations. - - Clarified MANDATORY behaviors for mie and mip CSRs - - Removed canonical discovery recipe because the OPT-* options directly inform the certification - tests and certification reference model of the status of the various options. Also, canonical - discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing - potentially illegal values to CSR fields. - - Added more options for interrupts - - Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans" -- revision: "0.5.0" - date: 2024-06-03 - changes: - - Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation - - Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out - these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet). - - Added table showing mapping of MC versions to associated RISC-V specifications -- revision: "0.4.0" - date: 2024-06-03 - changes: - - Added M-mode instruction requirements - - Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options). - - Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant. -- revision: "0.3.0" - date: 2024-05-25 - changes: - - Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle. -- revision: "0.2.0" - date: 2024-05-20 - changes: - - Very early draft -- revision: "0.1.0" - date: 2024-05-16 - changes: - - Initial version + - revision: "0.7.0" + date: 2024-07-29 + changes: + - First version after moving non-microcontroller content in this document to a new document + called "RISC-V CRDs (Certification Requirement Documents)" + - Change MC100 Unpriv ISA spec from + "https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31, + 2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the + former isn't ratified by the latter is the oldest ratified version. + - Added requirements for WFI instruction + - Added requirements related to msip memory-mapped register + - revision: "0.6.0" + date: 2024-07-11 + changes: + - Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards. + - Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor. + - Added a table showing the mapping from MC version to ISA manuals. + - Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller + was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations. + - Clarified MANDATORY behaviors for mie and mip CSRs + - Removed canonical discovery recipe because the OPT-* options directly inform the certification + tests and certification reference model of the status of the various options. Also, canonical + discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing + potentially illegal values to CSR fields. + - Added more options for interrupts + - Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans" + - revision: "0.5.0" + date: 2024-06-03 + changes: + - Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation + - Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out + these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet). + - Added table showing mapping of MC versions to associated RISC-V specifications + - revision: "0.4.0" + date: 2024-06-03 + changes: + - Added M-mode instruction requirements + - Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options). + - Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant. + - revision: "0.3.0" + date: 2024-05-25 + changes: + - Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle. + - revision: "0.2.0" + date: 2024-05-20 + changes: + - Very early draft + - revision: "0.1.0" + date: 2024-05-16 + changes: + - Initial version description: | MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support: @@ -104,39 +104,39 @@ extensions: version: "~> 2.0" presence: mandatory parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained + TIME_CSR_IMPLEMENTED: {} # Unconstrained Sm: version: "~> 1.11.0" presence: mandatory parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: {} # Unconstrained - PHYS_ADDR_WIDTH: {} # Unconstrained - MISALIGNED_LDST: {} # Unconstrained - MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained - MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained - MISALIGNED_SPLIT_STRATEGY: - schema: - const: by_byte - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - XLEN: - schema: - const: 32 + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: {} # Unconstrained + PHYS_ADDR_WIDTH: {} # Unconstrained + MISALIGNED_LDST: {} # Unconstrained + MISALIGNED_LDST_EXCEPTION_PRIORITY: {} # Unconstrained + MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained + MISALIGNED_SPLIT_STRATEGY: + schema: + const: by_byte + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + XLEN: + schema: + const: 32 diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index 188a05b82..951c892ee 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -16,14 +16,14 @@ versions: - version: "1.1.0" revision_history: -- revision: "0.1.0" - date: 2024-10-04 - changes: - - Created to test CRDs -- revision: "0.2.0" - date: 2024-10-05 - changes: - - Also created to test CRDs + - revision: "0.1.0" + date: 2024-10-04 + changes: + - Created to test CRDs + - revision: "0.2.0" + date: 2024-10-05 + changes: + - Also created to test CRDs description: | Mock CRD description: @@ -40,8 +40,8 @@ debug_manual_revision: "0.13.2" # XXX - Remove version information since specifying priv/unpriv ISA manual should imply this. extensions: $inherits: - - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" - - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" + - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" + - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" I: note: Just added this note to I extension MockExt: @@ -70,17 +70,17 @@ extensions: MOCK_ARRAY_BOOL_ARRAY_OF_8_FIRST_2_FALSE: {} MOCK_ARRAY_STRING_ENUM1: schema: - const : DEF + const: DEF MOCK_ARRAY_STRING_ENUM2: schema: - contains: { const : DEF } + contains: { const: DEF } C: version: "~> 2.2" presence: mandatory parameters: - MUTABLE_MISA_C: - schema: - const: false + MUTABLE_MISA_C: + schema: + const: false note: | Here's a multi-line note + for the C extension. @@ -91,68 +91,68 @@ extensions: version: "~> 2.0" presence: mandatory parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained + TIME_CSR_IMPLEMENTED: {} # Unconstrained Sm: version: "~> 1.11" presence: mandatory parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: - note: Here's a note for MTVEC_MODES parameter. - schema: - contains: { const : 0 } - PHYS_ADDR_WIDTH: {} # Unconstrained - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_BREAKPOINT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: - schema: - const: true - REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - # Uncomment when GitHub issue # is fixed. - #schema: - #- when: - # version: "=1.0.0" - # then: - # const: little - #- when: - # version: "=1.1.0" - # then: - # enum: [little, big] - XLEN: - schema: - const: 64 - CONFIG_PTR_ADDRESS: - schema: - const: 0xdeadbeef - note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: + note: Here's a note for MTVEC_MODES parameter. + schema: + contains: { const: 0 } + PHYS_ADDR_WIDTH: {} # Unconstrained + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_BREAKPOINT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: + schema: + const: true + REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + # Uncomment when GitHub issue # is fixed. + #schema: + #- when: + # version: "=1.0.0" + # then: + # const: little + #- when: + # version: "=1.1.0" + # then: + # enum: [little, big] + XLEN: + schema: + const: 64 + CONFIG_PTR_ADDRESS: + schema: + const: 0xdeadbeef + note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." Zifencei: presence: optional note: "Here's a note for Zifencei" @@ -160,16 +160,16 @@ extensions: presence: optional note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbom." parameters: - CACHE_BLOCK_SIZE: - schema: - const: 64 + CACHE_BLOCK_SIZE: + schema: + const: 64 Zicbom: presence: optional note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbop." parameters: - CACHE_BLOCK_SIZE: - schema: - const: 64 + CACHE_BLOCK_SIZE: + schema: + const: 64 Zba: presence: mandatory version: "~> 1.0" @@ -188,10 +188,10 @@ requirement_groups: description: | A bunch of additional requirements not associated with an extension. requirements: - - name: REQ-ANY-XLEN-001 - description: Must pay your taxes on time - - name: REQ-ANY-XLEN-002 - description: Don't count your chickens before they're hatched! + - name: REQ-ANY-XLEN-001 + description: Must pay your taxes on time + - name: REQ-ANY-XLEN-002 + description: Don't count your chickens before they're hatched! - name: Req-Grp-XLEN32 when: @@ -199,8 +199,8 @@ requirement_groups: description: | A bunch of additional requirements only that should show up for XLEN=32 requirements: - - name: REQ-XLEN32-001 - description: Need lots of extra CSRs with `h` suffix + - name: REQ-XLEN32-001 + description: Need lots of extra CSRs with `h` suffix - name: Req-Grp-XLEN64 when: @@ -208,19 +208,19 @@ requirement_groups: description: | A bunch of additional requirements only that should show up for XLEN=64 requirements: - - name: REQ-XLEN64-001 - description: Can avoid adding extra CSRs with `h` suffix + - name: REQ-XLEN64-001 + description: Can avoid adding extra CSRs with `h` suffix extra_notes: -- presence: optional - text: Here's the first extra note for the optional extensions section. -- presence: mandatory - text: | - Here's the first extra note for the mandatory extensions section. - This note is multiple lines. -- presence: optional - text: Here's the second extra note for the optional extensions section. + - presence: optional + text: Here's the first extra note for the optional extensions section. + - presence: mandatory + text: | + Here's the first extra note for the mandatory extensions section. + This note is multiple lines. + - presence: optional + text: Here's the second extra note for the optional extensions section. recommendations: -- text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. -- text: Micky should give Pluto an extra treat + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + - text: Micky should give Pluto an extra treat diff --git a/arch/common/inst_variable_types.yaml b/arch/common/inst_variable_types.yaml index 359523020..7824ae5ac 100644 --- a/arch/common/inst_variable_types.yaml +++ b/arch/common/inst_variable_types.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../schemas/inst_variable_metadatas.json --- - itype_imm: location: 31-20 diff --git a/arch/csr/H/hcounteren.yaml b/arch/csr/H/hcounteren.yaml index 7623bce73..46b2f2f1b 100644 --- a/arch/csr/H/hcounteren.yaml +++ b/arch/csr/H/hcounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/H/hcounteren.layout - $schema: csr_schema.json# kind: csr name: hcounteren diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 43a84b54a..034b1d017 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -198,7 +198,7 @@ fields: location_rv32: 21-0 location_rv64: 43-0 description: | - The physical page number (PPN) of the guest-physical root page table. + The physical page number (PPN) of the guest-physical root page table. type(): | if (!SV32X4_TRANSLATION && !SV39X4_TRANSLATION && !SV48X4_TRANSLATION && !SV57X4_TRANSLATION) { # Bare is the only supported mode, PPN is always 0 diff --git a/arch/csr/I/mcounteren.yaml b/arch/csr/I/mcounteren.yaml index eb904c454..23c4a4865 100644 --- a/arch/csr/I/mcounteren.yaml +++ b/arch/csr/I/mcounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/mcounteren.layout - $schema: csr_schema.json# kind: csr name: mcounteren @@ -84,7 +83,6 @@ description: | . <%- end -%> - definedBy: U # actually, defined by RV64, but must implement U-mode for this CSR to exist fields: CY: diff --git a/arch/csr/I/pmpaddr0.yaml b/arch/csr/I/pmpaddr0.yaml index 22ef1b493..250d438c0 100644 --- a/arch/csr/I/pmpaddr0.yaml +++ b/arch/csr/I/pmpaddr0.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr0 diff --git a/arch/csr/I/pmpaddr1.yaml b/arch/csr/I/pmpaddr1.yaml index 1c5ccf42b..5e24bf677 100644 --- a/arch/csr/I/pmpaddr1.yaml +++ b/arch/csr/I/pmpaddr1.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr1 diff --git a/arch/csr/I/pmpaddr10.yaml b/arch/csr/I/pmpaddr10.yaml index 55fc27da3..a7da04a4b 100644 --- a/arch/csr/I/pmpaddr10.yaml +++ b/arch/csr/I/pmpaddr10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr10 diff --git a/arch/csr/I/pmpaddr11.yaml b/arch/csr/I/pmpaddr11.yaml index deca16c14..a8ccd0b6b 100644 --- a/arch/csr/I/pmpaddr11.yaml +++ b/arch/csr/I/pmpaddr11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr11 diff --git a/arch/csr/I/pmpaddr12.yaml b/arch/csr/I/pmpaddr12.yaml index bc4a1a004..10f1f2efe 100644 --- a/arch/csr/I/pmpaddr12.yaml +++ b/arch/csr/I/pmpaddr12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr12 diff --git a/arch/csr/I/pmpaddr13.yaml b/arch/csr/I/pmpaddr13.yaml index 99b51637a..99d40a093 100644 --- a/arch/csr/I/pmpaddr13.yaml +++ b/arch/csr/I/pmpaddr13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr13 diff --git a/arch/csr/I/pmpaddr14.yaml b/arch/csr/I/pmpaddr14.yaml index 0223aa2ab..cda0e1265 100644 --- a/arch/csr/I/pmpaddr14.yaml +++ b/arch/csr/I/pmpaddr14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr14 diff --git a/arch/csr/I/pmpaddr15.yaml b/arch/csr/I/pmpaddr15.yaml index 546579465..1cb123271 100644 --- a/arch/csr/I/pmpaddr15.yaml +++ b/arch/csr/I/pmpaddr15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr15 diff --git a/arch/csr/I/pmpaddr16.yaml b/arch/csr/I/pmpaddr16.yaml index 8c4a403d8..d766d82fa 100644 --- a/arch/csr/I/pmpaddr16.yaml +++ b/arch/csr/I/pmpaddr16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr16 diff --git a/arch/csr/I/pmpaddr17.yaml b/arch/csr/I/pmpaddr17.yaml index 31ea87ecd..94b5b47b4 100644 --- a/arch/csr/I/pmpaddr17.yaml +++ b/arch/csr/I/pmpaddr17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr17 diff --git a/arch/csr/I/pmpaddr18.yaml b/arch/csr/I/pmpaddr18.yaml index 42927d3e5..1006a07df 100644 --- a/arch/csr/I/pmpaddr18.yaml +++ b/arch/csr/I/pmpaddr18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr18 diff --git a/arch/csr/I/pmpaddr19.yaml b/arch/csr/I/pmpaddr19.yaml index 1d6d4e332..7caa8cfbe 100644 --- a/arch/csr/I/pmpaddr19.yaml +++ b/arch/csr/I/pmpaddr19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr19 diff --git a/arch/csr/I/pmpaddr2.yaml b/arch/csr/I/pmpaddr2.yaml index 7b028ad20..8805ecdaf 100644 --- a/arch/csr/I/pmpaddr2.yaml +++ b/arch/csr/I/pmpaddr2.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr2 diff --git a/arch/csr/I/pmpaddr20.yaml b/arch/csr/I/pmpaddr20.yaml index 4706bddad..2479fbb52 100644 --- a/arch/csr/I/pmpaddr20.yaml +++ b/arch/csr/I/pmpaddr20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr20 diff --git a/arch/csr/I/pmpaddr21.yaml b/arch/csr/I/pmpaddr21.yaml index 235ebd088..27f99fec3 100644 --- a/arch/csr/I/pmpaddr21.yaml +++ b/arch/csr/I/pmpaddr21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr21 diff --git a/arch/csr/I/pmpaddr22.yaml b/arch/csr/I/pmpaddr22.yaml index da683c397..e73835903 100644 --- a/arch/csr/I/pmpaddr22.yaml +++ b/arch/csr/I/pmpaddr22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr22 diff --git a/arch/csr/I/pmpaddr23.yaml b/arch/csr/I/pmpaddr23.yaml index 86fd9e568..b23078e01 100644 --- a/arch/csr/I/pmpaddr23.yaml +++ b/arch/csr/I/pmpaddr23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr23 diff --git a/arch/csr/I/pmpaddr24.yaml b/arch/csr/I/pmpaddr24.yaml index eb23278cf..f07a22f66 100644 --- a/arch/csr/I/pmpaddr24.yaml +++ b/arch/csr/I/pmpaddr24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr24 diff --git a/arch/csr/I/pmpaddr25.yaml b/arch/csr/I/pmpaddr25.yaml index 779b656eb..c3a791b22 100644 --- a/arch/csr/I/pmpaddr25.yaml +++ b/arch/csr/I/pmpaddr25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr25 diff --git a/arch/csr/I/pmpaddr26.yaml b/arch/csr/I/pmpaddr26.yaml index 6a1b7445e..ad2d1cb06 100644 --- a/arch/csr/I/pmpaddr26.yaml +++ b/arch/csr/I/pmpaddr26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr26 diff --git a/arch/csr/I/pmpaddr27.yaml b/arch/csr/I/pmpaddr27.yaml index 3960dda99..ef27d3bf9 100644 --- a/arch/csr/I/pmpaddr27.yaml +++ b/arch/csr/I/pmpaddr27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr27 diff --git a/arch/csr/I/pmpaddr28.yaml b/arch/csr/I/pmpaddr28.yaml index 062e089de..b7f1bf427 100644 --- a/arch/csr/I/pmpaddr28.yaml +++ b/arch/csr/I/pmpaddr28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr28 diff --git a/arch/csr/I/pmpaddr29.yaml b/arch/csr/I/pmpaddr29.yaml index 770c88ddc..7a0a971ad 100644 --- a/arch/csr/I/pmpaddr29.yaml +++ b/arch/csr/I/pmpaddr29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr29 diff --git a/arch/csr/I/pmpaddr3.yaml b/arch/csr/I/pmpaddr3.yaml index b533c5996..7d79c0b92 100644 --- a/arch/csr/I/pmpaddr3.yaml +++ b/arch/csr/I/pmpaddr3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr3 diff --git a/arch/csr/I/pmpaddr30.yaml b/arch/csr/I/pmpaddr30.yaml index 6ef468278..0b8481e85 100644 --- a/arch/csr/I/pmpaddr30.yaml +++ b/arch/csr/I/pmpaddr30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr30 diff --git a/arch/csr/I/pmpaddr31.yaml b/arch/csr/I/pmpaddr31.yaml index 031f099eb..cb6889d51 100644 --- a/arch/csr/I/pmpaddr31.yaml +++ b/arch/csr/I/pmpaddr31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr31 diff --git a/arch/csr/I/pmpaddr32.yaml b/arch/csr/I/pmpaddr32.yaml index 9c6b6b9b1..ef38ca7aa 100644 --- a/arch/csr/I/pmpaddr32.yaml +++ b/arch/csr/I/pmpaddr32.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr32 diff --git a/arch/csr/I/pmpaddr33.yaml b/arch/csr/I/pmpaddr33.yaml index 6f90b581e..8bac47492 100644 --- a/arch/csr/I/pmpaddr33.yaml +++ b/arch/csr/I/pmpaddr33.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr33 diff --git a/arch/csr/I/pmpaddr34.yaml b/arch/csr/I/pmpaddr34.yaml index 64c83a7e5..8c06828a1 100644 --- a/arch/csr/I/pmpaddr34.yaml +++ b/arch/csr/I/pmpaddr34.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr34 diff --git a/arch/csr/I/pmpaddr35.yaml b/arch/csr/I/pmpaddr35.yaml index 9ed46e1dd..8cc63fde5 100644 --- a/arch/csr/I/pmpaddr35.yaml +++ b/arch/csr/I/pmpaddr35.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr35 diff --git a/arch/csr/I/pmpaddr36.yaml b/arch/csr/I/pmpaddr36.yaml index 770a97f9a..4b2283112 100644 --- a/arch/csr/I/pmpaddr36.yaml +++ b/arch/csr/I/pmpaddr36.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr36 diff --git a/arch/csr/I/pmpaddr37.yaml b/arch/csr/I/pmpaddr37.yaml index a93a78a01..957132029 100644 --- a/arch/csr/I/pmpaddr37.yaml +++ b/arch/csr/I/pmpaddr37.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr37 diff --git a/arch/csr/I/pmpaddr38.yaml b/arch/csr/I/pmpaddr38.yaml index b74030c19..4979a53a5 100644 --- a/arch/csr/I/pmpaddr38.yaml +++ b/arch/csr/I/pmpaddr38.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr38 diff --git a/arch/csr/I/pmpaddr39.yaml b/arch/csr/I/pmpaddr39.yaml index f9966eaa9..41340b495 100644 --- a/arch/csr/I/pmpaddr39.yaml +++ b/arch/csr/I/pmpaddr39.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr39 diff --git a/arch/csr/I/pmpaddr4.yaml b/arch/csr/I/pmpaddr4.yaml index 4ea909757..0a5d45b7a 100644 --- a/arch/csr/I/pmpaddr4.yaml +++ b/arch/csr/I/pmpaddr4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr4 diff --git a/arch/csr/I/pmpaddr40.yaml b/arch/csr/I/pmpaddr40.yaml index 496d6a9b8..21b3cf11f 100644 --- a/arch/csr/I/pmpaddr40.yaml +++ b/arch/csr/I/pmpaddr40.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr40 diff --git a/arch/csr/I/pmpaddr41.yaml b/arch/csr/I/pmpaddr41.yaml index c187fa435..6bb1bafc9 100644 --- a/arch/csr/I/pmpaddr41.yaml +++ b/arch/csr/I/pmpaddr41.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr41 diff --git a/arch/csr/I/pmpaddr42.yaml b/arch/csr/I/pmpaddr42.yaml index 4daef7a3c..bdab7845a 100644 --- a/arch/csr/I/pmpaddr42.yaml +++ b/arch/csr/I/pmpaddr42.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr42 diff --git a/arch/csr/I/pmpaddr43.yaml b/arch/csr/I/pmpaddr43.yaml index e8dd8f949..91b1812bc 100644 --- a/arch/csr/I/pmpaddr43.yaml +++ b/arch/csr/I/pmpaddr43.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr43 diff --git a/arch/csr/I/pmpaddr44.yaml b/arch/csr/I/pmpaddr44.yaml index 1ccd84dfc..5d0cdfca6 100644 --- a/arch/csr/I/pmpaddr44.yaml +++ b/arch/csr/I/pmpaddr44.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr44 diff --git a/arch/csr/I/pmpaddr45.yaml b/arch/csr/I/pmpaddr45.yaml index e600d8e97..18e02b28c 100644 --- a/arch/csr/I/pmpaddr45.yaml +++ b/arch/csr/I/pmpaddr45.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr45 diff --git a/arch/csr/I/pmpaddr46.yaml b/arch/csr/I/pmpaddr46.yaml index 9869421e0..950b7b2b8 100644 --- a/arch/csr/I/pmpaddr46.yaml +++ b/arch/csr/I/pmpaddr46.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr46 diff --git a/arch/csr/I/pmpaddr47.yaml b/arch/csr/I/pmpaddr47.yaml index 7f5b867a4..fb6a5f422 100644 --- a/arch/csr/I/pmpaddr47.yaml +++ b/arch/csr/I/pmpaddr47.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr47 diff --git a/arch/csr/I/pmpaddr48.yaml b/arch/csr/I/pmpaddr48.yaml index 739549f6c..9eba2608a 100644 --- a/arch/csr/I/pmpaddr48.yaml +++ b/arch/csr/I/pmpaddr48.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr48 diff --git a/arch/csr/I/pmpaddr49.yaml b/arch/csr/I/pmpaddr49.yaml index e14ed4ff6..26cb23996 100644 --- a/arch/csr/I/pmpaddr49.yaml +++ b/arch/csr/I/pmpaddr49.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr49 diff --git a/arch/csr/I/pmpaddr5.yaml b/arch/csr/I/pmpaddr5.yaml index 998712e5c..8a73ce45e 100644 --- a/arch/csr/I/pmpaddr5.yaml +++ b/arch/csr/I/pmpaddr5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr5 diff --git a/arch/csr/I/pmpaddr50.yaml b/arch/csr/I/pmpaddr50.yaml index 6226177fc..69aff1dec 100644 --- a/arch/csr/I/pmpaddr50.yaml +++ b/arch/csr/I/pmpaddr50.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr50 diff --git a/arch/csr/I/pmpaddr51.yaml b/arch/csr/I/pmpaddr51.yaml index 45461b001..d5d6464f4 100644 --- a/arch/csr/I/pmpaddr51.yaml +++ b/arch/csr/I/pmpaddr51.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr51 diff --git a/arch/csr/I/pmpaddr52.yaml b/arch/csr/I/pmpaddr52.yaml index 936908255..49ace51ac 100644 --- a/arch/csr/I/pmpaddr52.yaml +++ b/arch/csr/I/pmpaddr52.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr52 diff --git a/arch/csr/I/pmpaddr53.yaml b/arch/csr/I/pmpaddr53.yaml index 8e6e625ec..222efed3b 100644 --- a/arch/csr/I/pmpaddr53.yaml +++ b/arch/csr/I/pmpaddr53.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr53 diff --git a/arch/csr/I/pmpaddr54.yaml b/arch/csr/I/pmpaddr54.yaml index be5082f31..6f7e7677d 100644 --- a/arch/csr/I/pmpaddr54.yaml +++ b/arch/csr/I/pmpaddr54.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr54 diff --git a/arch/csr/I/pmpaddr55.yaml b/arch/csr/I/pmpaddr55.yaml index 0602b076f..0f9d5a506 100644 --- a/arch/csr/I/pmpaddr55.yaml +++ b/arch/csr/I/pmpaddr55.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr55 diff --git a/arch/csr/I/pmpaddr56.yaml b/arch/csr/I/pmpaddr56.yaml index 0a2be33f0..4ca1bd3e5 100644 --- a/arch/csr/I/pmpaddr56.yaml +++ b/arch/csr/I/pmpaddr56.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr56 diff --git a/arch/csr/I/pmpaddr57.yaml b/arch/csr/I/pmpaddr57.yaml index 1896ef4c6..bde0f738b 100644 --- a/arch/csr/I/pmpaddr57.yaml +++ b/arch/csr/I/pmpaddr57.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr57 diff --git a/arch/csr/I/pmpaddr58.yaml b/arch/csr/I/pmpaddr58.yaml index 78838af7d..6fa1aa32e 100644 --- a/arch/csr/I/pmpaddr58.yaml +++ b/arch/csr/I/pmpaddr58.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr58 diff --git a/arch/csr/I/pmpaddr59.yaml b/arch/csr/I/pmpaddr59.yaml index 8494a9ee5..794787cfd 100644 --- a/arch/csr/I/pmpaddr59.yaml +++ b/arch/csr/I/pmpaddr59.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr59 diff --git a/arch/csr/I/pmpaddr6.yaml b/arch/csr/I/pmpaddr6.yaml index eba823575..28733415e 100644 --- a/arch/csr/I/pmpaddr6.yaml +++ b/arch/csr/I/pmpaddr6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr6 diff --git a/arch/csr/I/pmpaddr60.yaml b/arch/csr/I/pmpaddr60.yaml index b33f867e9..293249668 100644 --- a/arch/csr/I/pmpaddr60.yaml +++ b/arch/csr/I/pmpaddr60.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr60 diff --git a/arch/csr/I/pmpaddr61.yaml b/arch/csr/I/pmpaddr61.yaml index 55c4244d9..957026423 100644 --- a/arch/csr/I/pmpaddr61.yaml +++ b/arch/csr/I/pmpaddr61.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr61 diff --git a/arch/csr/I/pmpaddr62.yaml b/arch/csr/I/pmpaddr62.yaml index ba3ffcece..0ae068f5d 100644 --- a/arch/csr/I/pmpaddr62.yaml +++ b/arch/csr/I/pmpaddr62.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr62 diff --git a/arch/csr/I/pmpaddr63.yaml b/arch/csr/I/pmpaddr63.yaml index 40cf7a6e2..d448de1db 100644 --- a/arch/csr/I/pmpaddr63.yaml +++ b/arch/csr/I/pmpaddr63.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr63 diff --git a/arch/csr/I/pmpaddr7.yaml b/arch/csr/I/pmpaddr7.yaml index 105d6cbf2..710c59757 100644 --- a/arch/csr/I/pmpaddr7.yaml +++ b/arch/csr/I/pmpaddr7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr7 diff --git a/arch/csr/I/pmpaddr8.yaml b/arch/csr/I/pmpaddr8.yaml index 355789fcb..e6807b166 100644 --- a/arch/csr/I/pmpaddr8.yaml +++ b/arch/csr/I/pmpaddr8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr8 diff --git a/arch/csr/I/pmpaddr9.yaml b/arch/csr/I/pmpaddr9.yaml index 827cb70d2..5cefea0af 100644 --- a/arch/csr/I/pmpaddr9.yaml +++ b/arch/csr/I/pmpaddr9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr9 diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index 51714e954..63d55e9e3 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg0 @@ -17,39 +15,39 @@ fields: pmp0cfg: location: 7-0 description: | - *PMP configuration for entry 0* + *PMP configuration for entry 0* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 0) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp1cfg: location: 15-8 description: | - *PMP configuration for entry 1* + *PMP configuration for entry 1* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 1) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp2cfg: location: 23-16 description: | - *PMP configuration for entry 2* + *PMP configuration for entry 2* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 2) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp3cfg: location: 31-24 description: | - *PMP configuration for entry 3* + *PMP configuration for entry 3* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 3) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 4* + *PMP configuration for entry 4* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 4) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 5* + *PMP configuration for entry 5* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 5) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 6* + *PMP configuration for entry 6* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 6) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 7* + *PMP configuration for entry 7* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 7) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index 44e262a69..7d1f4480e 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg1 @@ -18,39 +16,39 @@ fields: pmp4cfg: location: 7-0 description: | - *PMP configuration for entry 4* + *PMP configuration for entry 4* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 4) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp5cfg: location: 15-8 description: | - *PMP configuration for entry 5* + *PMP configuration for entry 5* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 5) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp6cfg: location: 23-16 description: | - *PMP configuration for entry 6* + *PMP configuration for entry 6* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 6) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp7cfg: location: 31-24 description: | - *PMP configuration for entry 7* + *PMP configuration for entry 7* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 7) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index aa4343c0f..1773750b6 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg10 @@ -17,39 +15,39 @@ fields: pmp40cfg: location: 7-0 description: | - *PMP configuration for entry 40* + *PMP configuration for entry 40* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 40) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp41cfg: location: 15-8 description: | - *PMP configuration for entry 41* + *PMP configuration for entry 41* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 41) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp42cfg: location: 23-16 description: | - *PMP configuration for entry 42* + *PMP configuration for entry 42* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 42) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp43cfg: location: 31-24 description: | - *PMP configuration for entry 43* + *PMP configuration for entry 43* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 43) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 44* + *PMP configuration for entry 44* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 44) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 45* + *PMP configuration for entry 45* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 45) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 46* + *PMP configuration for entry 46* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 46) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 47* + *PMP configuration for entry 47* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 47) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index 7ba8d05b6..de85b308a 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg11 @@ -18,39 +16,39 @@ fields: pmp44cfg: location: 7-0 description: | - *PMP configuration for entry 44* + *PMP configuration for entry 44* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 44) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp45cfg: location: 15-8 description: | - *PMP configuration for entry 45* + *PMP configuration for entry 45* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 45) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp46cfg: location: 23-16 description: | - *PMP configuration for entry 46* + *PMP configuration for entry 46* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 46) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp47cfg: location: 31-24 description: | - *PMP configuration for entry 47* + *PMP configuration for entry 47* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 47) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index 8897f4db9..959226127 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg12 @@ -17,39 +15,39 @@ fields: pmp48cfg: location: 7-0 description: | - *PMP configuration for entry 48* + *PMP configuration for entry 48* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 48) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp49cfg: location: 15-8 description: | - *PMP configuration for entry 49* + *PMP configuration for entry 49* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 49) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp50cfg: location: 23-16 description: | - *PMP configuration for entry 50* + *PMP configuration for entry 50* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 50) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp51cfg: location: 31-24 description: | - *PMP configuration for entry 51* + *PMP configuration for entry 51* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 51) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 52* + *PMP configuration for entry 52* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 52) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 53* + *PMP configuration for entry 53* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 53) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 54* + *PMP configuration for entry 54* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 54) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 55* + *PMP configuration for entry 55* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 55) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index aa151be42..2d937261f 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg13 @@ -18,39 +16,39 @@ fields: pmp52cfg: location: 7-0 description: | - *PMP configuration for entry 52* + *PMP configuration for entry 52* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 52) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp53cfg: location: 15-8 description: | - *PMP configuration for entry 53* + *PMP configuration for entry 53* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 53) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp54cfg: location: 23-16 description: | - *PMP configuration for entry 54* + *PMP configuration for entry 54* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 54) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp55cfg: location: 31-24 description: | - *PMP configuration for entry 55* + *PMP configuration for entry 55* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 55) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index e5c4744d4..e3e6bb44c 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg14 @@ -17,39 +15,39 @@ fields: pmp56cfg: location: 7-0 description: | - *PMP configuration for entry 56* + *PMP configuration for entry 56* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 56) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp57cfg: location: 15-8 description: | - *PMP configuration for entry 57* + *PMP configuration for entry 57* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 57) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp58cfg: location: 23-16 description: | - *PMP configuration for entry 58* + *PMP configuration for entry 58* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 58) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp59cfg: location: 31-24 description: | - *PMP configuration for entry 59* + *PMP configuration for entry 59* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 59) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 60* + *PMP configuration for entry 60* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 60) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 61* + *PMP configuration for entry 61* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 61) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 62* + *PMP configuration for entry 62* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 62) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 63* + *PMP configuration for entry 63* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 63) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 43454115e..410c6d15e 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg15 @@ -18,39 +16,39 @@ fields: pmp60cfg: location: 7-0 description: | - *PMP configuration for entry 60* + *PMP configuration for entry 60* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 60) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp61cfg: location: 15-8 description: | - *PMP configuration for entry 61* + *PMP configuration for entry 61* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 61) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp62cfg: location: 23-16 description: | - *PMP configuration for entry 62* + *PMP configuration for entry 62* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 62) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp63cfg: location: 31-24 description: | - *PMP configuration for entry 63* + *PMP configuration for entry 63* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 63) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index bad4210e8..c3422f116 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg2 @@ -17,39 +15,39 @@ fields: pmp8cfg: location: 7-0 description: | - *PMP configuration for entry 8* + *PMP configuration for entry 8* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 8) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp9cfg: location: 15-8 description: | - *PMP configuration for entry 9* + *PMP configuration for entry 9* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 9) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp10cfg: location: 23-16 description: | - *PMP configuration for entry 10* + *PMP configuration for entry 10* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 10) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp11cfg: location: 31-24 description: | - *PMP configuration for entry 11* + *PMP configuration for entry 11* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 11) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 12* + *PMP configuration for entry 12* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 12) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 13* + *PMP configuration for entry 13* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 13) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 14* + *PMP configuration for entry 14* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 14) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 15* + *PMP configuration for entry 15* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 15) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index 31f5a4806..d1002e342 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg3 @@ -18,39 +16,39 @@ fields: pmp12cfg: location: 7-0 description: | - *PMP configuration for entry 12* + *PMP configuration for entry 12* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 12) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp13cfg: location: 15-8 description: | - *PMP configuration for entry 13* + *PMP configuration for entry 13* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 13) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp14cfg: location: 23-16 description: | - *PMP configuration for entry 14* + *PMP configuration for entry 14* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 14) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp15cfg: location: 31-24 description: | - *PMP configuration for entry 15* + *PMP configuration for entry 15* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 15) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index d55346cc5..4b1b6b335 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg4 @@ -17,39 +15,39 @@ fields: pmp16cfg: location: 7-0 description: | - *PMP configuration for entry 16* + *PMP configuration for entry 16* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 16) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp17cfg: location: 15-8 description: | - *PMP configuration for entry 17* + *PMP configuration for entry 17* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 17) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp18cfg: location: 23-16 description: | - *PMP configuration for entry 18* + *PMP configuration for entry 18* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 18) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp19cfg: location: 31-24 description: | - *PMP configuration for entry 19* + *PMP configuration for entry 19* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 19) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 20* + *PMP configuration for entry 20* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 20) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 21* + *PMP configuration for entry 21* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 21) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 22* + *PMP configuration for entry 22* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 22) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 23* + *PMP configuration for entry 23* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 23) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index 3b9e2477c..afc26fccc 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg5 @@ -18,39 +16,39 @@ fields: pmp20cfg: location: 7-0 description: | - *PMP configuration for entry 20* + *PMP configuration for entry 20* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 20) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp21cfg: location: 15-8 description: | - *PMP configuration for entry 21* + *PMP configuration for entry 21* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 21) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp22cfg: location: 23-16 description: | - *PMP configuration for entry 22* + *PMP configuration for entry 22* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 22) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp23cfg: location: 31-24 description: | - *PMP configuration for entry 23* + *PMP configuration for entry 23* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 23) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index a7ab336b6..609f67617 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg6 @@ -17,39 +15,39 @@ fields: pmp24cfg: location: 7-0 description: | - *PMP configuration for entry 24* + *PMP configuration for entry 24* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 24) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp25cfg: location: 15-8 description: | - *PMP configuration for entry 25* + *PMP configuration for entry 25* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 25) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp26cfg: location: 23-16 description: | - *PMP configuration for entry 26* + *PMP configuration for entry 26* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 26) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp27cfg: location: 31-24 description: | - *PMP configuration for entry 27* + *PMP configuration for entry 27* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 27) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 28* + *PMP configuration for entry 28* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 28) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 29* + *PMP configuration for entry 29* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 29) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 30* + *PMP configuration for entry 30* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 30) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 31* + *PMP configuration for entry 31* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 31) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index bebd1871e..d56da433e 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg7 @@ -18,39 +16,39 @@ fields: pmp28cfg: location: 7-0 description: | - *PMP configuration for entry 28* + *PMP configuration for entry 28* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 28) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp29cfg: location: 15-8 description: | - *PMP configuration for entry 29* + *PMP configuration for entry 29* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 29) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp30cfg: location: 23-16 description: | - *PMP configuration for entry 30* + *PMP configuration for entry 30* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 30) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp31cfg: location: 31-24 description: | - *PMP configuration for entry 31* + *PMP configuration for entry 31* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 31) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index fa3b0fbd4..de8650e6c 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg8 @@ -17,39 +15,39 @@ fields: pmp32cfg: location: 7-0 description: | - *PMP configuration for entry 32* + *PMP configuration for entry 32* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 32) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp33cfg: location: 15-8 description: | - *PMP configuration for entry 33* + *PMP configuration for entry 33* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 33) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp34cfg: location: 23-16 description: | - *PMP configuration for entry 34* + *PMP configuration for entry 34* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 34) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp35cfg: location: 31-24 description: | - *PMP configuration for entry 35* + *PMP configuration for entry 35* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 35) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 36* + *PMP configuration for entry 36* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 36) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 37* + *PMP configuration for entry 37* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 37) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 38* + *PMP configuration for entry 38* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 38) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 39* + *PMP configuration for entry 39* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 39) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index 6fccacb66..c5878baa0 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg9 @@ -18,39 +16,39 @@ fields: pmp36cfg: location: 7-0 description: | - *PMP configuration for entry 36* + *PMP configuration for entry 36* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 36) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp37cfg: location: 15-8 description: | - *PMP configuration for entry 37* + *PMP configuration for entry 37* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 37) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp38cfg: location: 23-16 description: | - *PMP configuration for entry 38* + *PMP configuration for entry 38* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 38) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp39cfg: location: 31-24 description: | - *PMP configuration for entry 39* + *PMP configuration for entry 39* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 39) { return CsrFieldType::RWR; diff --git a/arch/csr/S/scounteren.yaml b/arch/csr/S/scounteren.yaml index f0055805a..395ec77d8 100644 --- a/arch/csr/S/scounteren.yaml +++ b/arch/csr/S/scounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/S/scounteren.layout - $schema: csr_schema.json# kind: csr name: scounteren diff --git a/arch/csr/Zicntr/mcountinhibit.yaml b/arch/csr/Zicntr/mcountinhibit.yaml index a8d3fe823..685b45357 100644 --- a/arch/csr/Zicntr/mcountinhibit.yaml +++ b/arch/csr/Zicntr/mcountinhibit.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zicntr/mcountinhibit.layout - $schema: csr_schema.json# kind: csr name: mcountinhibit @@ -44,8 +43,8 @@ description: | definedBy: anyOf: - - name: Sm - - name: Smhpm + - name: Sm + - name: Smhpm fields: CY: location: 0 diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index 73b4b9c3c..509504b05 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter10 diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 682f95116..86c92aae0 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter10h diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index 0cd3adbd9..81e45feb5 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter11 diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index d710fcfb1..2d0954a5e 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter11h diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index 940be2a1a..0960f7578 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter12 diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index da1b60847..696b27790 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter12h diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 251679470..24e9fc06f 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter13 diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 4f7ad9c11..7eac1cb8b 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter13h diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index c65d0acd8..8708dd5a6 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter14 diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index f5da64665..f34cb427a 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter14h diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index 0a1eeda23..007f40d8c 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter15 diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 0349cceaa..3212ae429 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter15h diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index fef98c2a2..016420bf0 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter16 diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 350f8f88d..9ffa84019 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter16h diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index 4326683c3..15f4889bd 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter17 diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 7d77d8dba..801ef507f 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter17h diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index 365ea8889..1b378ac50 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter18 diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 1714bdddd..cd38aad1b 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter18h diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index abeb3c0ae..f0a27a7a4 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter19 diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index fe8d94677..b408c5a47 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter19h diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index a92640605..60b930bb1 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter20 diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index db31015b8..e1a78f611 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter20h diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index 3d8ba93b2..60ad4c6fc 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter21 diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 57db30d76..2158d1093 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter21h diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index a2db1a461..2f5b26465 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter22 diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index c6f5555fc..f8987c1b8 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter22h diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index e8c4b5ff4..ec6b89bfa 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter23 diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index e6b261d23..c9b572cd5 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter23h diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index 5a214615d..aec19cb8d 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter24 diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index 9602adfb4..6ccbffcf0 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter24h diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index d10352ccd..577984436 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter25 diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index f77f95c9b..2662d4d51 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter25h diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index 778d77da5..20b5e5ccc 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter26 diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 346866402..e9c8b11c4 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter26h diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index 1e3014f54..52ba19b20 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter27 diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index bf683b7f9..5b18c3fc6 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter27h diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index f0359b73c..220586b96 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter28 diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index 635ba7b1e..6aaa60f56 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter28h diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index 479cae002..f63b3babc 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter29 diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index 7c76ca624..65f583acc 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter29h diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index 99907b9b8..a41868cae 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter3 diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 855b1087c..855006edb 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter30 diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 10e30fa68..8e04748de 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter30h diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 64aa6a664..431dd4679 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter31 diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 07bf78fe6..4d1edf797 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter31h diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index ea664cc42..157cef845 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter3h diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index 06d2d04cb..44fc65db9 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter4 diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index 47951185a..26902cc18 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter4h diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index ff0ce06fa..fd1be13a9 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter5 diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 354e4465a..81d40289f 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter5h diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index dd153ff5a..8834e0c21 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter6 diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 238c4e628..b60dee03e 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter6h diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index b350ebbd6..57841b7dd 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter7 diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 27b2468c8..6f37af957 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter7h diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index 7c4a50d31..a99cd0ce8 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter8 diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index 5eb7fcf05..83175ce6e 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter8h diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 91fbcf184..126d8ad01 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter9 diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index 8a9e203c7..100a8c9de 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter9h diff --git a/arch/csr/Zihpm/mhpmcounter10.yaml b/arch/csr/Zihpm/mhpmcounter10.yaml index abcf005ae..8bbc5e1d9 100644 --- a/arch/csr/Zihpm/mhpmcounter10.yaml +++ b/arch/csr/Zihpm/mhpmcounter10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter10 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[10] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[10]) { return read_hpm_counter(10); diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index d020a06c0..c17a6fdce 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter10h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT10[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[10]) { return read_hpm_counter(10)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter11.yaml b/arch/csr/Zihpm/mhpmcounter11.yaml index 311fc0cf1..0501702a3 100644 --- a/arch/csr/Zihpm/mhpmcounter11.yaml +++ b/arch/csr/Zihpm/mhpmcounter11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter11 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[11] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[11]) { return read_hpm_counter(11); diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 51e1157b1..8514ff4dc 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter11h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT11[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[11]) { return read_hpm_counter(11)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter12.yaml b/arch/csr/Zihpm/mhpmcounter12.yaml index fb1f3e895..f0aceebd1 100644 --- a/arch/csr/Zihpm/mhpmcounter12.yaml +++ b/arch/csr/Zihpm/mhpmcounter12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter12 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[12] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[12]) { return read_hpm_counter(12); diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 552478c7b..2f648514d 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter12h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT12[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[12]) { return read_hpm_counter(12)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter13.yaml b/arch/csr/Zihpm/mhpmcounter13.yaml index 5ac700007..10fc117df 100644 --- a/arch/csr/Zihpm/mhpmcounter13.yaml +++ b/arch/csr/Zihpm/mhpmcounter13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter13 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[13] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[13]) { return read_hpm_counter(13); diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index de931ede3..57b60ca1c 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter13h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT13[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[13]) { return read_hpm_counter(13)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter14.yaml b/arch/csr/Zihpm/mhpmcounter14.yaml index f9da216b0..2285c2cca 100644 --- a/arch/csr/Zihpm/mhpmcounter14.yaml +++ b/arch/csr/Zihpm/mhpmcounter14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter14 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[14] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[14]) { return read_hpm_counter(14); diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index fad4f5d6e..63791d24f 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter14h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT14[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[14]) { return read_hpm_counter(14)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter15.yaml b/arch/csr/Zihpm/mhpmcounter15.yaml index fa067b80e..a487e21c5 100644 --- a/arch/csr/Zihpm/mhpmcounter15.yaml +++ b/arch/csr/Zihpm/mhpmcounter15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter15 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[15] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[15]) { return read_hpm_counter(15); diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 56080a49c..040f97e01 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter15h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT15[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[15]) { return read_hpm_counter(15)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter16.yaml b/arch/csr/Zihpm/mhpmcounter16.yaml index 3c0a9f6eb..9ff6a8263 100644 --- a/arch/csr/Zihpm/mhpmcounter16.yaml +++ b/arch/csr/Zihpm/mhpmcounter16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter16 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[16] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[16]) { return read_hpm_counter(16); diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index 040cf26b5..1bbbb515a 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter16h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT16[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[16]) { return read_hpm_counter(16)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter17.yaml b/arch/csr/Zihpm/mhpmcounter17.yaml index a053f43f7..6c30f92d6 100644 --- a/arch/csr/Zihpm/mhpmcounter17.yaml +++ b/arch/csr/Zihpm/mhpmcounter17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter17 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[17] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[17]) { return read_hpm_counter(17); diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 913a81271..d7450adab 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter17h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT17[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[17]) { return read_hpm_counter(17)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter18.yaml b/arch/csr/Zihpm/mhpmcounter18.yaml index 8487fd364..02b6dcd4f 100644 --- a/arch/csr/Zihpm/mhpmcounter18.yaml +++ b/arch/csr/Zihpm/mhpmcounter18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter18 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[18] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[18]) { return read_hpm_counter(18); diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index b8dd73f0b..4d9cffaac 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter18h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT18[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[18]) { return read_hpm_counter(18)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter19.yaml b/arch/csr/Zihpm/mhpmcounter19.yaml index df0b9be79..0e45c395c 100644 --- a/arch/csr/Zihpm/mhpmcounter19.yaml +++ b/arch/csr/Zihpm/mhpmcounter19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter19 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[19] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[19]) { return read_hpm_counter(19); diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 306eea43c..63857f32e 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter19h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT19[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[19]) { return read_hpm_counter(19)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter20.yaml b/arch/csr/Zihpm/mhpmcounter20.yaml index c902cf875..6f7d6d1e8 100644 --- a/arch/csr/Zihpm/mhpmcounter20.yaml +++ b/arch/csr/Zihpm/mhpmcounter20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter20 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[20] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[20]) { return read_hpm_counter(20); diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 7366268de..ee8760ed7 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter20h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT20[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[20]) { return read_hpm_counter(20)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter21.yaml b/arch/csr/Zihpm/mhpmcounter21.yaml index 961203af3..b5cfa7a02 100644 --- a/arch/csr/Zihpm/mhpmcounter21.yaml +++ b/arch/csr/Zihpm/mhpmcounter21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter21 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[21] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[21]) { return read_hpm_counter(21); diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index 8686eab27..2437ed36b 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter21h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT21[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[21]) { return read_hpm_counter(21)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter22.yaml b/arch/csr/Zihpm/mhpmcounter22.yaml index 1f1df6c96..d35d8671d 100644 --- a/arch/csr/Zihpm/mhpmcounter22.yaml +++ b/arch/csr/Zihpm/mhpmcounter22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter22 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[22] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[22]) { return read_hpm_counter(22); diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index f4049e79c..2be137d45 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter22h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT22[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[22]) { return read_hpm_counter(22)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter23.yaml b/arch/csr/Zihpm/mhpmcounter23.yaml index 83c25f79f..380c27d78 100644 --- a/arch/csr/Zihpm/mhpmcounter23.yaml +++ b/arch/csr/Zihpm/mhpmcounter23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter23 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[23] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[23]) { return read_hpm_counter(23); diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 9152e9d9a..980c37379 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter23h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT23[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[23]) { return read_hpm_counter(23)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter24.yaml b/arch/csr/Zihpm/mhpmcounter24.yaml index c68626718..4f6669999 100644 --- a/arch/csr/Zihpm/mhpmcounter24.yaml +++ b/arch/csr/Zihpm/mhpmcounter24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter24 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[24] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[24]) { return read_hpm_counter(24); diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index 55bdde30a..c609c2658 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter24h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT24[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[24]) { return read_hpm_counter(24)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter25.yaml b/arch/csr/Zihpm/mhpmcounter25.yaml index dca9e4028..ca1ea5198 100644 --- a/arch/csr/Zihpm/mhpmcounter25.yaml +++ b/arch/csr/Zihpm/mhpmcounter25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter25 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[25] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[25]) { return read_hpm_counter(25); diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index 3d136816b..147c52d26 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter25h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT25[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[25]) { return read_hpm_counter(25)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter26.yaml b/arch/csr/Zihpm/mhpmcounter26.yaml index 0f70f1721..9175778c0 100644 --- a/arch/csr/Zihpm/mhpmcounter26.yaml +++ b/arch/csr/Zihpm/mhpmcounter26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter26 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[26] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[26]) { return read_hpm_counter(26); diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index b98d78a8c..11138a32a 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter26h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT26[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[26]) { return read_hpm_counter(26)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter27.yaml b/arch/csr/Zihpm/mhpmcounter27.yaml index 2682ce374..0cc6b33f9 100644 --- a/arch/csr/Zihpm/mhpmcounter27.yaml +++ b/arch/csr/Zihpm/mhpmcounter27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter27 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[27] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[27]) { return read_hpm_counter(27); diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index b45fd8ebe..8139cf8f7 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter27h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT27[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[27]) { return read_hpm_counter(27)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter28.yaml b/arch/csr/Zihpm/mhpmcounter28.yaml index a1c4fbb25..f21459474 100644 --- a/arch/csr/Zihpm/mhpmcounter28.yaml +++ b/arch/csr/Zihpm/mhpmcounter28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter28 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[28] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[28]) { return read_hpm_counter(28); diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index 2167cc2e9..995afc750 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter28h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT28[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[28]) { return read_hpm_counter(28)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter29.yaml b/arch/csr/Zihpm/mhpmcounter29.yaml index 6127a0c55..367de7cfe 100644 --- a/arch/csr/Zihpm/mhpmcounter29.yaml +++ b/arch/csr/Zihpm/mhpmcounter29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter29 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[29] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[29]) { return read_hpm_counter(29); diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index e924c6460..f6f68ee5b 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter29h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT29[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[29]) { return read_hpm_counter(29)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter3.yaml b/arch/csr/Zihpm/mhpmcounter3.yaml index 61729e21a..5c8dd1c6e 100644 --- a/arch/csr/Zihpm/mhpmcounter3.yaml +++ b/arch/csr/Zihpm/mhpmcounter3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter3 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[3] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[3]) { return read_hpm_counter(3); diff --git a/arch/csr/Zihpm/mhpmcounter30.yaml b/arch/csr/Zihpm/mhpmcounter30.yaml index a4ab437be..441eaab90 100644 --- a/arch/csr/Zihpm/mhpmcounter30.yaml +++ b/arch/csr/Zihpm/mhpmcounter30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter30 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[30] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[30]) { return read_hpm_counter(30); diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index 603f63f89..01d566880 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter30h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT30[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[30]) { return read_hpm_counter(30)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter31.yaml b/arch/csr/Zihpm/mhpmcounter31.yaml index 32c98cd50..917c8d533 100644 --- a/arch/csr/Zihpm/mhpmcounter31.yaml +++ b/arch/csr/Zihpm/mhpmcounter31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter31 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[31] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[31]) { return read_hpm_counter(31); diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index da1da7a17..185b961c3 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter31h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT31[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[31]) { return read_hpm_counter(31)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index cd0e5dd7c..5b95135dc 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter3h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT3[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[3]) { return read_hpm_counter(3)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter4.yaml b/arch/csr/Zihpm/mhpmcounter4.yaml index eb5b9bbad..9fc827b0b 100644 --- a/arch/csr/Zihpm/mhpmcounter4.yaml +++ b/arch/csr/Zihpm/mhpmcounter4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter4 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[4] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[4]) { return read_hpm_counter(4); diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index ca888f72e..ff2ffb6a2 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter4h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT4[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[4]) { return read_hpm_counter(4)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter5.yaml b/arch/csr/Zihpm/mhpmcounter5.yaml index 5fa038e73..b4c035e04 100644 --- a/arch/csr/Zihpm/mhpmcounter5.yaml +++ b/arch/csr/Zihpm/mhpmcounter5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter5 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[5] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[5]) { return read_hpm_counter(5); diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index 88ef7737f..e8cc95b13 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter5h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT5[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[5]) { return read_hpm_counter(5)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter6.yaml b/arch/csr/Zihpm/mhpmcounter6.yaml index 97527ec46..187e00a28 100644 --- a/arch/csr/Zihpm/mhpmcounter6.yaml +++ b/arch/csr/Zihpm/mhpmcounter6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter6 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[6] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[6]) { return read_hpm_counter(6); diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index 6907ddba6..356a42d65 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter6h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT6[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[6]) { return read_hpm_counter(6)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter7.yaml b/arch/csr/Zihpm/mhpmcounter7.yaml index cfb4ba894..7d56e48d5 100644 --- a/arch/csr/Zihpm/mhpmcounter7.yaml +++ b/arch/csr/Zihpm/mhpmcounter7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter7 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[7] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[7]) { return read_hpm_counter(7); diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 08aa55fb7..ae80b017a 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter7h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT7[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[7]) { return read_hpm_counter(7)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter8.yaml b/arch/csr/Zihpm/mhpmcounter8.yaml index 2c71caa78..a29a653bc 100644 --- a/arch/csr/Zihpm/mhpmcounter8.yaml +++ b/arch/csr/Zihpm/mhpmcounter8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter8 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[8] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[8]) { return read_hpm_counter(8); diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 8ae9a5aed..ab07e4a7c 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter8h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT8[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[8]) { return read_hpm_counter(8)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter9.yaml b/arch/csr/Zihpm/mhpmcounter9.yaml index 73392f5f1..729999ee5 100644 --- a/arch/csr/Zihpm/mhpmcounter9.yaml +++ b/arch/csr/Zihpm/mhpmcounter9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter9 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[9] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[9]) { return read_hpm_counter(9); diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index 9081f053b..307d049b4 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter9h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT9[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[9]) { return read_hpm_counter(9)[63:32]; diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml index 9b56c7491..52359704c 100644 --- a/arch/csr/Zihpm/mhpmevent10.yaml +++ b/arch/csr/Zihpm/mhpmevent10.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent10 diff --git a/arch/csr/Zihpm/mhpmevent10h.yaml b/arch/csr/Zihpm/mhpmevent10h.yaml index 9fe80eb61..ddc90479c 100644 --- a/arch/csr/Zihpm/mhpmevent10h.yaml +++ b/arch/csr/Zihpm/mhpmevent10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent10h diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml index 500c11cbc..f07693ca2 100644 --- a/arch/csr/Zihpm/mhpmevent11.yaml +++ b/arch/csr/Zihpm/mhpmevent11.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent11 diff --git a/arch/csr/Zihpm/mhpmevent11h.yaml b/arch/csr/Zihpm/mhpmevent11h.yaml index 7d1b6e997..10a4d69ab 100644 --- a/arch/csr/Zihpm/mhpmevent11h.yaml +++ b/arch/csr/Zihpm/mhpmevent11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent11h diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml index 3e06293c7..4233c540b 100644 --- a/arch/csr/Zihpm/mhpmevent12.yaml +++ b/arch/csr/Zihpm/mhpmevent12.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent12 diff --git a/arch/csr/Zihpm/mhpmevent12h.yaml b/arch/csr/Zihpm/mhpmevent12h.yaml index 054594b0d..1561213e0 100644 --- a/arch/csr/Zihpm/mhpmevent12h.yaml +++ b/arch/csr/Zihpm/mhpmevent12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent12h diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml index 5b4d051ba..b6691e172 100644 --- a/arch/csr/Zihpm/mhpmevent13.yaml +++ b/arch/csr/Zihpm/mhpmevent13.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent13 diff --git a/arch/csr/Zihpm/mhpmevent13h.yaml b/arch/csr/Zihpm/mhpmevent13h.yaml index 74ed46fde..9d6a4c4f4 100644 --- a/arch/csr/Zihpm/mhpmevent13h.yaml +++ b/arch/csr/Zihpm/mhpmevent13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent13h diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml index 5b09f4368..ed534b841 100644 --- a/arch/csr/Zihpm/mhpmevent14.yaml +++ b/arch/csr/Zihpm/mhpmevent14.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent14 diff --git a/arch/csr/Zihpm/mhpmevent14h.yaml b/arch/csr/Zihpm/mhpmevent14h.yaml index eb395e86d..53e1db943 100644 --- a/arch/csr/Zihpm/mhpmevent14h.yaml +++ b/arch/csr/Zihpm/mhpmevent14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent14h diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml index 5c72db6da..2140c2a97 100644 --- a/arch/csr/Zihpm/mhpmevent15.yaml +++ b/arch/csr/Zihpm/mhpmevent15.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent15 diff --git a/arch/csr/Zihpm/mhpmevent15h.yaml b/arch/csr/Zihpm/mhpmevent15h.yaml index 2914c5aa4..a8298f5a0 100644 --- a/arch/csr/Zihpm/mhpmevent15h.yaml +++ b/arch/csr/Zihpm/mhpmevent15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent15h diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml index 6eefa2918..7b041c5e8 100644 --- a/arch/csr/Zihpm/mhpmevent16.yaml +++ b/arch/csr/Zihpm/mhpmevent16.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent16 diff --git a/arch/csr/Zihpm/mhpmevent16h.yaml b/arch/csr/Zihpm/mhpmevent16h.yaml index 86c4539a1..7257f46c5 100644 --- a/arch/csr/Zihpm/mhpmevent16h.yaml +++ b/arch/csr/Zihpm/mhpmevent16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent16h diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml index 235850d37..698dde435 100644 --- a/arch/csr/Zihpm/mhpmevent17.yaml +++ b/arch/csr/Zihpm/mhpmevent17.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent17 diff --git a/arch/csr/Zihpm/mhpmevent17h.yaml b/arch/csr/Zihpm/mhpmevent17h.yaml index e73159f13..70e07cc5b 100644 --- a/arch/csr/Zihpm/mhpmevent17h.yaml +++ b/arch/csr/Zihpm/mhpmevent17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent17h diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml index 124d21a20..c6f2dfc40 100644 --- a/arch/csr/Zihpm/mhpmevent18.yaml +++ b/arch/csr/Zihpm/mhpmevent18.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent18 diff --git a/arch/csr/Zihpm/mhpmevent18h.yaml b/arch/csr/Zihpm/mhpmevent18h.yaml index 5d8f55fdc..4cd34aaaf 100644 --- a/arch/csr/Zihpm/mhpmevent18h.yaml +++ b/arch/csr/Zihpm/mhpmevent18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent18h diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml index 381680576..39dd37ef6 100644 --- a/arch/csr/Zihpm/mhpmevent19.yaml +++ b/arch/csr/Zihpm/mhpmevent19.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent19 diff --git a/arch/csr/Zihpm/mhpmevent19h.yaml b/arch/csr/Zihpm/mhpmevent19h.yaml index 30cf36077..2d67a0db2 100644 --- a/arch/csr/Zihpm/mhpmevent19h.yaml +++ b/arch/csr/Zihpm/mhpmevent19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent19h diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml index 370a5c4ce..2c6645a79 100644 --- a/arch/csr/Zihpm/mhpmevent20.yaml +++ b/arch/csr/Zihpm/mhpmevent20.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent20 diff --git a/arch/csr/Zihpm/mhpmevent20h.yaml b/arch/csr/Zihpm/mhpmevent20h.yaml index 1073830fd..32f9027ac 100644 --- a/arch/csr/Zihpm/mhpmevent20h.yaml +++ b/arch/csr/Zihpm/mhpmevent20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent20h diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml index 9164044e1..257aec1e1 100644 --- a/arch/csr/Zihpm/mhpmevent21.yaml +++ b/arch/csr/Zihpm/mhpmevent21.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent21 diff --git a/arch/csr/Zihpm/mhpmevent21h.yaml b/arch/csr/Zihpm/mhpmevent21h.yaml index cbb2757da..f5fa3dfe2 100644 --- a/arch/csr/Zihpm/mhpmevent21h.yaml +++ b/arch/csr/Zihpm/mhpmevent21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent21h diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml index a44146188..4731ba4e7 100644 --- a/arch/csr/Zihpm/mhpmevent22.yaml +++ b/arch/csr/Zihpm/mhpmevent22.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent22 diff --git a/arch/csr/Zihpm/mhpmevent22h.yaml b/arch/csr/Zihpm/mhpmevent22h.yaml index 1806b2789..a8adbe8a1 100644 --- a/arch/csr/Zihpm/mhpmevent22h.yaml +++ b/arch/csr/Zihpm/mhpmevent22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent22h diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml index 0c3d7d2f7..cc78b7c59 100644 --- a/arch/csr/Zihpm/mhpmevent23.yaml +++ b/arch/csr/Zihpm/mhpmevent23.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent23 diff --git a/arch/csr/Zihpm/mhpmevent23h.yaml b/arch/csr/Zihpm/mhpmevent23h.yaml index 41a9f0b02..ba1566e3d 100644 --- a/arch/csr/Zihpm/mhpmevent23h.yaml +++ b/arch/csr/Zihpm/mhpmevent23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent23h diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml index b566e153c..cd86cfa8f 100644 --- a/arch/csr/Zihpm/mhpmevent24.yaml +++ b/arch/csr/Zihpm/mhpmevent24.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent24 diff --git a/arch/csr/Zihpm/mhpmevent24h.yaml b/arch/csr/Zihpm/mhpmevent24h.yaml index 560463c51..69adfe753 100644 --- a/arch/csr/Zihpm/mhpmevent24h.yaml +++ b/arch/csr/Zihpm/mhpmevent24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent24h diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml index 55879cabe..79ce58cbd 100644 --- a/arch/csr/Zihpm/mhpmevent25.yaml +++ b/arch/csr/Zihpm/mhpmevent25.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent25 diff --git a/arch/csr/Zihpm/mhpmevent25h.yaml b/arch/csr/Zihpm/mhpmevent25h.yaml index 1eefa3bdf..411ba06a5 100644 --- a/arch/csr/Zihpm/mhpmevent25h.yaml +++ b/arch/csr/Zihpm/mhpmevent25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent25h diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml index 0efdccb2a..3537d02c3 100644 --- a/arch/csr/Zihpm/mhpmevent26.yaml +++ b/arch/csr/Zihpm/mhpmevent26.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent26 diff --git a/arch/csr/Zihpm/mhpmevent26h.yaml b/arch/csr/Zihpm/mhpmevent26h.yaml index 73bd744a7..276bf866f 100644 --- a/arch/csr/Zihpm/mhpmevent26h.yaml +++ b/arch/csr/Zihpm/mhpmevent26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent26h diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml index 22d5be09c..339b1afc4 100644 --- a/arch/csr/Zihpm/mhpmevent27.yaml +++ b/arch/csr/Zihpm/mhpmevent27.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent27 diff --git a/arch/csr/Zihpm/mhpmevent27h.yaml b/arch/csr/Zihpm/mhpmevent27h.yaml index cb1a55da6..f5136e8ec 100644 --- a/arch/csr/Zihpm/mhpmevent27h.yaml +++ b/arch/csr/Zihpm/mhpmevent27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent27h diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml index 172b0e1aa..c38cdcab0 100644 --- a/arch/csr/Zihpm/mhpmevent28.yaml +++ b/arch/csr/Zihpm/mhpmevent28.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent28 diff --git a/arch/csr/Zihpm/mhpmevent28h.yaml b/arch/csr/Zihpm/mhpmevent28h.yaml index 1f3bb09ab..6f5b083ed 100644 --- a/arch/csr/Zihpm/mhpmevent28h.yaml +++ b/arch/csr/Zihpm/mhpmevent28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent28h diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml index 42bbe1ef8..393ec1fd5 100644 --- a/arch/csr/Zihpm/mhpmevent29.yaml +++ b/arch/csr/Zihpm/mhpmevent29.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent29 diff --git a/arch/csr/Zihpm/mhpmevent29h.yaml b/arch/csr/Zihpm/mhpmevent29h.yaml index a7c41c7ab..11c6f67d7 100644 --- a/arch/csr/Zihpm/mhpmevent29h.yaml +++ b/arch/csr/Zihpm/mhpmevent29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent29h diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml index 2f309d6d9..64006dee4 100644 --- a/arch/csr/Zihpm/mhpmevent3.yaml +++ b/arch/csr/Zihpm/mhpmevent3.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent3 diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml index eb485ec4f..17a7b1a94 100644 --- a/arch/csr/Zihpm/mhpmevent30.yaml +++ b/arch/csr/Zihpm/mhpmevent30.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent30 diff --git a/arch/csr/Zihpm/mhpmevent30h.yaml b/arch/csr/Zihpm/mhpmevent30h.yaml index 3de930101..27b55926c 100644 --- a/arch/csr/Zihpm/mhpmevent30h.yaml +++ b/arch/csr/Zihpm/mhpmevent30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent30h diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml index 2e19278f2..281363e27 100644 --- a/arch/csr/Zihpm/mhpmevent31.yaml +++ b/arch/csr/Zihpm/mhpmevent31.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent31 diff --git a/arch/csr/Zihpm/mhpmevent31h.yaml b/arch/csr/Zihpm/mhpmevent31h.yaml index 7e03cc52e..0dca0fbe7 100644 --- a/arch/csr/Zihpm/mhpmevent31h.yaml +++ b/arch/csr/Zihpm/mhpmevent31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent31h diff --git a/arch/csr/Zihpm/mhpmevent3h.yaml b/arch/csr/Zihpm/mhpmevent3h.yaml index a2e4999af..b92a0a8e0 100644 --- a/arch/csr/Zihpm/mhpmevent3h.yaml +++ b/arch/csr/Zihpm/mhpmevent3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent3h diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml index 62e60497f..4c42d7c2d 100644 --- a/arch/csr/Zihpm/mhpmevent4.yaml +++ b/arch/csr/Zihpm/mhpmevent4.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent4 diff --git a/arch/csr/Zihpm/mhpmevent4h.yaml b/arch/csr/Zihpm/mhpmevent4h.yaml index 9981a53d1..e70ed1280 100644 --- a/arch/csr/Zihpm/mhpmevent4h.yaml +++ b/arch/csr/Zihpm/mhpmevent4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent4h diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml index 6f84cbb99..a5dcd5c67 100644 --- a/arch/csr/Zihpm/mhpmevent5.yaml +++ b/arch/csr/Zihpm/mhpmevent5.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent5 diff --git a/arch/csr/Zihpm/mhpmevent5h.yaml b/arch/csr/Zihpm/mhpmevent5h.yaml index 9194e4794..b8db07f6f 100644 --- a/arch/csr/Zihpm/mhpmevent5h.yaml +++ b/arch/csr/Zihpm/mhpmevent5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent5h diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml index d60f46635..a9bdf1c39 100644 --- a/arch/csr/Zihpm/mhpmevent6.yaml +++ b/arch/csr/Zihpm/mhpmevent6.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent6 diff --git a/arch/csr/Zihpm/mhpmevent6h.yaml b/arch/csr/Zihpm/mhpmevent6h.yaml index 4bcfb4141..d6e9003aa 100644 --- a/arch/csr/Zihpm/mhpmevent6h.yaml +++ b/arch/csr/Zihpm/mhpmevent6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent6h diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml index a439e216e..2cc53fd9b 100644 --- a/arch/csr/Zihpm/mhpmevent7.yaml +++ b/arch/csr/Zihpm/mhpmevent7.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent7 diff --git a/arch/csr/Zihpm/mhpmevent7h.yaml b/arch/csr/Zihpm/mhpmevent7h.yaml index a35879b13..f04327a66 100644 --- a/arch/csr/Zihpm/mhpmevent7h.yaml +++ b/arch/csr/Zihpm/mhpmevent7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent7h diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml index 2b7d07127..769eb3ab1 100644 --- a/arch/csr/Zihpm/mhpmevent8.yaml +++ b/arch/csr/Zihpm/mhpmevent8.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent8 diff --git a/arch/csr/Zihpm/mhpmevent8h.yaml b/arch/csr/Zihpm/mhpmevent8h.yaml index c3abcd162..0370dc318 100644 --- a/arch/csr/Zihpm/mhpmevent8h.yaml +++ b/arch/csr/Zihpm/mhpmevent8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent8h diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml index 821178e99..1674e0c64 100644 --- a/arch/csr/Zihpm/mhpmevent9.yaml +++ b/arch/csr/Zihpm/mhpmevent9.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent9 diff --git a/arch/csr/Zihpm/mhpmevent9h.yaml b/arch/csr/Zihpm/mhpmevent9h.yaml index 90ebe2e27..946464b3b 100644 --- a/arch/csr/Zihpm/mhpmevent9h.yaml +++ b/arch/csr/Zihpm/mhpmevent9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent9h diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index c14c19331..9e667159d 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -40,7 +40,6 @@ fields: [when,"VSXLEN = 64"] Because the implementation only supports a single VSXLEN == 64, this field is read-only-1. - type(): | if ((VSXLEN == 32) || (VSXLEN == 64)) { return CsrFieldType::RO; diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index a097a3f0e..11b8b07d5 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -1,6 +1,5 @@ # yaml-language-server: $schema=../../schemas/csr_schema.json - $schema: "csr_schema.json#" kind: csr name: mcause diff --git a/arch/csr/mconfigptr.yaml b/arch/csr/mconfigptr.yaml index 49fad5cc8..571d16d15 100644 --- a/arch/csr/mconfigptr.yaml +++ b/arch/csr/mconfigptr.yaml @@ -36,7 +36,6 @@ description: | M-mode software towards the beginning of the boot process. ==== - priv_mode: M length: MXLEN definedBy: diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index dab340dce..9318f9d3d 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -11,13 +11,13 @@ definedBy: # after 1.9.1, mideleg does not exist whe S-mode is not implemented # we can represent that by making mideleg an S extension CSR post 1.9.1 oneOf: - - name: Sm - version: "<= 1.9.1" - - allOf: - - name: S - version: "> 1.9.1" - name: Sm - version: "> 1.9.1" + version: "<= 1.9.1" + - allOf: + - name: S + version: "> 1.9.1" + - name: Sm + version: "> 1.9.1" description: | Controls exception delegation from M-mode to HS/S-mode diff --git a/arch/csr/mie.yaml b/arch/csr/mie.yaml index 927ed583c..2356afcd4 100644 --- a/arch/csr/mie.yaml +++ b/arch/csr/mie.yaml @@ -7,9 +7,147 @@ long_name: Machine Interrupt Enable address: 0x304 priv_mode: M length: MXLEN -definedBy: Sm -description: - $copy: "mip.yaml#/description" +definedBy: I +description: | + Per-type interrupt enables. + + For a detailed description of interrupt handling, see <%= link_to(:section, 'sec:interrupts') %>. + + The `mie` register is an + MXLEN-bit read/write register containing interrupt enable bits. + Interrupt cause number _i_ (as reported in CSR `mcause`) corresponds with + bit _i_ in + `mie`. Bits 15:0 are allocated to standard interrupt causes only, while + bits 16 and above are designated for platform use. + + NOTE: Interrupts designated for platform use may be designated for custom use + at the platform's discretion. + + An interrupt _i_ will trap to M-mode (causing the privilege mode to + change to M-mode) if all of the following are true: + + * either the current privilege mode is M and the MIE bit in the + `mstatus` register is set, or the current privilege mode has less + privilege than M-mode; + * bit _i_ is set in both `mip` and `mie`; + * if register `mideleg` exists, bit _i_ is not set in `mideleg`. + + These conditions for an interrupt trap to occur must be evaluated in a + bounded amount of time from when an interrupt becomes, or ceases to be, + pending in `mip`, and must also be evaluated immediately following the + execution of an __x__RET instruction or an explicit write to a CSR on + which these interrupt trap conditions expressly depend (including `mip`, + `mie`, `mstatus`, and `mideleg`). + + Interrupts to M-mode take priority over any interrupts to lower + privilege modes. + + A bit in `mie` must be writable if the corresponding interrupt can ever + become pending. Bits of `mie` that are not writable must be read-only + zero. + + [NOTE] + ==== + The machine-level interrupt registers handle a few root interrupt + sources which are assigned a fixed service priority for simplicity, + while separate external interrupt controllers can implement a more + complex prioritization scheme over a much larger set of interrupts that + are then muxed into the machine-level interrupt sources. + + ''' + + The non-maskable interrupt is not made visible via the `mip` register as + its presence is implicitly known when executing the NMI trap handler. + ==== + + If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are + the interrupt-pending and interrupt-enable bits for supervisor-level + external interrupts. SEIP is writable in `mip`, and may be written by + M-mode software to indicate to S-mode that an external interrupt is + pending. Additionally, the platform-level interrupt controller may + generate supervisor-level external interrupts. Supervisor-level external + interrupts are made pending based on the logical-OR of the + software-writable SEIP bit and the signal from the external interrupt + controller. When `mip` is read with a CSR instruction, the value of the + SEIP bit returned in the `rd` destination register is the logical-OR of + the software-writable bit and the interrupt signal from the interrupt + controller, but the signal from the interrupt controller is not used to + calculate the value written to SEIP. Only the software-writable SEIP bit + participates in the read-modify-write sequence of a CSRRS or CSRRC + instruction. + + [NOTE] + ==== + For example, if we name the software-writable SEIP bit `B` and the + signal from the external interrupt controller `E`, then if + `csrrs t0, mip, t1` is executed, `t0[9]` is written with `B || E`, then + `B` is written with `B || t1[9]`. If `csrrw t0, mip, t1` is executed, + then `t0[9]` is written with `B || E`, and `B` is simply written with + `t1[9]`. In neither case does `B` depend upon `E`. + + The SEIP field behavior is designed to allow a higher privilege layer to + mimic external interrupts cleanly, without losing any real external + interrupts. The behavior of the CSR instructions is slightly modified + from regular CSR accesses as a result. + ==== + + If supervisor mode is implemented, bits `mip`.STIP and `mie`.STIE are + the interrupt-pending and interrupt-enable bits for supervisor-level + timer interrupts. STIP is writable in `mip`, and may be written by + M-mode software to deliver timer interrupts to S-mode. + + If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are + the interrupt-pending and interrupt-enable bits for supervisor-level + software interrupts. SSIP is writable in `mip` and may also be set to 1 + by a platform-specific interrupt controller. + + <%- if ext?(:Sscofpmf) -%> + Bits `mip`.LCOFIP and `mie`.LCOFIE + are the interrupt-pending and interrupt-enable bits for local counter-overflow + interrupts. + LCOFIP is read-write in `mip` and reflects the occurrence of a local + counter-overflow overflow interrupt request resulting from any of the + `mhpmevent__n__`.OF bits being set. + If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are + read-only zeros. + <%- end -%> + + Multiple simultaneous interrupts destined for M-mode are handled in the + following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI. + + [NOTE] + ==== + The machine-level interrupt fixed-priority ordering rules were developed + with the following rationale. + + Interrupts for higher privilege modes must be serviced before interrupts + for lower privilege modes to support preemption. + + The platform-specific machine-level interrupt sources in bits 16 and + above have platform-specific priority, but are typically chosen to have + the highest service priority to support very fast local vectored + interrupts. + + External interrupts are handled before internal (timer/software) + interrupts as external interrupts are usually generated by devices that + might require low interrupt service times. + + Software interrupts are handled before internal timer interrupts, + because internal timer interrupts are usually intended for time slicing, + where time precision is less important, whereas software interrupts are + used for inter-processor messaging. Software interrupts can be avoided + when high-precision timing is required, or high-precision timer + interrupts can be routed via a different interrupt path. Software + interrupts are located in the lowest four bits of `mip` as these are + often written by software, and this position allows the use of a single + CSR instruction with a five-bit immediate. + ==== + + Restricted views of the `mip` and `mie` registers appear as the `sip` + and `sie` registers for supervisor level. If an interrupt is delegated + to S-mode by setting a bit in the `mideleg` register, it becomes visible + in the `sip` register and is maskable using the `sie` register. + Otherwise, the corresponding bits in `sip` and `sie` are read-only zero. fields: SSIE: location: 1 diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index f496aa1ac..54e0e7aaf 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -24,7 +24,7 @@ fields: Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state. definedBy: - anyOf: [F,V] # NOTE: if you implement a custom extension overlay that writes to XS, then you need to add your extension here in the overlay as well + anyOf: [F, V] # NOTE: if you implement a custom extension overlay that writes to XS, then you need to add your extension here in the overlay as well type(): | # this is read-only if FS and VS are both read-only # otherwise, it is read-only with hardware update diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index 2e0e58559..c206cd60d 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -1,6 +1,5 @@ # yaml-language-server: $schema=../../schemas/csr_schema.json - $schema: "csr_schema.json#" kind: csr name: scause diff --git a/arch/ext/A.yaml b/arch/ext/A.yaml index f72416a5b..ec0ee8408 100644 --- a/arch/ext/A.yaml +++ b/arch/ext/A.yaml @@ -9,16 +9,16 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "2.1.0" - state: ratified - ratification_date: 2019-12 - contributors: - - name: Unknown - email: unknown@void.segfault - company: Unknown - implies: - - [Zaamo, "1.0.0"] - - [Zalrsc, "1.0.0"] + - version: "2.1.0" + state: ratified + ratification_date: 2019-12 + contributors: + - name: Unknown + email: unknown@void.segfault + company: Unknown + implies: + - [Zaamo, "1.0.0"] + - [Zalrsc, "1.0.0"] description: | The atomic-instruction extension, named `A`, contains @@ -87,10 +87,10 @@ params: schema: type: string enum: - - reserve naturally-aligned 64-byte region - - reserve naturally-aligned 128-byte region - - reserve exactly enough to cover the access - - custom + - reserve naturally-aligned 64-byte region + - reserve naturally-aligned 128-byte region + - reserve exactly enough to cover the access + - custom LRSC_FAIL_ON_VA_SYNONYM: description: | Whether or not an `sc.l`/`sc.d` will fail if its VA does not match the VA of the prior @@ -107,9 +107,9 @@ params: schema: type: string enum: - - always raise misaligned exception - - always raise access fault - - custom + - always raise misaligned exception + - always raise access fault + - custom LRSC_FAIL_ON_NON_EXACT_LRSC: description: | Whether or not a Store Conditional fails if its physical address and size do not diff --git a/arch/ext/B.yaml b/arch/ext/B.yaml index b7eac4986..51b7928c0 100644 --- a/arch/ext/B.yaml +++ b/arch/ext/B.yaml @@ -12,18 +12,18 @@ doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 - contributors: - - name: Ved Shanbhogue - email: ved@rivosinc.com - company: Rivos, Inc. - url: https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view - implies: - - [Zba, "1.0.0"] - - [Zbb, "1.0.0"] - - [Zbs, "1.0.0"] + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 + contributors: + - name: Ved Shanbhogue + email: ved@rivosinc.com + company: Rivos, Inc. + url: https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view + implies: + - [Zba, "1.0.0"] + - [Zbb, "1.0.0"] + - [Zbs, "1.0.0"] description: | The B standard extension comprises instructions provided by the `Zba`, `Zbb`, and `Zbs` extensions. diff --git a/arch/ext/C.yaml b/arch/ext/C.yaml index 4559fa8c6..6020da884 100644 --- a/arch/ext/C.yaml +++ b/arch/ext/C.yaml @@ -12,9 +12,9 @@ doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 description: | The `C` extension reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. The C diff --git a/arch/ext/D.yaml b/arch/ext/D.yaml index a99778999..849ee0042 100644 --- a/arch/ext/D.yaml +++ b/arch/ext/D.yaml @@ -6,12 +6,12 @@ name: D type: unprivileged long_name: Double-precision floating-point versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 - changes: - - Define NaN-boxing scheme, changed definition of FMAX and FMIN - implies: [F, "2.2.0"] + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 + changes: + - Define NaN-boxing scheme, changed definition of FMAX and FMIN + implies: [F, "2.2.0"] description: | The `D` extension adds double-precision floating-point computational instructions compliant diff --git a/arch/ext/F.yaml b/arch/ext/F.yaml index fd45f3bcc..e24d2f257 100644 --- a/arch/ext/F.yaml +++ b/arch/ext/F.yaml @@ -6,11 +6,11 @@ name: F type: unprivileged long_name: Single-precision floating-point versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 - changes: - - Define NaN-boxing scheme, changed definition of FMAX and FMIN + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 + changes: + - Define NaN-boxing scheme, changed definition of FMAX and FMIN description: | This chapter describes the standard instruction-set extension for single-precision floating-point, which is named "F" and adds @@ -262,7 +262,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: S diff --git a/arch/ext/H.yaml b/arch/ext/H.yaml index 3ff99325b..e63b9863b 100644 --- a/arch/ext/H.yaml +++ b/arch/ext/H.yaml @@ -6,41 +6,41 @@ name: H type: privileged long_name: Hypervisor versions: -- version: "1.0.0" - state: ratified - ratification_date: 2019-12 - requires: - name: S - version: '>= 1.12.0' + - version: "1.0.0" + state: ratified + ratification_date: 2019-12 + requires: + name: S + version: ">= 1.12.0" interrupt_codes: -- num: 2 - name: Virtual supervisor software interrupt - var: VirtualSupervisorSoftware -- num: 6 - name: Virtual supervisor timer interrupt - var: VirtualSupervisorTimer -- num: 10 - name: Virtual supervisor external interrupt - var: VirtualSupervisorExternal -- num: 12 - name: Supervisor guest external interrupt - var: SupervisorGuestExternal + - num: 2 + name: Virtual supervisor software interrupt + var: VirtualSupervisorSoftware + - num: 6 + name: Virtual supervisor timer interrupt + var: VirtualSupervisorTimer + - num: 10 + name: Virtual supervisor external interrupt + var: VirtualSupervisorExternal + - num: 12 + name: Supervisor guest external interrupt + var: SupervisorGuestExternal exception_codes: -- num: 10 - name: Environment call from VS-mode - var: VScall -- num: 20 - name: Instruction guest page fault - var: InstructionGuestPageFault -- num: 21 - name: Load guest page fault - var: LoadGuestPageFault -- num: 22 - name: Virtual instruction - var: VirtualInstruction -- num: 23 - name: Store/AMO guest page fault - var: StoreAmoGuestPageFault + - num: 10 + name: Environment call from VS-mode + var: VScall + - num: 20 + name: Instruction guest page fault + var: InstructionGuestPageFault + - num: 21 + name: Load guest page fault + var: LoadGuestPageFault + - num: 22 + name: Virtual instruction + var: VirtualInstruction + - num: 23 + name: Store/AMO guest page fault + var: StoreAmoGuestPageFault description: | This chapter describes the RISC-V hypervisor extension, which virtualizes the supervisor-level architecture to support the efficient @@ -458,10 +458,10 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" - - "always transformed standard instruction" - - "custom" + - "always zero" + - "always pseudoinstruction" + - "always transformed standard instruction" + - "custom" TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT: description: | Value to write into htval/mtval2 when there is a guest page fault on a final translation. @@ -474,10 +474,10 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" - - "always transformed standard instruction" - - "custom" + - "always zero" + - "always pseudoinstruction" + - "always transformed standard instruction" + - "custom" TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT: description: | Value to write into htval/mtval2 when there is a guest page fault on a final translation. @@ -488,8 +488,8 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" + - "always zero" + - "always pseudoinstruction" TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst when there is an instruction address misaligned exception. @@ -500,8 +500,8 @@ params: schema: type: string enum: - - "always zero" - - "custom" + - "always zero" + - "custom" TINST_VALUE_ON_BREAKPOINT: description: | Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode. @@ -511,7 +511,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_VIRTUAL_INSTRUCTION: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -521,7 +521,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -532,7 +532,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_LOAD_ACCESS_FAULT: description: | Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. @@ -543,7 +543,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -554,7 +554,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT: description: | Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. @@ -565,7 +565,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_UCALL: description: | Value written into htinst/mtinst on a UCall exception from VU/VS-mode. @@ -575,7 +575,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_SCALL: description: | Value written into htinst/mtinst on a SCall exception from VU/VS-mode. @@ -585,7 +585,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_MCALL: description: | Value written into htinst/mtinst on a MCall exception from VU/VS-mode. @@ -595,7 +595,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_VSCALL: description: | Value written into htinst/mtinst on a VSCall exception from VU/VS-mode. @@ -605,7 +605,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_LOAD_PAGE_FAULT: description: | Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode. @@ -616,7 +616,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_PAGE_FAULT: description: | Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode. @@ -627,7 +627,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TRAP_ON_ECALL_FROM_VS: description: | Whether or not an ECALL-from-VS-mode causes a synchronous exception. diff --git a/arch/ext/I.yaml b/arch/ext/I.yaml index 31a0e9099..a7d919782 100644 --- a/arch/ext/I.yaml +++ b/arch/ext/I.yaml @@ -6,10 +6,10 @@ name: I type: unprivileged long_name: Base integer ISA (RV32I or RV64I) versions: -- version: "2.1.0" - state: ratified - ratification_date: 2019-06 - changes: - - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA + - version: "2.1.0" + state: ratified + ratification_date: 2019-06 + changes: + - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA description: | Base integer instructions -- TODO diff --git a/arch/ext/M.yaml b/arch/ext/M.yaml index 25f3af18b..5c5b3dff5 100644 --- a/arch/ext/M.yaml +++ b/arch/ext/M.yaml @@ -6,9 +6,9 @@ name: M type: unprivileged long_name: Integer multiply and divide instructions versions: -- version: "2.0.0" - state: ratified - ratification_date: 2019-12 + - version: "2.0.0" + state: ratified + ratification_date: 2019-12 description: | This chapter describes the standard integer multiplication and division instruction extension, which is named `M` and contains instructions diff --git a/arch/ext/MockExt.yaml b/arch/ext/MockExt.yaml index 57cc560d4..594bfbd4a 100644 --- a/arch/ext/MockExt.yaml +++ b/arch/ext/MockExt.yaml @@ -7,11 +7,11 @@ type: privileged long_name: Mock Extension (for testing database) description: This is just for testing versions: -- version: "0.9.9" - state: development -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "0.9.9" + state: development + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 params: MOCK_ENUM_2_INTS: description: foo @@ -148,8 +148,8 @@ params: schema: type: array items: - - const: false - - const: false + - const: false + - const: false additionalItems: type: boolean maxItems: 8 diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index 34e33bc92..d7fecf677 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -6,12 +6,12 @@ name: S type: privileged long_name: Supervisor mode versions: -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - requires: - name: U - version: "= 1.12.0" + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + requires: + name: U + version: "= 1.12.0" description: | This chapter describes the RISC-V supervisor-level architecture, which contains a common core that is used with various supervisor-level @@ -207,15 +207,13 @@ params: Whether or not `stvec.MODE` supports Direct (0). schema: type: boolean - extra_validation: - assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED + extra_validation: assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED STVEC_MODE_VECTORED: description: | Whether or not `stvec.MODE` supports Vectored (1). schema: type: boolean - extra_validation: - assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED + extra_validation: assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED SATP_MODE_BARE: description: | Whether or not satp.MODE == Bare is supported. @@ -245,8 +243,7 @@ params: schema: type: boolean default: false - extra_validation: - assert TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY == false if ext?(:Sv32) || ext?(:Sv39) || ext?(:Sv48) || ext?(:Sv57) + extra_validation: assert TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY == false if ext?(:Sv32) || ext?(:Sv39) || ext?(:Sv48) || ext?(:Sv57) MSTATUS_FS_WRITEABLE: description: | When `S` is enabled but `F` is not, mstatus.FS is optionally writeable. @@ -254,8 +251,7 @@ params: This parameter only has an effect when both S and F mode are disabled. schema: type: boolean - extra_validation: - assert MSTATUS_FS_WRITEABLE == true if ext?(:F) + extra_validation: assert MSTATUS_FS_WRITEABLE == true if ext?(:F) MSTATUS_VS_WRITEABLE: description: | When `S` is enabled but `V` is not, mstatus.VS is optionally writeable. @@ -263,8 +259,7 @@ params: This parameter only has an effect when both S and V mode are disabled. schema: type: boolean - extra_validation: - assert MSTATUS_VS_WRITEABLE == true if ext?(:V) + extra_validation: assert MSTATUS_VS_WRITEABLE == true if ext?(:V) MSTATUS_FS_LEGAL_VALUES: description: | The set of values that mstatus.FS will accept from a software write. @@ -272,7 +267,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: F @@ -285,7 +280,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: V diff --git a/arch/ext/Sm.yaml b/arch/ext/Sm.yaml index fdd3b5d35..db631b92f 100644 --- a/arch/ext/Sm.yaml +++ b/arch/ext/Sm.yaml @@ -6,90 +6,90 @@ name: Sm type: privileged long_name: Machine mode versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Moved Machine spec to *Ratified* status. - - Improvements to the description and commentary. - - Specified which interrupt sources are reserved for standard use. - - Allocated some synchronous exception causes for custom use. - - Specified the priority ordering of synchronous exceptions. - - Added specification that xRET instructions may, but are not required - to, clear LR reservations if A extension present. - - Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. - - Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*. - - Made the unused `misa` fields *WARL*, rather than *WIRI*. - - Rectified an editing error that misdescribed the mechanism by which - `mstatus.__x__IE` is written upon an exception. - - Described scheme for emulating misaligned AMOs. - - Specified the behavior of the `misa` and `__x__epc` registers in systems - with variable IALIGN. - - Specified the behavior of writing self-contradictory values to the - `misa` register. - - Specified contents of CSRs across XLEN modification. - - Moved PLIC chapter into its own document. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - Changed MRET to clear `mstatus`.MPRV when leaving M-mode. - - Relaxed I/O regions have been specified to follow RVWMO. The previous - specification implied that PPO rules other than fences and - acquire/release annotations did not apply. - - Constrained the LR/SC reservation set size and shape when using - page-based virtual memory. - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - Removed the N extension. - - Defined the mandatory RV32-only CSR `mstatush`, which contains most of - the same fields as the upper 32 bits of RV64's `mstatus`. - - Defined the mandatory CSR `mconfigptr`, which if nonzero contains the - address of a configuration data structure. - - Defined optional `mseccfg` and `mseccfgh` CSRs, which control the - machine's security configuration. - - Defined `menvcfg` CSR (and RV32-only `menvcfgh`), which control various characteristics - of the execution environment. - - Designated part of SYSTEM major opcode for custom use. - - Permitted the unconditional delegation of less-privileged interrupts. - - Added optional big-endian and bi-endian support. - - Made priority of load/store/AMO address-misaligned exceptions - implementation-defined relative to load/store/AMO page-fault and - access-fault exceptions. - - Software breakpoint exceptions are permitted to write either 0 or the - `pc` to `__x__tval`. - - Specified relaxed constraints for implicit reads of non-idempotent regions. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 - changes: - - Redefined `misa`.MXL to be read-only, making MXLEN a constant. - - Defined the `misa`.B field to reflect that the B extension has been - implemented. - - Defined the `misa`.V field to reflect that the V extension has been - implemented. - - Defined the RV32-only `medelegh` CSR. - - Defined the misaligned atomicity granule PMA, superseding the proposed Zam - extension. - - Defined hardware error and software check exception codes. - - Specified synchronization requirements when changing the PBMTE fields - in `menvcfg` and `henvcfg`. - - Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. - - Relaxed behavior of some HINTs when MXLEN > XLEN. - - Transliterated the document from LaTeX into AsciiDoc. - - Included all ratified extensions through March 2024. - - Clarified that "platform- or custom-use" interrupts are actually - "platform-use interrupts", where the platform can choose to make some custom. - - Clarified semantics of explicit accesses to CSRs wider than XLEN bits. - - Clarified that MXLEN≥SXLEN. - - Clarified that WFI is not a HINT instruction. - - Clarified that, for a given exception cause, `__x__tval` might sometimes - be set to a nonzero value but sometimes not. - - Clarified exception behavior of unimplemented or inaccessible CSRs. - - Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. - - Clarified that timer and count-overflow interrupts' arrival in - interrupt-pending registers is not immediate. - - Clarified that MXR affects only explicit memory accesses. + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Moved Machine spec to *Ratified* status. + - Improvements to the description and commentary. + - Specified which interrupt sources are reserved for standard use. + - Allocated some synchronous exception causes for custom use. + - Specified the priority ordering of synchronous exceptions. + - Added specification that xRET instructions may, but are not required + to, clear LR reservations if A extension present. + - Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. + - Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*. + - Made the unused `misa` fields *WARL*, rather than *WIRI*. + - Rectified an editing error that misdescribed the mechanism by which + `mstatus.__x__IE` is written upon an exception. + - Described scheme for emulating misaligned AMOs. + - Specified the behavior of the `misa` and `__x__epc` registers in systems + with variable IALIGN. + - Specified the behavior of writing self-contradictory values to the + `misa` register. + - Specified contents of CSRs across XLEN modification. + - Moved PLIC chapter into its own document. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - Changed MRET to clear `mstatus`.MPRV when leaving M-mode. + - Relaxed I/O regions have been specified to follow RVWMO. The previous + specification implied that PPO rules other than fences and + acquire/release annotations did not apply. + - Constrained the LR/SC reservation set size and shape when using + page-based virtual memory. + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - Removed the N extension. + - Defined the mandatory RV32-only CSR `mstatush`, which contains most of + the same fields as the upper 32 bits of RV64's `mstatus`. + - Defined the mandatory CSR `mconfigptr`, which if nonzero contains the + address of a configuration data structure. + - Defined optional `mseccfg` and `mseccfgh` CSRs, which control the + machine's security configuration. + - Defined `menvcfg` CSR (and RV32-only `menvcfgh`), which control various characteristics + of the execution environment. + - Designated part of SYSTEM major opcode for custom use. + - Permitted the unconditional delegation of less-privileged interrupts. + - Added optional big-endian and bi-endian support. + - Made priority of load/store/AMO address-misaligned exceptions + implementation-defined relative to load/store/AMO page-fault and + access-fault exceptions. + - Software breakpoint exceptions are permitted to write either 0 or the + `pc` to `__x__tval`. + - Specified relaxed constraints for implicit reads of non-idempotent regions. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 + changes: + - Redefined `misa`.MXL to be read-only, making MXLEN a constant. + - Defined the `misa`.B field to reflect that the B extension has been + implemented. + - Defined the `misa`.V field to reflect that the V extension has been + implemented. + - Defined the RV32-only `medelegh` CSR. + - Defined the misaligned atomicity granule PMA, superseding the proposed Zam + extension. + - Defined hardware error and software check exception codes. + - Specified synchronization requirements when changing the PBMTE fields + in `menvcfg` and `henvcfg`. + - Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. + - Relaxed behavior of some HINTs when MXLEN > XLEN. + - Transliterated the document from LaTeX into AsciiDoc. + - Included all ratified extensions through March 2024. + - Clarified that "platform- or custom-use" interrupts are actually + "platform-use interrupts", where the platform can choose to make some custom. + - Clarified semantics of explicit accesses to CSRs wider than XLEN bits. + - Clarified that MXLEN≥SXLEN. + - Clarified that WFI is not a HINT instruction. + - Clarified that, for a given exception cause, `__x__tval` might sometimes + be set to a nonzero value but sometimes not. + - Clarified exception behavior of unimplemented or inaccessible CSRs. + - Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. + - Clarified that timer and count-overflow interrupts' arrival in + interrupt-pending registers is not immediate. + - Clarified that MXR affects only explicit memory accesses. description: | This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware @@ -101,72 +101,72 @@ description: | contains a common core that is used with various supervisor-level address translation and protection schemes. interrupt_codes: -- num: 1 - name: Supervisor software interrupt - var: SupervisorSoftware -- num: 3 - name: Machine software interrupt - var: MachineSoftware -- num: 5 - name: Supervisor timer interrupt - var: SupervisorTimer -- num: 7 - name: Machine timer interrupt - var: MachineTimer -- num: 9 - name: Supervisor external interrupt - var: SupervisorExternal -- num: 11 - name: Machine external interrupt - var: MachineExternal + - num: 1 + name: Supervisor software interrupt + var: SupervisorSoftware + - num: 3 + name: Machine software interrupt + var: MachineSoftware + - num: 5 + name: Supervisor timer interrupt + var: SupervisorTimer + - num: 7 + name: Machine timer interrupt + var: MachineTimer + - num: 9 + name: Supervisor external interrupt + var: SupervisorExternal + - num: 11 + name: Machine external interrupt + var: MachineExternal exception_codes: -- num: 0 - name: Instruction address misaligned - var: InstructionAddressMisaligned -- num: 1 - name: Instruction access fault - var: InstructionAccessFault -- num: 2 - name: Illegal instruction - var: IllegalInstruction -- num: 3 - name: Breakpoint - var: Breakpoint -- num: 4 - name: Load address misaligned - var: LoadAddressMisaligned -- num: 5 - name: Load access fault - var: LoadAccessFault -- num: 6 - name: Store/AMO address misaligned - var: StoreAmoAddressMisaligned -- num: 7 - name: Store/AMO access fault - var: StoreAmoAccessFault -- num: 8 - name: Environment call from <%- if ext?(:H) -%>V<%- end -%>U-mode - var: Ucall -- num: 9 - name: Environment call from <%- if ext?(:H) -%>H<%- end -%>S-mode - var: Scall -- num: 11 - name: Environment call from M-mode - var: Mcall -- num: 12 - name: Instruction page fault - var: InstructionPageFault -- num: 13 - name: Load page fault - var: LoadPageFault -- num: 15 - name: Store/AMO page fault - var: StoreAmoPageFault -- num: 18 - name: Software Check - var: SoftwareCheck - when: - version: ">= 1.13.0" + - num: 0 + name: Instruction address misaligned + var: InstructionAddressMisaligned + - num: 1 + name: Instruction access fault + var: InstructionAccessFault + - num: 2 + name: Illegal instruction + var: IllegalInstruction + - num: 3 + name: Breakpoint + var: Breakpoint + - num: 4 + name: Load address misaligned + var: LoadAddressMisaligned + - num: 5 + name: Load access fault + var: LoadAccessFault + - num: 6 + name: Store/AMO address misaligned + var: StoreAmoAddressMisaligned + - num: 7 + name: Store/AMO access fault + var: StoreAmoAccessFault + - num: 8 + name: Environment call from <%- if ext?(:H) -%>V<%- end -%>U-mode + var: Ucall + - num: 9 + name: Environment call from <%- if ext?(:H) -%>H<%- end -%>S-mode + var: Scall + - num: 11 + name: Environment call from M-mode + var: Mcall + - num: 12 + name: Instruction page fault + var: InstructionPageFault + - num: 13 + name: Load page fault + var: LoadPageFault + - num: 15 + name: Store/AMO page fault + var: StoreAmoPageFault + - num: 18 + name: Software Check + var: SoftwareCheck + when: + version: ">= 1.13.0" params: XLEN: description: | diff --git a/arch/ext/Smaia.yaml b/arch/ext/Smaia.yaml index 5e696ae40..86ec96e02 100644 --- a/arch/ext/Smaia.yaml +++ b/arch/ext/Smaia.yaml @@ -7,7 +7,7 @@ long_name: Advanced Interrupt Architecture, M-mode extension description: Advanced Interrupt Architecture, M-mode extension type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-06 - url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf + - version: "1.0.0" + state: ratified + ratification_date: 2023-06 + url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf diff --git a/arch/ext/Smcdeleg.yaml b/arch/ext/Smcdeleg.yaml index 5979178c8..a1b603acb 100644 --- a/arch/ext/Smcdeleg.yaml +++ b/arch/ext/Smcdeleg.yaml @@ -14,24 +14,24 @@ doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: null - repositories: - - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/download/v1.0.0/riscv-smcdeleg-ssccfg-v1.0.0.pdf - contributors: - - name: Beeman Strong - email: beeman@rivosinc.com - company: Rivos, Inc. - - name: Atish Patra - email: atishp@rivosinc.com - company: Rivos, Inc. - - name: Allen Baum - email: allen.baum@esperantotech.com - company: Rivos, Inc. - - name: Greg Favor - email: gfavor@ventanamicro.com - company: Ventana Microsystems - - name: John Hauser - email: jh.riscv@jhauser.us + - version: "1.0.0" + state: ratified + ratification_date: null + repositories: + - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg + url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/download/v1.0.0/riscv-smcdeleg-ssccfg-v1.0.0.pdf + contributors: + - name: Beeman Strong + email: beeman@rivosinc.com + company: Rivos, Inc. + - name: Atish Patra + email: atishp@rivosinc.com + company: Rivos, Inc. + - name: Allen Baum + email: allen.baum@esperantotech.com + company: Rivos, Inc. + - name: Greg Favor + email: gfavor@ventanamicro.com + company: Ventana Microsystems + - name: John Hauser + email: jh.riscv@jhauser.us diff --git a/arch/ext/Smcntrpmf.yaml b/arch/ext/Smcntrpmf.yaml index 174269df0..a5c5fb5e9 100644 --- a/arch/ext/Smcntrpmf.yaml +++ b/arch/ext/Smcntrpmf.yaml @@ -7,7 +7,7 @@ long_name: Cycle and Instret Privilege Mode Filtering description: Cycle and Instret Privilege Mode Filtering type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf diff --git a/arch/ext/Smhpm.yaml b/arch/ext/Smhpm.yaml index fa2d63df3..6b31da57a 100644 --- a/arch/ext/Smhpm.yaml +++ b/arch/ext/Smhpm.yaml @@ -7,23 +7,23 @@ long_name: M-mode programmable hardware performance counters description: M-mode programmable hardware performance counters type: privileged versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Defined the `mcountinhibit` CSR, which stops performance counters from - incrementing to reduce energy consumption. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - PMP reset values are now platform-defined. - - An additional 48 optional PMP registers have been defined. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Defined the `mcountinhibit` CSR, which stops performance counters from + incrementing to reduce energy consumption. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - PMP reset values are now platform-defined. + - An additional 48 optional PMP registers have been defined. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 params: HPM_COUNTER_EN: description: | @@ -36,9 +36,9 @@ params: schema: type: array items: - - const: false - - const: false - - const: false + - const: false + - const: false + - const: false additionalItems: type: boolean maxItems: 32 @@ -66,9 +66,9 @@ params: schema: type: array items: - - type: boolean - - const: false - - type: boolean + - type: boolean + - const: false + - type: boolean additionalItems: type: boolean maxItems: 32 diff --git a/arch/ext/Smpmp.yaml b/arch/ext/Smpmp.yaml index 05e0ec654..5884987c8 100644 --- a/arch/ext/Smpmp.yaml +++ b/arch/ext/Smpmp.yaml @@ -6,23 +6,23 @@ name: Smpmp type: privileged long_name: Physical Memory Protection versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. - - Specified semantics for PMP regions coarser than four bytes. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - PMP reset values are now platform-defined. - - An additional 48 optional PMP registers have been defined. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. + - Specified semantics for PMP regions coarser than four bytes. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - PMP reset values are now platform-defined. + - An additional 48 optional PMP registers have been defined. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 description: | To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart. The optional PMP (Physical Memory Protection) unit diff --git a/arch/ext/Ssaia.yaml b/arch/ext/Ssaia.yaml index 09bdfe48d..028adb0fa 100644 --- a/arch/ext/Ssaia.yaml +++ b/arch/ext/Ssaia.yaml @@ -7,10 +7,10 @@ long_name: Advanced Interrupt Architecture, S-mode extension description: Advanced Interrupt Architecture, S-mode extension type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-06 - url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf - requires: - name: S - version: ">= 1.12" + - version: "1.0.0" + state: ratified + ratification_date: 2023-06 + url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf + requires: + name: S + version: ">= 1.12" diff --git a/arch/ext/Ssccfg.yaml b/arch/ext/Ssccfg.yaml index b19973dbc..d6425cc79 100644 --- a/arch/ext/Ssccfg.yaml +++ b/arch/ext/Ssccfg.yaml @@ -7,7 +7,7 @@ long_name: Supervisor-mode counter configuration description: Supervisor-mode counter configuration type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx diff --git a/arch/ext/Ssccptr.yaml b/arch/ext/Ssccptr.yaml index 247dc2b07..03a8ee5a8 100644 --- a/arch/ext/Ssccptr.yaml +++ b/arch/ext/Ssccptr.yaml @@ -11,13 +11,13 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. diff --git a/arch/ext/Sscofpmf.yaml b/arch/ext/Sscofpmf.yaml index 17fc12c9e..de4584f09 100644 --- a/arch/ext/Sscofpmf.yaml +++ b/arch/ext/Sscofpmf.yaml @@ -7,9 +7,9 @@ long_name: Counter Overflow and Privilege Mode Filtering description: Counter Overflow and Privilege Mode Filtering type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link - requires: - name: Smhpm + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link + requires: + name: Smhpm diff --git a/arch/ext/Sscounterenw.yaml b/arch/ext/Sscounterenw.yaml index 97f71aa81..b6a4b997a 100644 --- a/arch/ext/Sscounterenw.yaml +++ b/arch/ext/Sscounterenw.yaml @@ -11,11 +11,11 @@ description: | This extension was ratified with the RVA22 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link - param_constraints: - SCOUNTENABLE_EN: - extra_validation: | - HPM_COUNTER_EN.each_with_index { |hpm_exists, idx| assert(!hpm_exists || SCOUNTENABLE_EN[idx]) } + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link + param_constraints: + SCOUNTENABLE_EN: + extra_validation: | + HPM_COUNTER_EN.each_with_index { |hpm_exists, idx| assert(!hpm_exists || SCOUNTENABLE_EN[idx]) } diff --git a/arch/ext/Sstc.yaml b/arch/ext/Sstc.yaml index 435287d68..03f2b76e7 100644 --- a/arch/ext/Sstc.yaml +++ b/arch/ext/Sstc.yaml @@ -7,7 +7,7 @@ long_name: Superivisor mode timer interrupts description: Superivisor mode timer interrupts type: privileged versions: -- version: "0.9.0" - state: ratified - ratification_date: null - url: https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view?usp=drive_link + - version: "0.9.0" + state: ratified + ratification_date: null + url: https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view?usp=drive_link diff --git a/arch/ext/Sstvala.yaml b/arch/ext/Sstvala.yaml index 98e5fce73..66c8a101d 100644 --- a/arch/ext/Sstvala.yaml +++ b/arch/ext/Sstvala.yaml @@ -17,47 +17,47 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - param_constraints: - REPORT_VA_IN_STVAL_ON_BREAKPOINT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: - schema: - const: true - REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + param_constraints: + REPORT_VA_IN_STVAL_ON_BREAKPOINT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: + schema: + const: true + REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: + schema: + const: true diff --git a/arch/ext/Sstvecd.yaml b/arch/ext/Sstvecd.yaml index cbe35c0c1..c2a899c2b 100644 --- a/arch/ext/Sstvecd.yaml +++ b/arch/ext/Sstvecd.yaml @@ -10,17 +10,17 @@ description: | four-byte-aligned address. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - param_constraints: - STVEC_MODE_DIRECT: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + param_constraints: + STVEC_MODE_DIRECT: + schema: + const: true diff --git a/arch/ext/Sv32.yaml b/arch/ext/Sv32.yaml index 03ab2a2b1..e638dc938 100644 --- a/arch/ext/Sv32.yaml +++ b/arch/ext/Sv32.yaml @@ -7,7 +7,7 @@ long_name: 32-bit virtual address translation (3 level) description: 32-bit virtual address translation (3 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf diff --git a/arch/ext/Sv39.yaml b/arch/ext/Sv39.yaml index 35a1d74f3..bd54871df 100644 --- a/arch/ext/Sv39.yaml +++ b/arch/ext/Sv39.yaml @@ -7,7 +7,7 @@ long_name: 39-bit virtual address translation (3 level) description: 39-bit virtual address translation (3 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf diff --git a/arch/ext/Sv48.yaml b/arch/ext/Sv48.yaml index ac56935db..40b6416f6 100644 --- a/arch/ext/Sv48.yaml +++ b/arch/ext/Sv48.yaml @@ -7,10 +7,10 @@ long_name: 48-bit virtual address translation (4 level) description: 48-bit virtual address translation (4 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf - requires: - name: Sv39 - version: ">= 1.12" + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + requires: + name: Sv39 + version: ">= 1.12" diff --git a/arch/ext/Sv57.yaml b/arch/ext/Sv57.yaml index 49b4447d5..62f1d82a1 100644 --- a/arch/ext/Sv57.yaml +++ b/arch/ext/Sv57.yaml @@ -7,10 +7,10 @@ long_name: 57-bit virtual address translation (5 level) description: 57-bit virtual address translation (5 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf - requires: - name: Sv48 - version: ">= 1.12" + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + requires: + name: Sv48 + version: ">= 1.12" diff --git a/arch/ext/Svade.yaml b/arch/ext/Svade.yaml index 8dcbf4857..5ea7c4bd9 100644 --- a/arch/ext/Svade.yaml +++ b/arch/ext/Svade.yaml @@ -10,31 +10,31 @@ description: | during a page walk. Rather, encountering a PTE with the A bit clear or the D bit clear when an operation is a write will cause a Page Fault. versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-11 - url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf - repositories: - - url: https://github.com/riscvarchive/riscv-svadu - branch: main - contributors: - - name: Aaron Durbin - company: Rivos, Inc. - - name: Andrew Waterman - company: SiFive - - name: Earl Killian - company: Aril - - name: Greg Favor - company: Ventana - - name: John Ingalls - company: SiFive - - name: Ken Dockser - company: Tenstorrent - - name: Krste Asanovic - company: SiFive - - name: Paul Donahue - - name: Ved Shanbhogue - company: Rivos, Inc. + - version: "1.0.0" + state: ratified + ratification_date: 2023-11 + url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf + repositories: + - url: https://github.com/riscvarchive/riscv-svadu + branch: main + contributors: + - name: Aaron Durbin + company: Rivos, Inc. + - name: Andrew Waterman + company: SiFive + - name: Earl Killian + company: Aril + - name: Greg Favor + company: Ventana + - name: John Ingalls + company: SiFive + - name: Ken Dockser + company: Tenstorrent + - name: Krste Asanovic + company: SiFive + - name: Paul Donahue + - name: Ved Shanbhogue + company: Rivos, Inc. conflicts: Svadu doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) diff --git a/arch/ext/Svadu.yaml b/arch/ext/Svadu.yaml index 93202f732..d4fcbfdfa 100644 --- a/arch/ext/Svadu.yaml +++ b/arch/ext/Svadu.yaml @@ -93,31 +93,31 @@ description: | is zero, the implementation behaves as though Svadu were not implemented for VS-stage address translation. versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-11 - url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf - repositories: - - url: https://github.com/riscvarchive/riscv-svadu - branch: main - contributors: - - name: Aaron Durbin - company: Rivos, Inc. - - name: Andrew Waterman - company: SiFive - - name: Earl Killian - company: Aril - - name: Greg Favor - company: Ventana - - name: John Ingalls - company: SiFive - - name: Ken Dockser - company: Tenstorrent - - name: Krste Asanovic - company: SiFive - - name: Paul Donahue - - name: Ved Shanbhogue - company: Rivos, Inc. + - version: "1.0.0" + state: ratified + ratification_date: 2023-11 + url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf + repositories: + - url: https://github.com/riscvarchive/riscv-svadu + branch: main + contributors: + - name: Aaron Durbin + company: Rivos, Inc. + - name: Andrew Waterman + company: SiFive + - name: Earl Killian + company: Aril + - name: Greg Favor + company: Ventana + - name: John Ingalls + company: SiFive + - name: Ken Dockser + company: Tenstorrent + - name: Krste Asanovic + company: SiFive + - name: Paul Donahue + - name: Ved Shanbhogue + company: Rivos, Inc. conflicts: Svade doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) diff --git a/arch/ext/Svbare.yaml b/arch/ext/Svbare.yaml index afc684ac2..379238fcb 100644 --- a/arch/ext/Svbare.yaml +++ b/arch/ext/Svbare.yaml @@ -11,12 +11,12 @@ description: | [NOTE] This extension was ratified as part of the RVA22 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - requires: - name: S - param_constraints: - SATP_MODE_BARE: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + requires: + name: S + param_constraints: + SATP_MODE_BARE: + schema: + const: true diff --git a/arch/ext/Svinval.yaml b/arch/ext/Svinval.yaml index 1ebb07e06..c208c0adf 100644 --- a/arch/ext/Svinval.yaml +++ b/arch/ext/Svinval.yaml @@ -73,8 +73,8 @@ description: | `sfence.w.inval` and `sfence.inval.ir` instructions as no-ops. -- versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: S + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: S diff --git a/arch/ext/Svnapot.yaml b/arch/ext/Svnapot.yaml index 240f60cf7..d3fb8c3d5 100644 --- a/arch/ext/Svnapot.yaml +++ b/arch/ext/Svnapot.yaml @@ -168,8 +168,8 @@ description: | first step. ==== versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: Sv39 + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: Sv39 diff --git a/arch/ext/Svpbmt.yaml b/arch/ext/Svpbmt.yaml index 43db85e29..0cbc750e4 100644 --- a/arch/ext/Svpbmt.yaml +++ b/arch/ext/Svpbmt.yaml @@ -12,12 +12,12 @@ description: | This extension was ratified as part of the RVA22 profile. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - requires: - name: Sv39 - param_constraints: - SATP_MODE_BARE: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + requires: + name: Sv39 + param_constraints: + SATP_MODE_BARE: + schema: + const: true diff --git a/arch/ext/U.yaml b/arch/ext/U.yaml index a3a42d8de..40a7a0657 100644 --- a/arch/ext/U.yaml +++ b/arch/ext/U.yaml @@ -7,9 +7,9 @@ long_name: User-level privilege mode description: User-level privilege mode type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: 2019-12 + - version: "1.12.0" + state: ratified + ratification_date: 2019-12 params: MUTABLE_MISA_U: description: | diff --git a/arch/ext/V.yaml b/arch/ext/V.yaml index 462b12a6d..de7b3fe6d 100644 --- a/arch/ext/V.yaml +++ b/arch/ext/V.yaml @@ -6,9 +6,9 @@ name: V type: unprivileged long_name: Variable-length vector versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null description: | TODO params: @@ -38,7 +38,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: S diff --git a/arch/ext/Za128rs.yaml b/arch/ext/Za128rs.yaml index e78da5e68..24a232461 100644 --- a/arch/ext/Za128rs.yaml +++ b/arch/ext/Za128rs.yaml @@ -14,13 +14,13 @@ description: | The minimum reservation set size is effectively determined by the size of atomic accesses in the A extension. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - param_constraints: - LRSC_RESERVATION_STRATEGY: - schema: - oneOf: - - const: reserve exactly enough to cover the access - - const: reserve naturally-aligned 64-byte region - - const: reserve naturally-aligned 128-byte region + - version: "1.0.0" + state: ratified + ratification_date: null + param_constraints: + LRSC_RESERVATION_STRATEGY: + schema: + oneOf: + - const: reserve exactly enough to cover the access + - const: reserve naturally-aligned 64-byte region + - const: reserve naturally-aligned 128-byte region diff --git a/arch/ext/Zaamo.yaml b/arch/ext/Zaamo.yaml index 84722a566..42966feda 100644 --- a/arch/ext/Zaamo.yaml +++ b/arch/ext/Zaamo.yaml @@ -6,9 +6,9 @@ name: Zaamo long_name: Load-acquire/Store-release atomic instructions type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 description: | The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an diff --git a/arch/ext/Zalrsc.yaml b/arch/ext/Zalrsc.yaml index 90043522f..2be66d982 100644 --- a/arch/ext/Zalrsc.yaml +++ b/arch/ext/Zalrsc.yaml @@ -6,9 +6,9 @@ name: Zalrsc long_name: Atomic read-modify-write instructions type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 description: | Complex atomic memory operations on a single memory word or doubleword diff --git a/arch/ext/Zba.yaml b/arch/ext/Zba.yaml index 73b105806..de4642e66 100644 --- a/arch/ext/Zba.yaml +++ b/arch/ext/Zba.yaml @@ -23,41 +23,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbb.yaml b/arch/ext/Zbb.yaml index 747b4f74e..dbf92908c 100644 --- a/arch/ext/Zbb.yaml +++ b/arch/ext/Zbb.yaml @@ -11,41 +11,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbc.yaml b/arch/ext/Zbc.yaml index 1668b2042..bfcc8e774 100644 --- a/arch/ext/Zbc.yaml +++ b/arch/ext/Zbc.yaml @@ -11,41 +11,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbs.yaml b/arch/ext/Zbs.yaml index b7aee60c7..5340c261a 100644 --- a/arch/ext/Zbs.yaml +++ b/arch/ext/Zbs.yaml @@ -15,42 +15,42 @@ doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - url: https://drive.google.com/drive/u/0/folders/1_wqb-rXOVkGa6rqmugN3kwCftWDf1daU - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + url: https://drive.google.com/drive/u/0/folders/1_wqb-rXOVkGa6rqmugN3kwCftWDf1daU + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zcb.yaml b/arch/ext/Zcb.yaml index ccd0012fc..df46dc60e 100644 --- a/arch/ext/Zcb.yaml +++ b/arch/ext/Zcb.yaml @@ -18,25 +18,25 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-04 - repositories: - - url: https://github.com/riscv/riscv-code-size-reduction - branch: main - contributors: - - name: Tariq Kurd - - name: Ibrahim Abu Kharmeh - - name: Torbjørn Viem Ness - - name: Matteo Perotti - - name: Nidal Faour - - name: Bill Traynor - - name: Rafael Sene - - name: Xinlong Wu - - name: sinan - - name: Jeremy Bennett - - name: Heda Chen - - name: Alasdair Armstrong - - name: Graeme Smecher - - name: Nicolas Brunie - - name: Jiawei + - version: "1.0.0" + state: ratified + ratification_date: 2023-04 + repositories: + - url: https://github.com/riscv/riscv-code-size-reduction + branch: main + contributors: + - name: Tariq Kurd + - name: Ibrahim Abu Kharmeh + - name: Torbjørn Viem Ness + - name: Matteo Perotti + - name: Nidal Faour + - name: Bill Traynor + - name: Rafael Sene + - name: Xinlong Wu + - name: sinan + - name: Jeremy Bennett + - name: Heda Chen + - name: Alasdair Armstrong + - name: Graeme Smecher + - name: Nicolas Brunie + - name: Jiawei diff --git a/arch/ext/Zfhmin.yaml b/arch/ext/Zfhmin.yaml index 024f43efa..e51b3d183 100644 --- a/arch/ext/Zfhmin.yaml +++ b/arch/ext/Zfhmin.yaml @@ -44,9 +44,9 @@ description: | ==== type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: F - version: ">= 2.2" + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: F + version: ">= 2.2" diff --git a/arch/ext/Zic64b.yaml b/arch/ext/Zic64b.yaml index 15395d5ec..3e09eff3a 100644 --- a/arch/ext/Zic64b.yaml +++ b/arch/ext/Zic64b.yaml @@ -11,22 +11,22 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - requires: - anyOf: - - name: Zicbom - - name: Zicboz - - name: Zicbop - param_constraints: - CACHE_BLOCK_SIZE: - schema: - const: 64 + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + requires: + anyOf: + - name: Zicbom + - name: Zicboz + - name: Zicbop + param_constraints: + CACHE_BLOCK_SIZE: + schema: + const: 64 diff --git a/arch/ext/Zicbom.yaml b/arch/ext/Zicbom.yaml index 23206267c..f874010f7 100644 --- a/arch/ext/Zicbom.yaml +++ b/arch/ext/Zicbom.yaml @@ -7,9 +7,9 @@ long_name: Cache block management instructions description: Cache block management instructions type: unprivileged versions: -- version: "1.0.1-b34ea8a" - state: ratified - ratification_date: 2022-05 + - version: "1.0.1-b34ea8a" + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Zicbop.yaml b/arch/ext/Zicbop.yaml index 3cd9c3d01..50fa8e862 100644 --- a/arch/ext/Zicbop.yaml +++ b/arch/ext/Zicbop.yaml @@ -7,9 +7,9 @@ long_name: Cache block prefetch description: Cache block prefetch instruction type: unprivileged versions: -- version: 1.0.1-b34ea8a - state: ratified - ratification_date: 2022-05 + - version: 1.0.1-b34ea8a + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Zicboz.yaml b/arch/ext/Zicboz.yaml index 343b25baf..c3ce2ab69 100644 --- a/arch/ext/Zicboz.yaml +++ b/arch/ext/Zicboz.yaml @@ -7,9 +7,9 @@ long_name: Cache block zero instruction description: Cache block zero instruction type: unprivileged versions: -- version: 1.0.1-b34ea8a - state: ratified - ratification_date: 2022-05 + - version: 1.0.1-b34ea8a + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Ziccamoa.yaml b/arch/ext/Ziccamoa.yaml index 838438db1..ceea8fe11 100644 --- a/arch/ext/Ziccamoa.yaml +++ b/arch/ext/Ziccamoa.yaml @@ -10,6 +10,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Ziccif.yaml b/arch/ext/Ziccif.yaml index 4a35d7b00..69d7e3240 100644 --- a/arch/ext/Ziccif.yaml +++ b/arch/ext/Ziccif.yaml @@ -12,6 +12,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zicclsm.yaml b/arch/ext/Zicclsm.yaml index 835e91223..9eae9b58a 100644 --- a/arch/ext/Zicclsm.yaml +++ b/arch/ext/Zicclsm.yaml @@ -18,10 +18,10 @@ description: | Standard software distributions should assume their existence only for correctness, not for performance. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - param_constraints: - MISALIGNED_LDST: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + param_constraints: + MISALIGNED_LDST: + schema: + const: true diff --git a/arch/ext/Ziccrse.yaml b/arch/ext/Ziccrse.yaml index 93e7539b8..f73fc4f39 100644 --- a/arch/ext/Ziccrse.yaml +++ b/arch/ext/Ziccrse.yaml @@ -10,6 +10,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zicfilp.yaml b/arch/ext/Zicfilp.yaml index 27613044c..a13771176 100644 --- a/arch/ext/Zicfilp.yaml +++ b/arch/ext/Zicfilp.yaml @@ -6,9 +6,9 @@ description: | TODO type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-07 + - version: "1.0.0" + state: ratified + ratification_date: 2024-07 params: REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK: description: | diff --git a/arch/ext/Zicfiss.yaml b/arch/ext/Zicfiss.yaml index 41c0b0e6c..0bd011bfb 100644 --- a/arch/ext/Zicfiss.yaml +++ b/arch/ext/Zicfiss.yaml @@ -8,9 +8,9 @@ description: | TODO type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-07 + - version: "1.0.0" + state: ratified + ratification_date: 2024-07 params: REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK: description: | diff --git a/arch/ext/Zicntr.yaml b/arch/ext/Zicntr.yaml index 85f2ce5e2..e709f094e 100644 --- a/arch/ext/Zicntr.yaml +++ b/arch/ext/Zicntr.yaml @@ -7,12 +7,12 @@ long_name: Architectural performance counters description: Architectural performance counters type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: 2019-12 - requires: - name: Zicsr - version: ">= 2.0" + - version: "2.0.0" + state: ratified + ratification_date: 2019-12 + requires: + name: Zicsr + version: ">= 2.0" params: TIME_CSR_IMPLEMENTED: description: | diff --git a/arch/ext/Zicsr.yaml b/arch/ext/Zicsr.yaml index 92689331a..1cc2ec2b2 100644 --- a/arch/ext/Zicsr.yaml +++ b/arch/ext/Zicsr.yaml @@ -7,6 +7,6 @@ long_name: Control and status registers description: Control and status registers type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zifencei.yaml b/arch/ext/Zifencei.yaml index 7b661769b..d13473028 100644 --- a/arch/ext/Zifencei.yaml +++ b/arch/ext/Zifencei.yaml @@ -67,6 +67,6 @@ description: | ==== type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zihintpause.yaml b/arch/ext/Zihintpause.yaml index 06db29627..7bbe10de9 100644 --- a/arch/ext/Zihintpause.yaml +++ b/arch/ext/Zihintpause.yaml @@ -68,6 +68,6 @@ description: | ==== type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zihpm.yaml b/arch/ext/Zihpm.yaml index f7ec3b9ba..c5922e781 100644 --- a/arch/ext/Zihpm.yaml +++ b/arch/ext/Zihpm.yaml @@ -7,8 +7,8 @@ long_name: Programmable hardware performance counters description: Programmable hardware performance counters type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: unknown - requires: - name: Smhpm + - version: "2.0.0" + state: ratified + ratification_date: unknown + requires: + name: Smhpm diff --git a/arch/ext/Zkt.yaml b/arch/ext/Zkt.yaml index d5946dd45..4db84b276 100644 --- a/arch/ext/Zkt.yaml +++ b/arch/ext/Zkt.yaml @@ -335,28 +335,28 @@ description: | type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - contributors: - - name: Alexander Zeh - - name: Andy Glew - - name: Barry Spinney - - name: Ben Marshall - email: benmarshall@pqshield.com - - name: Daniel Page - - name: Derek Atkins - - name: Ken Dockser - - name: Markku-Juhani O. Saarinen - - name: Nathan Menhorn - - name: L Peter Deutsch - - name: Richard Newell - - name: Claire Wolf -- version: 1.0.1 - state: ratified - ratification_date: null - changes: - - Fix typos to show that `c.srli`, `c.srai`, and `c.slli` are Zkt instructions in RV64. + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + contributors: + - name: Alexander Zeh + - name: Andy Glew + - name: Barry Spinney + - name: Ben Marshall + email: benmarshall@pqshield.com + - name: Daniel Page + - name: Derek Atkins + - name: Ken Dockser + - name: Markku-Juhani O. Saarinen + - name: Nathan Menhorn + - name: L Peter Deutsch + - name: Richard Newell + - name: Claire Wolf + - version: 1.0.1 + state: ratified + ratification_date: null + changes: + - Fix typos to show that `c.srli`, `c.srai`, and `c.slli` are Zkt instructions in RV64. company: name: RISC-V International url: https://riscv.org diff --git a/arch/ext/Zmmul.yaml b/arch/ext/Zmmul.yaml index 1d52348e2..aef4c684a 100644 --- a/arch/ext/Zmmul.yaml +++ b/arch/ext/Zmmul.yaml @@ -20,6 +20,6 @@ description: | implemented in soft logic. type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2022-06 + - version: "1.0.0" + state: ratified + ratification_date: 2022-06 diff --git a/arch/inst/A/amoadd.d.yaml b/arch/inst/A/amoadd.d.yaml index 3d7c6b529..d0eb0ce3f 100644 --- a/arch/inst/A/amoadd.d.yaml +++ b/arch/inst/A/amoadd.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoadd.d long_name: Atomic fetch-and-add doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Add the value of register _rs2_ to the loaded value - * Write the sum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Add the value of register _rs2_ to the loaded value + * Write the sum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xs1) encoding: match: 00000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Add, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoadd.w.yaml b/arch/inst/A/amoadd.w.yaml index 81938edbd..f4178c0c0 100644 --- a/arch/inst/A/amoadd.w.yaml +++ b/arch/inst/A/amoadd.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoadd.w long_name: Atomic fetch-and-add word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Add the least-significant word of register _rs2_ to the loaded value - * Write the sum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Add the least-significant word of register _rs2_ to the loaded value + * Write the sum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Add, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoand.d.yaml b/arch/inst/A/amoand.d.yaml index 3d12556b3..dd945113d 100644 --- a/arch/inst/A/amoand.d.yaml +++ b/arch/inst/A/amoand.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoand.d long_name: Atomic fetch-and-and doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * AND the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * AND the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 01100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::And, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoand.w.yaml b/arch/inst/A/amoand.w.yaml index 512501131..a941de7be 100644 --- a/arch/inst/A/amoand.w.yaml +++ b/arch/inst/A/amoand.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoand.w long_name: Atomic fetch-and-and word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * AND the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * AND the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 01100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::And, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomax.d.yaml b/arch/inst/A/amomax.d.yaml index c223bf017..ddc0d1222 100644 --- a/arch/inst/A/amomax.d.yaml +++ b/arch/inst/A/amomax.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomax.d long_name: Atomic MAX doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 10100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Max, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomax.w.yaml b/arch/inst/A/amomax.w.yaml index 2f4602c7d..c7a4d71f9 100644 --- a/arch/inst/A/amomax.w.yaml +++ b/arch/inst/A/amomax.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomax.w long_name: Atomic MAX word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 10100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Max, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomaxu.d.yaml b/arch/inst/A/amomaxu.d.yaml index 821ea8ea7..96ba6b0df 100644 --- a/arch/inst/A/amomaxu.d.yaml +++ b/arch/inst/A/amomaxu.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomaxu.d long_name: Atomic MAX unsigned doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 11100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Maxu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomaxu.w.yaml b/arch/inst/A/amomaxu.w.yaml index 268abc22a..a5e4ab919 100644 --- a/arch/inst/A/amomaxu.w.yaml +++ b/arch/inst/A/amomaxu.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomaxu.w long_name: Atomic MAX unsigned word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 11100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Maxu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomin.d.yaml b/arch/inst/A/amomin.d.yaml index f111b4102..27ab36416 100644 --- a/arch/inst/A/amomin.d.yaml +++ b/arch/inst/A/amomin.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomin.d long_name: Atomic MIN doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value - * Write the minimum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value + * Write the minimum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 10000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Min, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomin.w.yaml b/arch/inst/A/amomin.w.yaml index b461a48f8..5b9fc763e 100644 --- a/arch/inst/A/amomin.w.yaml +++ b/arch/inst/A/amomin.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomin.w long_name: Atomic MIN word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 10000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Min, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amominu.d.yaml b/arch/inst/A/amominu.d.yaml index 3252fe812..7a1ef9855 100644 --- a/arch/inst/A/amominu.d.yaml +++ b/arch/inst/A/amominu.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amominu.d long_name: Atomic MIN unsigned doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value - * Write the minimum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value + * Write the minimum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 11000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Minu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amominu.w.yaml b/arch/inst/A/amominu.w.yaml index c5eba85a8..7860ced2e 100644 --- a/arch/inst/A/amominu.w.yaml +++ b/arch/inst/A/amominu.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amominu.w long_name: Atomic MIN unsigned word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 11000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Minu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoor.d.yaml b/arch/inst/A/amoor.d.yaml index bb4a019e0..bad4d513d 100644 --- a/arch/inst/A/amoor.d.yaml +++ b/arch/inst/A/amoor.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoor.d long_name: Atomic fetch-and-or doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * OR the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * OR the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 01000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Or, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoor.w.yaml b/arch/inst/A/amoor.w.yaml index bd31b909f..2791a551f 100644 --- a/arch/inst/A/amoor.w.yaml +++ b/arch/inst/A/amoor.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoor.w long_name: Atomic fetch-and-or word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * OR the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * OR the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 01000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Or, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoswap.d.yaml b/arch/inst/A/amoswap.d.yaml index e6f065534..10cccfede 100644 --- a/arch/inst/A/amoswap.d.yaml +++ b/arch/inst/A/amoswap.d.yaml @@ -5,11 +5,11 @@ kind: instruction name: amoswap.d long_name: Atomic SWAP doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the value into _rd_ - * Store the value of register _rs2_ to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the value into _rd_ + * Store the value of register _rs2_ to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -17,16 +17,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 00001------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Swap, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoswap.w.yaml b/arch/inst/A/amoswap.w.yaml index 152b663b6..5b03197eb 100644 --- a/arch/inst/A/amoswap.w.yaml +++ b/arch/inst/A/amoswap.w.yaml @@ -5,27 +5,27 @@ kind: instruction name: amoswap.w long_name: Atomic SWAP word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Store the least-significant word of register _rs2_ to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Store the least-significant word of register _rs2_ to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00001------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -42,8 +42,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Swap, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoxor.d.yaml b/arch/inst/A/amoxor.d.yaml index a47e9373c..d9c442659 100644 --- a/arch/inst/A/amoxor.d.yaml +++ b/arch/inst/A/amoxor.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoxor.d long_name: Atomic fetch-and-xor doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * XOR the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * XOR the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 00100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Xor, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoxor.w.yaml b/arch/inst/A/amoxor.w.yaml index 1c262bd09..e4bf3478a 100644 --- a/arch/inst/A/amoxor.w.yaml +++ b/arch/inst/A/amoxor.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoxor.w long_name: Atomic fetch-and-xor word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * XOR the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * XOR the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Xor, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/lr.d.yaml b/arch/inst/A/lr.d.yaml index 4844143e8..033d3be64 100644 --- a/arch/inst/A/lr.d.yaml +++ b/arch/inst/A/lr.d.yaml @@ -5,43 +5,43 @@ kind: instruction name: lr.d long_name: Load reserved doubleword description: | - Loads a word from the address in rs1, places the value in rd, - and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the - addressed word. + Loads a word from the address in rs1, places the value in rd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. - The address in rs1 must be 8-byte aligned. + The address in rs1 must be 8-byte aligned. - If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an - `LoadAccessFault` exception will be generated. The access-fault exception can be generated - for a memory access that would otherwise be able to complete except for the misalignment, - if the misaligned access should not be emulated. + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. - An implementation can register an arbitrarily large reservation set on each LR, provided the - reservation set includes all bytes of the addressed data word or doubleword. - An SC can only pair with the most recent LR in program order. - An SC may succeed only if no store from another hart to the reservation set can be - observed to have occurred between the LR and the SC, and if there is no other SC between the - LR and itself in program order. - An SC may succeed only if no write from a device other than a hart to the bytes accessed by - the LR instruction can be observed to have occurred between the LR and SC. Note this LR - might have had a different effective address and data size, but reserved the SC's - address as part of the reservation set. + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. - [NOTE] - ---- - Following this model, in systems with memory translation, an SC is allowed to succeed if the - earlier LR reserved the same location using an alias with a different virtual address, but is - also allowed to fail if the virtual address is different. + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. - To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only - required to invalidate reservations when they overlap the bytes accessed by the LR. - These writes are not required to invalidate the reservation when they access other bytes in - the reservation set. - ---- + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- - Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. - LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those - with both bits clear, but may result in lower performance. + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. definedBy: anyOf: [A, Zalrsc] base: 64 @@ -49,14 +49,14 @@ assembly: xd, xs1 encoding: match: 00010--00000-----011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -91,8 +91,6 @@ operation(): | X[rd] = load_reserved<32>(virtual_address, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/lr.w.yaml b/arch/inst/A/lr.w.yaml index 883fedf19..ca99cf80c 100644 --- a/arch/inst/A/lr.w.yaml +++ b/arch/inst/A/lr.w.yaml @@ -5,62 +5,62 @@ kind: instruction name: lr.w long_name: Load reserved word description: | - Loads a word from the address in rs1, places the sign-extended value in rd, - and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the - addressed word. + Loads a word from the address in rs1, places the sign-extended value in rd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. - <%- if XLEN == 64 -%> - The 32-bit load result is sign-extended to 64-bits. - <%- end -%> + <%- if XLEN == 64 -%> + The 32-bit load result is sign-extended to 64-bits. + <%- end -%> - The address in rs1 must be naturally aligned to the size of the operand - (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). + The address in rs1 must be naturally aligned to the size of the operand + (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). - If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an - `LoadAccessFault` exception will be generated. The access-fault exception can be generated - for a memory access that would otherwise be able to complete except for the misalignment, - if the misaligned access should not be emulated. + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. - An implementation can register an arbitrarily large reservation set on each LR, provided the - reservation set includes all bytes of the addressed data word or doubleword. - An SC can only pair with the most recent LR in program order. - An SC may succeed only if no store from another hart to the reservation set can be - observed to have occurred between the LR and the SC, and if there is no other SC between the - LR and itself in program order. - An SC may succeed only if no write from a device other than a hart to the bytes accessed by - the LR instruction can be observed to have occurred between the LR and SC. Note this LR - might have had a different effective address and data size, but reserved the SC's - address as part of the reservation set. + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. - [NOTE] - ---- - Following this model, in systems with memory translation, an SC is allowed to succeed if the - earlier LR reserved the same location using an alias with a different virtual address, but is - also allowed to fail if the virtual address is different. + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. - To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only - required to invalidate reservations when they overlap the bytes accessed by the LR. - These writes are not required to invalidate the reservation when they access other bytes in - the reservation set. - ---- + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- - Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. - LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those - with both bits clear, but may result in lower performance. + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. definedBy: anyOf: [A, Zalrsc] assembly: xd, xs1 encoding: match: 00010--00000-----010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -100,8 +100,6 @@ operation(): | X[rd] = sext(load_value[31:0], 32); } - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 3f55a4ec7..019117fb8 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -104,16 +104,16 @@ assembly: xd, xs2, xs1 encoding: match: 00011------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -150,8 +150,6 @@ operation(): | Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding); X[rd] = success ? 0 : 1; - - sail(): | { if speculate_conditional () == false then { diff --git a/arch/inst/A/sc.w.yaml b/arch/inst/A/sc.w.yaml index fc29cbc00..4519f59fe 100644 --- a/arch/inst/A/sc.w.yaml +++ b/arch/inst/A/sc.w.yaml @@ -110,16 +110,16 @@ assembly: xd, xs2, xs1 encoding: match: 00011------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -156,8 +156,6 @@ operation(): | Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding); X[rd] = success ? 0 : 1; - - sail(): | { if speculate_conditional () == false then { diff --git a/arch/inst/B/add.uw.yaml b/arch/inst/B/add.uw.yaml index f8aedbf6d..cf0ca7a24 100644 --- a/arch/inst/B/add.uw.yaml +++ b/arch/inst/B/add.uw.yaml @@ -14,20 +14,20 @@ assembly: xd, xs1, xs2 encoding: match: 0000100----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always vs: always vu: always pseudoinstructions: -- when: rs2 == 0 - to: zext.w xd, xs1 + - when: rs2 == 0 + to: zext.w xd, xs1 operation(): | if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { raise (ExceptionCode::IllegalInstruction, mode(), $encoding); @@ -35,8 +35,6 @@ operation(): | X[rd] = X[rs2] + X[rs1][31:0]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/andn.yaml b/arch/inst/B/andn.yaml index c377ce8a1..0b723e1ad 100644 --- a/arch/inst/B/andn.yaml +++ b/arch/inst/B/andn.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | X[rd] = X[rs2] & ~X[rs1]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bclr.yaml b/arch/inst/B/bclr.yaml index 03ebc50ba..5de87be7a 100644 --- a/arch/inst/B/bclr.yaml +++ b/arch/inst/B/bclr.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] & ~(1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bclri.yaml b/arch/inst/B/bclri.yaml index 7c270a899..17739413f 100644 --- a/arch/inst/B/bclri.yaml +++ b/arch/inst/B/bclri.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0100100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] & ~(1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bext.yaml b/arch/inst/B/bext.yaml index 92ea15b8f..4aafdd2d3 100644 --- a/arch/inst/B/bext.yaml +++ b/arch/inst/B/bext.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100100----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = (X[rs1] >> index) & 1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bexti.yaml b/arch/inst/B/bexti.yaml index 44b568785..1584b1af7 100644 --- a/arch/inst/B/bexti.yaml +++ b/arch/inst/B/bexti.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0100100----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = (X[rs1] >> index) & 1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/binv.yaml b/arch/inst/B/binv.yaml index 40262f63b..4d4af940d 100644 --- a/arch/inst/B/binv.yaml +++ b/arch/inst/B/binv.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] ^ (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/binvi.yaml b/arch/inst/B/binvi.yaml index ac23c5775..6e1edf9ba 100644 --- a/arch/inst/B/binvi.yaml +++ b/arch/inst/B/binvi.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0110100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] ^ (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bset.yaml b/arch/inst/B/bset.yaml index c0a5e0427..f3004636d 100644 --- a/arch/inst/B/bset.yaml +++ b/arch/inst/B/bset.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] | (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bseti.yaml b/arch/inst/B/bseti.yaml index 9b9e69307..56693a4a7 100644 --- a/arch/inst/B/bseti.yaml +++ b/arch/inst/B/bseti.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0010100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 001010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] | (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmul.yaml b/arch/inst/B/clmul.yaml index 73529d043..58c5a9fad 100644 --- a/arch/inst/B/clmul.yaml +++ b/arch/inst/B/clmul.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmulh.yaml b/arch/inst/B/clmulh.yaml index 44b695eaf..adae02b84 100644 --- a/arch/inst/B/clmulh.yaml +++ b/arch/inst/B/clmulh.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmulr.yaml b/arch/inst/B/clmulr.yaml index 7a4033f8a..a56b2b863 100644 --- a/arch/inst/B/clmulr.yaml +++ b/arch/inst/B/clmulr.yaml @@ -17,12 +17,12 @@ access: encoding: match: 0000101----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 operation(): | if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { raise (ExceptionCode::IllegalInstruction, mode(), $encoding); @@ -40,8 +40,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clz.yaml b/arch/inst/B/clz.yaml index 4349b7bda..38d9a6f3e 100644 --- a/arch/inst/B/clz.yaml +++ b/arch/inst/B/clz.yaml @@ -15,10 +15,10 @@ assembly: xd, xs1 encoding: match: 011000000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clzw.yaml b/arch/inst/B/clzw.yaml index d0ede84fc..8e3b006bd 100644 --- a/arch/inst/B/clzw.yaml +++ b/arch/inst/B/clzw.yaml @@ -15,10 +15,10 @@ assembly: xd, xs1 encoding: match: 011000000000-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = 31 - $signed(highest_set_bit(X[rs1][31:0])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/cpop.yaml b/arch/inst/B/cpop.yaml index cb9d5a6fe..6b4718098 100644 --- a/arch/inst/B/cpop.yaml +++ b/arch/inst/B/cpop.yaml @@ -24,10 +24,10 @@ assembly: xd, xs1 encoding: match: 011000000010-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | X[rd] = bitcount; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/cpopw.yaml b/arch/inst/B/cpopw.yaml index f061ae07b..94d298d73 100644 --- a/arch/inst/B/cpopw.yaml +++ b/arch/inst/B/cpopw.yaml @@ -25,10 +25,10 @@ assembly: xd, xs1 encoding: match: 011000000010-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -50,8 +50,6 @@ operation(): | X[rd] = bitcount; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/ctz.yaml b/arch/inst/B/ctz.yaml index d39a0f351..51305dbde 100644 --- a/arch/inst/B/ctz.yaml +++ b/arch/inst/B/ctz.yaml @@ -16,10 +16,10 @@ assembly: xd, xs1 encoding: match: 011000000001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(lowest_set_bit(X[rs1])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/ctzw.yaml b/arch/inst/B/ctzw.yaml index 97ac4ee96..1db05c84f 100644 --- a/arch/inst/B/ctzw.yaml +++ b/arch/inst/B/ctzw.yaml @@ -17,10 +17,10 @@ assembly: xd, xs1 encoding: match: 011000000001-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(lowest_set_bit(X[rs1][31:0])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/max.yaml b/arch/inst/B/max.yaml index aab174111..e483a3f54 100644 --- a/arch/inst/B/max.yaml +++ b/arch/inst/B/max.yaml @@ -20,12 +20,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | X[rd] = ($signed(X[rs1]) > $signed(X[rs2])) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/maxu.yaml b/arch/inst/B/maxu.yaml index d2cb26ff2..9bc665aaf 100644 --- a/arch/inst/B/maxu.yaml +++ b/arch/inst/B/maxu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = (X[rs1] > X[rs2]) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/min.yaml b/arch/inst/B/min.yaml index b7e838fd9..cd5fefc85 100644 --- a/arch/inst/B/min.yaml +++ b/arch/inst/B/min.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = ($signed(X[rs1]) < $signed(X[rs2])) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/minu.yaml b/arch/inst/B/minu.yaml index 3a0038c2c..1b6ace4e8 100644 --- a/arch/inst/B/minu.yaml +++ b/arch/inst/B/minu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = (X[rs1] < X[rs2]) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/orc.b.yaml b/arch/inst/B/orc.b.yaml index 6fdedd626..52ddd67be 100644 --- a/arch/inst/B/orc.b.yaml +++ b/arch/inst/B/orc.b.yaml @@ -14,10 +14,10 @@ assembly: xd, xs1, xs2 encoding: match: 001010000111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/orn.yaml b/arch/inst/B/orn.yaml index 50f45f0c4..3bd9e8642 100644 --- a/arch/inst/B/orn.yaml +++ b/arch/inst/B/orn.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = X[rs1] | ~X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rev8.yaml b/arch/inst/B/rev8.yaml index 950629425..f3a6702d5 100644 --- a/arch/inst/B/rev8.yaml +++ b/arch/inst/B/rev8.yaml @@ -21,17 +21,17 @@ encoding: RV32: match: 011010011000-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011010111000-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -55,8 +55,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rol.yaml b/arch/inst/B/rol.yaml index 251f039bf..6f166de0f 100644 --- a/arch/inst/B/rol.yaml +++ b/arch/inst/B/rol.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110000----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (X[rs1] << shamt) | (X[rs1] >> (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rolw.yaml b/arch/inst/B/rolw.yaml index daadd41df..070c001dc 100644 --- a/arch/inst/B/rolw.yaml +++ b/arch/inst/B/rolw.yaml @@ -14,12 +14,12 @@ base: 64 encoding: match: 0110000----------001-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/ror.yaml b/arch/inst/B/ror.yaml index 1d75f3112..df4dedf74 100644 --- a/arch/inst/B/ror.yaml +++ b/arch/inst/B/ror.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index e66453373..b8e7023bc 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -14,21 +14,21 @@ encoding: RV32: match: 0110000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/roriw.yaml b/arch/inst/B/roriw.yaml index df7da5ab3..7e23ce7aa 100644 --- a/arch/inst/B/roriw.yaml +++ b/arch/inst/B/roriw.yaml @@ -15,12 +15,12 @@ base: 64 encoding: match: 0110000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | XReg unextended_result = (X[rs1] >> shamt) | (X[rs1] << (32 - shamt)); X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/rorw.yaml b/arch/inst/B/rorw.yaml index 62f4036d1..1ef4e63fc 100644 --- a/arch/inst/B/rorw.yaml +++ b/arch/inst/B/rorw.yaml @@ -15,12 +15,12 @@ base: 64 encoding: match: 0110000----------101-----0111011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | XReg unextended_result = (X[rs1] >> shamt) | (X[rs1] << (32 - shamt)); X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/sext.b.yaml b/arch/inst/B/sext.b.yaml index a4d2a4bd4..84dfd40c4 100644 --- a/arch/inst/B/sext.b.yaml +++ b/arch/inst/B/sext.b.yaml @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 011000000100-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = {{56{X[rs1][7]}}, X[rs1][7:0]}; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sext.h.yaml b/arch/inst/B/sext.h.yaml index fe2054f4f..d7a3a59f0 100644 --- a/arch/inst/B/sext.h.yaml +++ b/arch/inst/B/sext.h.yaml @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 011000000101-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = {{48{X[rs1][15]}}, X[rs1][15:0]}; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh1add.uw.yaml b/arch/inst/B/sh1add.uw.yaml index 1d5ee5299..8883d4aa4 100644 --- a/arch/inst/B/sh1add.uw.yaml +++ b/arch/inst/B/sh1add.uw.yaml @@ -14,12 +14,12 @@ base: 64 encoding: match: 0010000----------010-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 assembly: xd, xs1, xs2 access: s: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 1); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh1add.yaml b/arch/inst/B/sh1add.yaml index 88c89a1e7..15f1e23d4 100644 --- a/arch/inst/B/sh1add.yaml +++ b/arch/inst/B/sh1add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 1); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh2add.uw.yaml b/arch/inst/B/sh2add.uw.yaml index 2256b8ff9..fd29fff5a 100644 --- a/arch/inst/B/sh2add.uw.yaml +++ b/arch/inst/B/sh2add.uw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 2); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh2add.yaml b/arch/inst/B/sh2add.yaml index e0c7e3cc5..02b3905e2 100644 --- a/arch/inst/B/sh2add.yaml +++ b/arch/inst/B/sh2add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 2); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh3add.uw.yaml b/arch/inst/B/sh3add.uw.yaml index 9cc2a29a0..d8b88d16b 100644 --- a/arch/inst/B/sh3add.uw.yaml +++ b/arch/inst/B/sh3add.uw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------110-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 3); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh3add.yaml b/arch/inst/B/sh3add.yaml index ace5749ef..0ceefa250 100644 --- a/arch/inst/B/sh3add.yaml +++ b/arch/inst/B/sh3add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 3); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/slli.uw.yaml b/arch/inst/B/slli.uw.yaml index 47c9d7d5d..4b5b11d83 100644 --- a/arch/inst/B/slli.uw.yaml +++ b/arch/inst/B/slli.uw.yaml @@ -16,12 +16,12 @@ base: 64 encoding: match: 000010-----------001-----0011011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 assembly: xd, xs1, shamt access: s: always @@ -35,8 +35,6 @@ operation(): | X[rd] = X[rs1][31:0] << shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/xnor.yaml b/arch/inst/B/xnor.yaml index fc64d5e2e..0afd1d30d 100644 --- a/arch/inst/B/xnor.yaml +++ b/arch/inst/B/xnor.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = ~(X[rs1] ^ X[rs2]); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/zext.h.yaml b/arch/inst/B/zext.h.yaml index 4e1b492f9..247db427c 100644 --- a/arch/inst/B/zext.h.yaml +++ b/arch/inst/B/zext.h.yaml @@ -19,19 +19,19 @@ encoding: RV32: match: 000010000000-----100-----0110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000010000000-----100-----0111011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 excludedBy: - anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented + anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented assembly: xd, xs1 access: s: always @@ -45,8 +45,6 @@ operation(): | X[rd] = X[rs1][15:0]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/C/c.add.yaml b/arch/inst/C/c.add.yaml index 678dfbb14..c2249358b 100644 --- a/arch/inst/C/c.add.yaml +++ b/arch/inst/C/c.add.yaml @@ -9,16 +9,16 @@ description: | C.ADD expands into `add rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 1001----------10 variables: - - name: rs2 - location: 6-2 - - name: rd - location: 11-7 + - name: rs2 + location: 6-2 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.addi.yaml b/arch/inst/C/c.addi.yaml index 445543b1b..6263e0c8f 100644 --- a/arch/inst/C/c.addi.yaml +++ b/arch/inst/C/c.addi.yaml @@ -11,18 +11,18 @@ description: | The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 000-----------01 variables: - - name: imm - location: 12|6-2 - not: 0 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + not: 0 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addi16sp.yaml b/arch/inst/C/c.addi16sp.yaml index 5b3e53196..78cc3d196 100644 --- a/arch/inst/C/c.addi16sp.yaml +++ b/arch/inst/C/c.addi16sp.yaml @@ -11,16 +11,16 @@ description: | C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 011-00010-----01 variables: - - name: imm - location: 12|4-3|5|2|6 - left_shift: 4 - not: 0 + - name: imm + location: 12|4-3|5|2|6 + left_shift: 4 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addi4spn.yaml b/arch/inst/C/c.addi4spn.yaml index d51063be9..3da786baf 100644 --- a/arch/inst/C/c.addi4spn.yaml +++ b/arch/inst/C/c.addi4spn.yaml @@ -11,18 +11,18 @@ description: | C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 000-----------00 variables: - - name: imm - location: 10-7|12-11|5|6 - left_shift: 2 - not: 0 - - name: rd - location: 4-2 + - name: imm + location: 10-7|12-11|5|6 + left_shift: 2 + not: 0 + - name: rd + location: 4-2 access: s: always u: always diff --git a/arch/inst/C/c.addiw.yaml b/arch/inst/C/c.addiw.yaml index a5c8220c9..d1c409584 100644 --- a/arch/inst/C/c.addiw.yaml +++ b/arch/inst/C/c.addiw.yaml @@ -11,18 +11,18 @@ description: | C.ADDIW is only valid when rd ≠ x0; the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm encoding: match: 001-----------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addw.yaml b/arch/inst/C/c.addw.yaml index 61ba1a41f..a78674a86 100644 --- a/arch/inst/C/c.addw.yaml +++ b/arch/inst/C/c.addw.yaml @@ -10,17 +10,17 @@ description: | C.ADDW expands into `addw rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, rs2 encoding: match: 100111---01---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.and.yaml b/arch/inst/C/c.and.yaml index 6f365559b..ba2648f0b 100644 --- a/arch/inst/C/c.and.yaml +++ b/arch/inst/C/c.and.yaml @@ -10,16 +10,16 @@ description: | C.AND expands into `and rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---11---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.andi.yaml b/arch/inst/C/c.andi.yaml index c32f5f8e7..3ef3ac838 100644 --- a/arch/inst/C/c.andi.yaml +++ b/arch/inst/C/c.andi.yaml @@ -10,16 +10,16 @@ description: | C.ANDI expands into `andi rd, rd, imm`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 100-10--------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 9-7 + - name: imm + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.beqz.yaml b/arch/inst/C/c.beqz.yaml index 75d88ee54..b831bdf36 100644 --- a/arch/inst/C/c.beqz.yaml +++ b/arch/inst/C/c.beqz.yaml @@ -9,17 +9,17 @@ description: | It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1, imm encoding: match: 110-----------01 variables: - - name: imm - location: 12|6-5|2|11-10|4-3 - left_shift: 0 - - name: rs1 - location: 9-7 + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 0 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.bnez.yaml b/arch/inst/C/c.bnez.yaml index 91ee35e96..aa4cb97a0 100644 --- a/arch/inst/C/c.bnez.yaml +++ b/arch/inst/C/c.bnez.yaml @@ -9,17 +9,17 @@ description: | It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1, imm encoding: match: 111-----------01 variables: - - name: imm - location: 12|6-5|2|11-10|4-3 - left_shift: 0 - - name: rs1 - location: 9-7 + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 0 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.ebreak.yaml b/arch/inst/C/c.ebreak.yaml index cb97f8058..09f19331d 100644 --- a/arch/inst/C/c.ebreak.yaml +++ b/arch/inst/C/c.ebreak.yaml @@ -19,8 +19,8 @@ description: | and should not increment the `minstret` CSR. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: " " encoding: match: "1001000000000010" diff --git a/arch/inst/C/c.fld.yaml b/arch/inst/C/c.fld.yaml index 4e2c54bca..f4672ed0e 100644 --- a/arch/inst/C/c.fld.yaml +++ b/arch/inst/C/c.fld.yaml @@ -11,19 +11,19 @@ description: | It expands to `fld` `rd, offset(rs1)`. definedBy: allOf: - - C - - D + - C + - D assembly: xd, imm(xs1) encoding: match: 001-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fldsp.yaml b/arch/inst/C/c.fldsp.yaml index da3ef66fa..beb226b79 100644 --- a/arch/inst/C/c.fldsp.yaml +++ b/arch/inst/C/c.fldsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fld` `rd, offset(x2)`. definedBy: allOf: - - C - - D + - C + - D assembly: fd, imm(sp) encoding: match: 001-----------10 variables: - - name: imm - location: 4-2|12|6-5 - left_shift: 3 - - name: rd - location: 11-7 + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.flw.yaml b/arch/inst/C/c.flw.yaml index e99c975c3..80165e98b 100644 --- a/arch/inst/C/c.flw.yaml +++ b/arch/inst/C/c.flw.yaml @@ -11,19 +11,19 @@ description: | It expands to `flw` `rd, offset(rs1)`. definedBy: allOf: - - C - - F + - C + - F assembly: xd, imm(xs1) encoding: match: 011-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.flwsp.yaml b/arch/inst/C/c.flwsp.yaml index a92007cee..0e50dbf1b 100644 --- a/arch/inst/C/c.flwsp.yaml +++ b/arch/inst/C/c.flwsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `flw` `rd, offset(x2)`. definedBy: allOf: - - C - - F + - C + - F assembly: fd, imm(sp) encoding: match: 011-----------10 variables: - - name: imm - location: 3-2|12|6-4 - left_shift: 2 - - name: rd - location: 11-7 + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.fsd.yaml b/arch/inst/C/c.fsd.yaml index b16493053..22a1c3785 100644 --- a/arch/inst/C/c.fsd.yaml +++ b/arch/inst/C/c.fsd.yaml @@ -11,19 +11,19 @@ description: | It expands to `fsd` `rs2, offset(rs1)`. definedBy: allOf: - - C - - D + - C + - D assembly: xs2, imm(xs1) encoding: match: 101-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fsdsp.yaml b/arch/inst/C/c.fsdsp.yaml index 61c5cb4d3..185240e2c 100644 --- a/arch/inst/C/c.fsdsp.yaml +++ b/arch/inst/C/c.fsdsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fsd` `rs2, offset(x2)`. definedBy: allOf: - - C - - D + - C + - D assembly: fs2, imm(sp) encoding: match: 101-----------10 variables: - - name: imm - location: 9-7|12-10 - left_shift: 3 - - name: rs2 - location: 6-2 + - name: imm + location: 9-7|12-10 + left_shift: 3 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.fsw.yaml b/arch/inst/C/c.fsw.yaml index b50f1f257..704652115 100644 --- a/arch/inst/C/c.fsw.yaml +++ b/arch/inst/C/c.fsw.yaml @@ -11,19 +11,19 @@ description: | It expands to `fsw` `rs2, offset(rs1)`. definedBy: allOf: - - C - - F + - C + - F assembly: xs2, imm(xs1) encoding: match: 111-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fswsp.yaml b/arch/inst/C/c.fswsp.yaml index e02c29024..37cca7c62 100644 --- a/arch/inst/C/c.fswsp.yaml +++ b/arch/inst/C/c.fswsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fsw` `rs2, offset(x2)`. definedBy: allOf: - - C - - F + - C + - F assembly: fs2, imm(sp) encoding: match: 111-----------10 variables: - - name: imm - location: 8-7|12-9 - left_shift: 2 - - name: rs2 - location: 6-2 + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.j.yaml b/arch/inst/C/c.j.yaml index 1a4ba8a41..d1fb316ee 100644 --- a/arch/inst/C/c.j.yaml +++ b/arch/inst/C/c.j.yaml @@ -9,16 +9,16 @@ description: | It expands to `jal` `x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 101-----------01 variables: - - name: imm - location: 12|8|10-9|6|7|2|11|5-3 - left_shift: 1 - sign_extend: true + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true access: s: always u: always diff --git a/arch/inst/C/c.jal.yaml b/arch/inst/C/c.jal.yaml index 2b168b001..6d397fcf0 100644 --- a/arch/inst/C/c.jal.yaml +++ b/arch/inst/C/c.jal.yaml @@ -9,17 +9,17 @@ description: | It expands to `jal` `x1, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 32 assembly: imm encoding: match: 001-----------01 variables: - - name: imm - location: 12|8|10-9|6|7|2|11|5-3 - left_shift: 1 - sign_extend: true + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true access: s: always u: always diff --git a/arch/inst/C/c.jalr.yaml b/arch/inst/C/c.jalr.yaml index 5865fceb4..a6cd9ada2 100644 --- a/arch/inst/C/c.jalr.yaml +++ b/arch/inst/C/c.jalr.yaml @@ -9,15 +9,15 @@ description: | C.JALR expands to jalr x1, 0(rs1). definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1 encoding: match: 1001-----0000010 variables: - - name: rs1 - location: 11-7 - not: 0 + - name: rs1 + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.jr.yaml b/arch/inst/C/c.jr.yaml index 97ede0638..18701146b 100644 --- a/arch/inst/C/c.jr.yaml +++ b/arch/inst/C/c.jr.yaml @@ -9,15 +9,15 @@ description: | C.JR expands to jalr x0, 0(rs1). definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1 encoding: match: 1000-----0000010 variables: - - name: rs1 - location: 11-7 - not: 0 + - name: rs1 + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.ld.yaml b/arch/inst/C/c.ld.yaml index f34a728b6..b9d05dea0 100644 --- a/arch/inst/C/c.ld.yaml +++ b/arch/inst/C/c.ld.yaml @@ -11,19 +11,19 @@ description: | It expands to `ld` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 011-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.ldsp.yaml b/arch/inst/C/c.ldsp.yaml index 3094c3624..50786f1d7 100644 --- a/arch/inst/C/c.ldsp.yaml +++ b/arch/inst/C/c.ldsp.yaml @@ -13,19 +13,19 @@ description: | C.LDSP is only valid when rd ≠ x0 the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm(sp) encoding: match: 011-----------10 variables: - - name: imm - location: 4-2|12|6-5 - left_shift: 3 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.li.yaml b/arch/inst/C/c.li.yaml index e162bc7fb..19f3fd4e7 100644 --- a/arch/inst/C/c.li.yaml +++ b/arch/inst/C/c.li.yaml @@ -10,17 +10,17 @@ description: | C.LI is only valid when rd ≠ x0; the code points with rd=x0 encode HINTs. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 010-----------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.lq.yaml b/arch/inst/C/c.lq.yaml index 12dfd8304..b6d532298 100644 --- a/arch/inst/C/c.lq.yaml +++ b/arch/inst/C/c.lq.yaml @@ -11,19 +11,19 @@ description: | It expands to `lq` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 001-----------00 variables: - - name: imm - location: 12-11|6-5|10 - left_shift: 4 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 12-11|6-5|10 + left_shift: 4 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.lqsp.yaml b/arch/inst/C/c.lqsp.yaml index 937857306..adce78227 100644 --- a/arch/inst/C/c.lqsp.yaml +++ b/arch/inst/C/c.lqsp.yaml @@ -12,19 +12,19 @@ description: | C.LQSP is only valid when rd ≠ x0 the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm(sp) encoding: match: 001-----------10 variables: - - name: imm - location: 5-2|12|6 - left_shift: 4 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 5-2|12|6 + left_shift: 4 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.lui.yaml b/arch/inst/C/c.lui.yaml index 85c946574..bf2cca884 100644 --- a/arch/inst/C/c.lui.yaml +++ b/arch/inst/C/c.lui.yaml @@ -11,18 +11,18 @@ description: | The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 011-----------01 variables: - - name: imm - location: 12|6-2 - left_shift: 12 - - name: rd - location: 11-7 - not: [0, 2] + - name: imm + location: 12|6-2 + left_shift: 12 + - name: rd + location: 11-7 + not: [0, 2] access: s: always u: always diff --git a/arch/inst/C/c.lw.yaml b/arch/inst/C/c.lw.yaml index 91c2d3a60..da6019aa9 100644 --- a/arch/inst/C/c.lw.yaml +++ b/arch/inst/C/c.lw.yaml @@ -11,19 +11,19 @@ description: | It expands to `lw` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 010-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.lwsp.yaml b/arch/inst/C/c.lwsp.yaml index 93e03f9b1..3c4e82051 100644 --- a/arch/inst/C/c.lwsp.yaml +++ b/arch/inst/C/c.lwsp.yaml @@ -12,18 +12,18 @@ description: | C.LWSP is only valid when rd ≠ x0. The code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(sp) encoding: match: 010-----------10 variables: - - name: imm - location: 3-2|12|6-4 - left_shift: 2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.mv.yaml b/arch/inst/C/c.mv.yaml index 0bd2a872b..36e97e4d1 100644 --- a/arch/inst/C/c.mv.yaml +++ b/arch/inst/C/c.mv.yaml @@ -9,18 +9,18 @@ description: | C.MV expands to addi rd, x0, rs2. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, xs2 encoding: match: 1000----------10 variables: - - name: rd - location: 11-7 - not: 0 - - name: rs2 - location: 6-2 - not: 0 + - name: rd + location: 11-7 + not: 0 + - name: rs2 + location: 6-2 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.nop.yaml b/arch/inst/C/c.nop.yaml index 804e23ed0..60bdb525b 100644 --- a/arch/inst/C/c.nop.yaml +++ b/arch/inst/C/c.nop.yaml @@ -8,15 +8,15 @@ description: | C.NOP expands into `addi x0, x0, imm`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 000-00000-----01 variables: - - name: imm - location: 12|6-2 - not: 0 + - name: imm + location: 12|6-2 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.or.yaml b/arch/inst/C/c.or.yaml index 29c2e379a..b14f348c1 100644 --- a/arch/inst/C/c.or.yaml +++ b/arch/inst/C/c.or.yaml @@ -10,16 +10,16 @@ description: | C.OR expands into `or rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---10---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sd.yaml b/arch/inst/C/c.sd.yaml index ccb9b2d84..b44bd2745 100644 --- a/arch/inst/C/c.sd.yaml +++ b/arch/inst/C/c.sd.yaml @@ -11,19 +11,19 @@ description: | It expands to `sd` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 111-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sdsp.yaml b/arch/inst/C/c.sdsp.yaml index 9c1f3a4cc..d5d0d1c46 100644 --- a/arch/inst/C/c.sdsp.yaml +++ b/arch/inst/C/c.sdsp.yaml @@ -11,18 +11,18 @@ description: | It expands to `sd` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xs2, imm(sp) encoding: match: 111-----------10 variables: - - name: imm - location: 9-7|12-10 - left_shift: 3 - - name: rs2 - location: 6-2 + - name: imm + location: 9-7|12-10 + left_shift: 3 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.slli.yaml b/arch/inst/C/c.slli.yaml index 34457091f..f678469d8 100644 --- a/arch/inst/C/c.slli.yaml +++ b/arch/inst/C/c.slli.yaml @@ -9,17 +9,17 @@ description: | C.SLLI expands into `slli rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 000-----------10 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: shamt + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.sq.yaml b/arch/inst/C/c.sq.yaml index 7fa512768..24fb6f1fd 100644 --- a/arch/inst/C/c.sq.yaml +++ b/arch/inst/C/c.sq.yaml @@ -11,19 +11,19 @@ description: | It expands to `sq` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 101-----------00 variables: - - name: imm - location: 12-11|6-5|10 - left_shift: 4 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 12-11|6-5|10 + left_shift: 4 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sqsp.yaml b/arch/inst/C/c.sqsp.yaml index f2f0e486f..107e1981d 100644 --- a/arch/inst/C/c.sqsp.yaml +++ b/arch/inst/C/c.sqsp.yaml @@ -11,18 +11,18 @@ description: | It expands to `sq` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xs2, imm(sp) encoding: match: 101-----------10 variables: - - name: imm - location: 10-7|12-11 - left_shift: 4 - - name: rs2 - location: 6-2 + - name: imm + location: 10-7|12-11 + left_shift: 4 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.srai.yaml b/arch/inst/C/c.srai.yaml index 1f3a70b16..eb49c07cf 100644 --- a/arch/inst/C/c.srai.yaml +++ b/arch/inst/C/c.srai.yaml @@ -10,16 +10,16 @@ description: | C.SRAI expands into `srai rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 100-01--------01 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 9-7 + - name: shamt + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.srli.yaml b/arch/inst/C/c.srli.yaml index 51b246f48..cb18fa23c 100644 --- a/arch/inst/C/c.srli.yaml +++ b/arch/inst/C/c.srli.yaml @@ -10,16 +10,16 @@ description: | C.SRLI expands into `srli rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 100-00--------01 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 9-7 + - name: shamt + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sub.yaml b/arch/inst/C/c.sub.yaml index 60af66e88..32757173a 100644 --- a/arch/inst/C/c.sub.yaml +++ b/arch/inst/C/c.sub.yaml @@ -10,16 +10,16 @@ description: | C.SUB expands into `sub rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---00---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.subw.yaml b/arch/inst/C/c.subw.yaml index 2e45ead86..36ecadfe5 100644 --- a/arch/inst/C/c.subw.yaml +++ b/arch/inst/C/c.subw.yaml @@ -10,17 +10,17 @@ description: | C.SUBW expands into `subw rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, rs2 encoding: match: 100111---00---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sw.yaml b/arch/inst/C/c.sw.yaml index 2717ce020..f2ac18a3d 100644 --- a/arch/inst/C/c.sw.yaml +++ b/arch/inst/C/c.sw.yaml @@ -11,19 +11,19 @@ description: | It expands to `sw` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 110-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.swsp.yaml b/arch/inst/C/c.swsp.yaml index 1327b350f..dedf9e04c 100644 --- a/arch/inst/C/c.swsp.yaml +++ b/arch/inst/C/c.swsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `sw` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(sp) encoding: match: 110-----------10 variables: - - name: imm - location: 8-7|12-9 - left_shift: 2 - - name: rs2 - location: 6-2 + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.xor.yaml b/arch/inst/C/c.xor.yaml index ca04d2a18..5700c7b63 100644 --- a/arch/inst/C/c.xor.yaml +++ b/arch/inst/C/c.xor.yaml @@ -10,16 +10,16 @@ description: | C.XOR expands into `xor rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---01---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/D/fadd.d.yaml b/arch/inst/D/fadd.d.yaml index 78b384072..2256219fe 100644 --- a/arch/inst/D/fadd.d.yaml +++ b/arch/inst/D/fadd.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0000001------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fclass.d.yaml b/arch/inst/D/fclass.d.yaml index 06bd14a88..81874ef66 100644 --- a/arch/inst/D/fclass.d.yaml +++ b/arch/inst/D/fclass.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111000100000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.l.yaml b/arch/inst/D/fcvt.d.l.yaml index 1754fe9c3..e44cff7f8 100644 --- a/arch/inst/D/fcvt.d.l.yaml +++ b/arch/inst/D/fcvt.d.l.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.lu.yaml b/arch/inst/D/fcvt.d.lu.yaml index 71cc3e6ec..d1187f980 100644 --- a/arch/inst/D/fcvt.d.lu.yaml +++ b/arch/inst/D/fcvt.d.lu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.s.yaml b/arch/inst/D/fcvt.d.s.yaml index 19fd2e7d7..933be04fb 100644 --- a/arch/inst/D/fcvt.d.s.yaml +++ b/arch/inst/D/fcvt.d.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010000100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.w.yaml b/arch/inst/D/fcvt.d.w.yaml index cefecd930..202fa1370 100644 --- a/arch/inst/D/fcvt.d.w.yaml +++ b/arch/inst/D/fcvt.d.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.wu.yaml b/arch/inst/D/fcvt.d.wu.yaml index 9a05ce038..54eed68ce 100644 --- a/arch/inst/D/fcvt.d.wu.yaml +++ b/arch/inst/D/fcvt.d.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.l.d.yaml b/arch/inst/D/fcvt.l.d.yaml index 20352af5d..4460b3ddd 100644 --- a/arch/inst/D/fcvt.l.d.yaml +++ b/arch/inst/D/fcvt.l.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.l.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.lu.d.yaml b/arch/inst/D/fcvt.lu.d.yaml index f2e1f103e..dd7a24e59 100644 --- a/arch/inst/D/fcvt.lu.d.yaml +++ b/arch/inst/D/fcvt.lu.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.lu.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.s.d.yaml b/arch/inst/D/fcvt.s.d.yaml index 6f69d7638..f76d003e2 100644 --- a/arch/inst/D/fcvt.s.d.yaml +++ b/arch/inst/D/fcvt.s.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010000000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.w.d.yaml b/arch/inst/D/fcvt.w.d.yaml index 243fc5694..076e8900c 100644 --- a/arch/inst/D/fcvt.w.d.yaml +++ b/arch/inst/D/fcvt.w.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.wu.d.yaml b/arch/inst/D/fcvt.wu.d.yaml index abd390d4d..2653f58af 100644 --- a/arch/inst/D/fcvt.wu.d.yaml +++ b/arch/inst/D/fcvt.wu.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvtmod.w.d.yaml b/arch/inst/D/fcvtmod.w.d.yaml index d890f78fa..efd9414d1 100644 --- a/arch/inst/D/fcvtmod.w.d.yaml +++ b/arch/inst/D/fcvtmod.w.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fcvtmod.w.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 110000101000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fdiv.d.yaml b/arch/inst/D/fdiv.d.yaml index a3c17b19a..05c6cbd8e 100644 --- a/arch/inst/D/fdiv.d.yaml +++ b/arch/inst/D/fdiv.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0001101------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/feq.d.yaml b/arch/inst/D/feq.d.yaml index e3249eca6..1b008186d 100644 --- a/arch/inst/D/feq.d.yaml +++ b/arch/inst/D/feq.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fld.yaml b/arch/inst/D/fld.yaml index cc6a60256..7623d079d 100644 --- a/arch/inst/D/fld.yaml +++ b/arch/inst/D/fld.yaml @@ -5,18 +5,18 @@ kind: instruction name: fld long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, imm encoding: match: -----------------011-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fle.d.yaml b/arch/inst/D/fle.d.yaml index 149a7ee35..d5cb10f86 100644 --- a/arch/inst/D/fle.d.yaml +++ b/arch/inst/D/fle.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fleq.d.yaml b/arch/inst/D/fleq.d.yaml index 2046c32a7..f83760edd 100644 --- a/arch/inst/D/fleq.d.yaml +++ b/arch/inst/D/fleq.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1010001----------100-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fli.d.yaml b/arch/inst/D/fli.d.yaml index 113895fc0..9e226b79d 100644 --- a/arch/inst/D/fli.d.yaml +++ b/arch/inst/D/fli.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 111100100001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/flt.d.yaml b/arch/inst/D/flt.d.yaml index 8ab8d1996..5b37dcb96 100644 --- a/arch/inst/D/flt.d.yaml +++ b/arch/inst/D/flt.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fltq.d.yaml b/arch/inst/D/fltq.d.yaml index 63b1e93ed..2e662b260 100644 --- a/arch/inst/D/fltq.d.yaml +++ b/arch/inst/D/fltq.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1010001----------101-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmadd.d.yaml b/arch/inst/D/fmadd.d.yaml index c269141a7..3a04f8abf 100644 --- a/arch/inst/D/fmadd.d.yaml +++ b/arch/inst/D/fmadd.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1000011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmax.d.yaml b/arch/inst/D/fmax.d.yaml index 4e35cc44c..33ab9e2a8 100644 --- a/arch/inst/D/fmax.d.yaml +++ b/arch/inst/D/fmax.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010101----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmaxm.d.yaml b/arch/inst/D/fmaxm.d.yaml index 37765a2a5..0cce65dfa 100644 --- a/arch/inst/D/fmaxm.d.yaml +++ b/arch/inst/D/fmaxm.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 0010101----------011-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmin.d.yaml b/arch/inst/D/fmin.d.yaml index b91899406..56ab0470c 100644 --- a/arch/inst/D/fmin.d.yaml +++ b/arch/inst/D/fmin.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010101----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fminm.d.yaml b/arch/inst/D/fminm.d.yaml index 06ef3eae8..7dc713939 100644 --- a/arch/inst/D/fminm.d.yaml +++ b/arch/inst/D/fminm.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 0010101----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmsub.d.yaml b/arch/inst/D/fmsub.d.yaml index 3d582fdf9..025ebd63a 100644 --- a/arch/inst/D/fmsub.d.yaml +++ b/arch/inst/D/fmsub.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1000111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmul.d.yaml b/arch/inst/D/fmul.d.yaml index 5a7d07db6..9d632cb38 100644 --- a/arch/inst/D/fmul.d.yaml +++ b/arch/inst/D/fmul.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0001001------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmv.d.x.yaml b/arch/inst/D/fmv.d.x.yaml index 62007aaf2..a94132798 100644 --- a/arch/inst/D/fmv.d.x.yaml +++ b/arch/inst/D/fmv.d.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: fmv.d.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111100100000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmv.x.d.yaml b/arch/inst/D/fmv.x.d.yaml index 729fe7dc9..e6880c94a 100644 --- a/arch/inst/D/fmv.x.d.yaml +++ b/arch/inst/D/fmv.x.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: fmv.x.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111000100000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmvh.x.d.yaml b/arch/inst/D/fmvh.x.d.yaml index 86f7d4976..20ec6fa41 100644 --- a/arch/inst/D/fmvh.x.d.yaml +++ b/arch/inst/D/fmvh.x.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fmvh.x.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 111000100001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmvp.d.x.yaml b/arch/inst/D/fmvp.d.x.yaml index c44068bb4..6755e561c 100644 --- a/arch/inst/D/fmvp.d.x.yaml +++ b/arch/inst/D/fmvp.d.x.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmvp.d.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1011001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fnmadd.d.yaml b/arch/inst/D/fnmadd.d.yaml index 6e73fcf6f..876bf51c5 100644 --- a/arch/inst/D/fnmadd.d.yaml +++ b/arch/inst/D/fnmadd.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1001111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fnmsub.d.yaml b/arch/inst/D/fnmsub.d.yaml index f9f49cee5..d19d53ad4 100644 --- a/arch/inst/D/fnmsub.d.yaml +++ b/arch/inst/D/fnmsub.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1001011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fround.d.yaml b/arch/inst/D/fround.d.yaml index b67de8da0..c9cc9d890 100644 --- a/arch/inst/D/fround.d.yaml +++ b/arch/inst/D/fround.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, rm encoding: match: 010000100100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/froundnx.d.yaml b/arch/inst/D/froundnx.d.yaml index 411f4c8a6..e20c585e8 100644 --- a/arch/inst/D/froundnx.d.yaml +++ b/arch/inst/D/froundnx.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, rm encoding: match: 010000100101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsd.yaml b/arch/inst/D/fsd.yaml index 989b89200..f5f188def 100644 --- a/arch/inst/D/fsd.yaml +++ b/arch/inst/D/fsd.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsd long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xs1, xs2, imm encoding: match: -----------------011-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/D/fsgnj.d.yaml b/arch/inst/D/fsgnj.d.yaml index fdab3944f..6011bc7d8 100644 --- a/arch/inst/D/fsgnj.d.yaml +++ b/arch/inst/D/fsgnj.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsgnjn.d.yaml b/arch/inst/D/fsgnjn.d.yaml index 6e7a206f8..a26814ac5 100644 --- a/arch/inst/D/fsgnjn.d.yaml +++ b/arch/inst/D/fsgnjn.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsgnjx.d.yaml b/arch/inst/D/fsgnjx.d.yaml index b4e55c47c..b2ffc3162 100644 --- a/arch/inst/D/fsgnjx.d.yaml +++ b/arch/inst/D/fsgnjx.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsqrt.d.yaml b/arch/inst/D/fsqrt.d.yaml index 657abdfa7..05afdf583 100644 --- a/arch/inst/D/fsqrt.d.yaml +++ b/arch/inst/D/fsqrt.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010110100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsub.d.yaml b/arch/inst/D/fsub.d.yaml index 1bddc6665..5675815fe 100644 --- a/arch/inst/D/fsub.d.yaml +++ b/arch/inst/D/fsub.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0000101------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/F/fadd.s.yaml b/arch/inst/F/fadd.s.yaml index fdefa3a07..f82a7e2de 100644 --- a/arch/inst/F/fadd.s.yaml +++ b/arch/inst/F/fadd.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0000000------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fclass.s.yaml b/arch/inst/F/fclass.s.yaml index 29f391926..4e559a1d1 100644 --- a/arch/inst/F/fclass.s.yaml +++ b/arch/inst/F/fclass.s.yaml @@ -5,41 +5,41 @@ kind: instruction name: fclass.s long_name: Single-precision floating-point classify. description: | - The `fclass.s` instruction examines the value in floating-point register - _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates - the class of the floating-point number. - The format of the mask is described in the table below. - The corresponding bit in _rd_ will be set if the property is true and - clear otherwise. - All other bits in _rd_ are cleared. - Note that exactly one bit in rd will be set. - `fclass.s` does not set the floating-point exception flags. + The `fclass.s` instruction examines the value in floating-point register + _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates + the class of the floating-point number. + The format of the mask is described in the table below. + The corresponding bit in _rd_ will be set if the property is true and + clear otherwise. + All other bits in _rd_ are cleared. + Note that exactly one bit in rd will be set. + `fclass.s` does not set the floating-point exception flags. - .Format of result of `fclass` instruction. - [%autowidth,float="center",align="center",cols="^,<",options="header",] - |=== - |_rd_ bit |Meaning - |0 |_rs1_ is latexmath:[$-\infty$]. - |1 |_rs1_ is a negative normal number. - |2 |_rs1_ is a negative subnormal number. - |3 |_rs1_ is latexmath:[$-0$]. - |4 |_rs1_ is latexmath:[$+0$]. - |5 |_rs1_ is a positive subnormal number. - |6 |_rs1_ is a positive normal number. - |7 |_rs1_ is latexmath:[$+\infty$]. - |8 |_rs1_ is a signaling NaN. - |9 |_rs1_ is a quiet NaN. - |=== + .Format of result of `fclass` instruction. + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |_rd_ bit |Meaning + |0 |_rs1_ is latexmath:[$-\infty$]. + |1 |_rs1_ is a negative normal number. + |2 |_rs1_ is a negative subnormal number. + |3 |_rs1_ is latexmath:[$-0$]. + |4 |_rs1_ is latexmath:[$+0$]. + |5 |_rs1_ is a positive subnormal number. + |6 |_rs1_ is a positive normal number. + |7 |_rs1_ is latexmath:[$+\infty$]. + |8 |_rs1_ is a signaling NaN. + |9 |_rs1_ is a quiet NaN. + |=== definedBy: F assembly: xd, fs1 encoding: match: 111000000000-----001-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -74,8 +74,6 @@ operation(): | X[rd] = 1 << 9; } - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/F/fcvt.l.s.yaml b/arch/inst/F/fcvt.l.s.yaml index c5d156aa4..85e56d0de 100644 --- a/arch/inst/F/fcvt.l.s.yaml +++ b/arch/inst/F/fcvt.l.s.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.l.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: xd, fs1, rm encoding: match: 110000000010-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.lu.s.yaml b/arch/inst/F/fcvt.lu.s.yaml index a77ccfe53..f80fe600a 100644 --- a/arch/inst/F/fcvt.lu.s.yaml +++ b/arch/inst/F/fcvt.lu.s.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.lu.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: xd, fs1, rm encoding: match: 110000000011-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.l.yaml b/arch/inst/F/fcvt.s.l.yaml index 436bf1906..2893034c6 100644 --- a/arch/inst/F/fcvt.s.l.yaml +++ b/arch/inst/F/fcvt.s.l.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.s.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: fd, xs1, rm encoding: match: 110100000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.lu.yaml b/arch/inst/F/fcvt.s.lu.yaml index b999a2296..31dbe4871 100644 --- a/arch/inst/F/fcvt.s.lu.yaml +++ b/arch/inst/F/fcvt.s.lu.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.s.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: fd, xs1, rm encoding: match: 110100000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.w.yaml b/arch/inst/F/fcvt.s.w.yaml index 70074ff6d..9e0d646c0 100644 --- a/arch/inst/F/fcvt.s.w.yaml +++ b/arch/inst/F/fcvt.s.w.yaml @@ -20,12 +20,12 @@ assembly: fd, xs1 encoding: match: 110100000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -50,9 +50,6 @@ operation(): | mark_f_state_dirty(); - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.wu.yaml b/arch/inst/F/fcvt.s.wu.yaml index 783e1a461..57fab4e22 100644 --- a/arch/inst/F/fcvt.s.wu.yaml +++ b/arch/inst/F/fcvt.s.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, xs1, rm encoding: match: 110100000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.w.s.yaml b/arch/inst/F/fcvt.w.s.yaml index 5693a6046..9921dd935 100644 --- a/arch/inst/F/fcvt.w.s.yaml +++ b/arch/inst/F/fcvt.w.s.yaml @@ -5,47 +5,47 @@ kind: instruction name: fcvt.w.s long_name: Convert single-precision float to integer word to signed 32-bit integer. description: | - Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates - integer register _rd_. + Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates + integer register _rd_. - For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width. + For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width. - If the rounded result is not representable as a 32-bit signed integer, it is clipped to the - nearest value and the invalid flag is set. + If the rounded result is not representable as a 32-bit signed integer, it is clipped to the + nearest value and the invalid flag is set. - The range of valid inputs and behavior for invalid inputs are: + The range of valid inputs and behavior for invalid inputs are: - [separator="!"] - !=== - ! ! Value + [separator="!"] + !=== + ! ! Value - h! Minimum valid input (after rounding) ! `-2^31` - h! Maximum valid input (after rounding) ! `2^31 - 1` - h! Output for out-of-range negative input ! `-2^31` - h! Output for `-∞` ! `-2^31` - h! Output for out-of-range positive input ! `2^31 - 1` - h! Output for `+∞` for `NaN` ! `2^31 - 1` - !=== + h! Minimum valid input (after rounding) ! `-2^31` + h! Maximum valid input (after rounding) ! `2^31 - 1` + h! Output for out-of-range negative input ! `-2^31` + h! Output for `-∞` ! `-2^31` + h! Output for out-of-range positive input ! `2^31 - 1` + h! Output for `+∞` for `NaN` ! `2^31 - 1` + !=== - All floating-point to integer and integer to floating-point conversion instructions round - according to the _rm_ field. - A floating-point register can be initialized to floating-point positive zero using - `fcvt.s.w rd, x0`, which will never set any exception flags. + All floating-point to integer and integer to floating-point conversion instructions round + according to the _rm_ field. + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w rd, x0`, which will never set any exception flags. - All floating-point conversion instructions set the Inexact exception flag if the rounded - result differs from the operand value and the Invalid exception flag is not set. + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. definedBy: F assembly: xd, fs1 encoding: match: 110000000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -53,35 +53,31 @@ access: vu: always data_independent_timing: true operation(): | - check_f_ok($encoding); + check_f_ok($encoding); - Bits<32> sp_value = f[fs1][31:0]; + Bits<32> sp_value = f[fs1][31:0]; - Bits<1> sign = sp_value[31]; - Bits<8> exp = sp_value[30:23]; - Bits<23> sig = sp_value[22:0]; + Bits<1> sign = sp_value[31]; + Bits<8> exp = sp_value[30:23]; + Bits<23> sig = sp_value[22:0]; - RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); - if ( (exp == 0xff) && (sig != 0)) { - sign = 0; - set_fp_flag(FpFlag::NV); - X[rd] = SP_CANONICAL_NAN; - } else { - if (exp != 0) { - sig = sig | 0x00800000; - } - Bits<64> sig64 = sig << 32; - Bits<16> shift_dist = 0xAA - exp; - if (0 < shift_dist) { - sig64 = softfloat_shiftRightJam64(sig64, shift_dist ); - } - X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode ); + if ( (exp == 0xff) && (sig != 0)) { + sign = 0; + set_fp_flag(FpFlag::NV); + X[rd] = SP_CANONICAL_NAN; + } else { + if (exp != 0) { + sig = sig | 0x00800000; } - - - - + Bits<64> sig64 = sig << 32; + Bits<16> shift_dist = 0xAA - exp; + if (0 < shift_dist) { + sig64 = softfloat_shiftRightJam64(sig64, shift_dist ); + } + X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode ); + } sail(): | { diff --git a/arch/inst/F/fcvt.wu.s.yaml b/arch/inst/F/fcvt.wu.s.yaml index 62468f564..6dc4667bc 100644 --- a/arch/inst/F/fcvt.wu.s.yaml +++ b/arch/inst/F/fcvt.wu.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, fs1, rm encoding: match: 110000000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fdiv.s.yaml b/arch/inst/F/fdiv.s.yaml index a022a8965..297533cb9 100644 --- a/arch/inst/F/fdiv.s.yaml +++ b/arch/inst/F/fdiv.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0001100------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/feq.s.yaml b/arch/inst/F/feq.s.yaml index 5cb61a47b..c278a7918 100644 --- a/arch/inst/F/feq.s.yaml +++ b/arch/inst/F/feq.s.yaml @@ -5,23 +5,23 @@ kind: instruction name: feq.s long_name: Single-precision floating-point equal description: | - Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set. - Positive zero is considered equal to negative zero. + Positive zero is considered equal to negative zero. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -46,8 +46,6 @@ operation(): | ) ? 1 : 0; } - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fle.s.yaml b/arch/inst/F/fle.s.yaml index 23cee21f4..12043cddb 100644 --- a/arch/inst/F/fle.s.yaml +++ b/arch/inst/F/fle.s.yaml @@ -5,24 +5,24 @@ kind: instruction name: fle.s long_name: Single-precision floating-point less than or equal description: | - Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). - If either operand is a NaN (signaling or quiet), the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). + If either operand is a NaN (signaling or quiet), the invalid flag is set. - Positive zero and negative zero are considered equal. + Positive zero and negative zero are considered equal. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | ) ? 1 : 0; } - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fleq.s.yaml b/arch/inst/F/fleq.s.yaml index b2645b9d8..2d40e3d28 100644 --- a/arch/inst/F/fleq.s.yaml +++ b/arch/inst/F/fleq.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fleq.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, fs1, fs2 encoding: match: 1010000----------100-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fli.s.yaml b/arch/inst/F/fli.s.yaml index 293103c89..4ddd2390e 100644 --- a/arch/inst/F/fli.s.yaml +++ b/arch/inst/F/fli.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: fli.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, fs1 encoding: match: 111100000001-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let bits : bits(32) = match constantidx { diff --git a/arch/inst/F/flt.s.yaml b/arch/inst/F/flt.s.yaml index e6d63d55b..468aa9d4f 100644 --- a/arch/inst/F/flt.s.yaml +++ b/arch/inst/F/flt.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: flt.s long_name: Single-precision floating-point less than description: | - Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). - If either operand is a NaN (signaling or quiet), the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). + If either operand is a NaN (signaling or quiet), the invalid flag is set. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,10 +47,6 @@ operation(): | X[rd] = a_lt_b ? 1 : 0; } - - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fltq.s.yaml b/arch/inst/F/fltq.s.yaml index 219da4452..a06e604e7 100644 --- a/arch/inst/F/fltq.s.yaml +++ b/arch/inst/F/fltq.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fltq.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, fs1, fs2 encoding: match: 1010000----------101-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/flw.yaml b/arch/inst/F/flw.yaml index 1ca5c6928..948394d82 100644 --- a/arch/inst/F/flw.yaml +++ b/arch/inst/F/flw.yaml @@ -14,12 +14,12 @@ assembly: fd, xs1, imm encoding: match: -----------------010-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -41,7 +41,6 @@ operation(): | mark_f_state_dirty(); - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/F/fmadd.s.yaml b/arch/inst/F/fmadd.s.yaml index 353d68e44..84b813800 100644 --- a/arch/inst/F/fmadd.s.yaml +++ b/arch/inst/F/fmadd.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1000011 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmax.s.yaml b/arch/inst/F/fmax.s.yaml index c617d7543..4836edacb 100644 --- a/arch/inst/F/fmax.s.yaml +++ b/arch/inst/F/fmax.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010100----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fmaxm.s.yaml b/arch/inst/F/fmaxm.s.yaml index 39d20ca1e..db023f712 100644 --- a/arch/inst/F/fmaxm.s.yaml +++ b/arch/inst/F/fmaxm.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmaxm.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, xs1, xs2 encoding: match: 0010100----------011-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fmin.s.yaml b/arch/inst/F/fmin.s.yaml index 06dd4c629..fa278a102 100644 --- a/arch/inst/F/fmin.s.yaml +++ b/arch/inst/F/fmin.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, xs1, xs2 encoding: match: 0010100----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fminm.s.yaml b/arch/inst/F/fminm.s.yaml index da71a465c..aa8d00371 100644 --- a/arch/inst/F/fminm.s.yaml +++ b/arch/inst/F/fminm.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fminm.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, fs1, fs2 encoding: match: 0010100----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fmsub.s.yaml b/arch/inst/F/fmsub.s.yaml index 13d2a7f52..a36336190 100644 --- a/arch/inst/F/fmsub.s.yaml +++ b/arch/inst/F/fmsub.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1000111 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmul.s.yaml b/arch/inst/F/fmul.s.yaml index 66d5392b7..d64c434d7 100644 --- a/arch/inst/F/fmul.s.yaml +++ b/arch/inst/F/fmul.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0001000------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmv.w.x.yaml b/arch/inst/F/fmv.w.x.yaml index 4b593de63..a3cbe3a5c 100644 --- a/arch/inst/F/fmv.w.x.yaml +++ b/arch/inst/F/fmv.w.x.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmv.w.x long_name: Single-precision floating-point move from integer description: | - Moves the single-precision value encoded in IEEE 754-2008 standard encoding - from the lower 32 bits of integer register `rs1` to the floating-point - register `fd`. The bits are not modified in the transfer, and in particular, - the payloads of non-canonical NaNs are preserved. + Moves the single-precision value encoded in IEEE 754-2008 standard encoding + from the lower 32 bits of integer register `rs1` to the floating-point + register `fd`. The bits are not modified in the transfer, and in particular, + the payloads of non-canonical NaNs are preserved. definedBy: F assembly: fd, xs1 encoding: match: 111100000000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/F/fmv.x.w.yaml b/arch/inst/F/fmv.x.w.yaml index f8887234c..353ac0f9d 100644 --- a/arch/inst/F/fmv.x.w.yaml +++ b/arch/inst/F/fmv.x.w.yaml @@ -5,21 +5,21 @@ kind: instruction name: fmv.x.w long_name: Move single-precision value from floating-point to integer register description: | - Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 - encoding to the lower 32 bits of integer register rd. - The bits are not modified in the transfer, and in particular, the payloads of non-canonical - NaNs are preserved. - For RV64, the higher 32 bits of the destination register are filled with copies of the - floating-point number's sign bit. + Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 + encoding to the lower 32 bits of integer register rd. + The bits are not modified in the transfer, and in particular, the payloads of non-canonical + NaNs are preserved. + For RV64, the higher 32 bits of the destination register are filled with copies of the + floating-point number's sign bit. definedBy: F assembly: xd, fs1 encoding: match: 111000000000-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,11 +27,9 @@ access: vu: always data_independent_timing: true operation(): | - check_f_ok($encoding); - - X[rd] = sext(f[fs1][31:0], 32); - + check_f_ok($encoding); + X[rd] = sext(f[fs1][31:0], 32); sail(): | { diff --git a/arch/inst/F/fnmadd.s.yaml b/arch/inst/F/fnmadd.s.yaml index 1b0eaecf5..b18f8c6fb 100644 --- a/arch/inst/F/fnmadd.s.yaml +++ b/arch/inst/F/fnmadd.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1001111 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fnmsub.s.yaml b/arch/inst/F/fnmsub.s.yaml index c1a1997b8..ee988c456 100644 --- a/arch/inst/F/fnmsub.s.yaml +++ b/arch/inst/F/fnmsub.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, xs1, xs2, xs3, rm encoding: match: -----00------------------1001011 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fround.s.yaml b/arch/inst/F/fround.s.yaml index 83753b0a8..34db217b9 100644 --- a/arch/inst/F/fround.s.yaml +++ b/arch/inst/F/fround.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fround.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, xs1, rm encoding: match: 010000000100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/froundnx.s.yaml b/arch/inst/F/froundnx.s.yaml index b3d8927e0..8ff644feb 100644 --- a/arch/inst/F/froundnx.s.yaml +++ b/arch/inst/F/froundnx.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: froundnx.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, rs1, rm encoding: match: 010000000101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fsgnj.s.yaml b/arch/inst/F/fsgnj.s.yaml index 544d564e1..65e132247 100644 --- a/arch/inst/F/fsgnj.s.yaml +++ b/arch/inst/F/fsgnj.s.yaml @@ -5,21 +5,21 @@ kind: instruction name: fsgnj.s long_name: Single-precision sign inject description: | - Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_. + Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -27,8 +27,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fmv.s + - when: (rs2 == rs1) + to: fmv.s operation(): | check_f_ok($encoding); @@ -43,8 +43,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsgnjn.s.yaml b/arch/inst/F/fsgnjn.s.yaml index 286f7bffd..d39200cd6 100644 --- a/arch/inst/F/fsgnjn.s.yaml +++ b/arch/inst/F/fsgnjn.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsgnjn.s long_name: Single-precision sign inject negate description: | - Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_. + Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -26,8 +26,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fneg.s + - when: (rs2 == rs1) + to: fneg.s operation(): | check_f_ok($encoding); @@ -42,8 +42,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsgnjx.s.yaml b/arch/inst/F/fsgnjx.s.yaml index e6fba2282..50d0f3ef2 100644 --- a/arch/inst/F/fsgnjx.s.yaml +++ b/arch/inst/F/fsgnjx.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsgnjx.s long_name: Single-precision sign inject exclusive or description: | - Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_. + Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -26,8 +26,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fabs.s + - when: (rs2 == rs1) + to: fabs.s operation(): | check_f_ok($encoding); @@ -41,8 +41,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsqrt.s.yaml b/arch/inst/F/fsqrt.s.yaml index a869687a2..939cdbac8 100644 --- a/arch/inst/F/fsqrt.s.yaml +++ b/arch/inst/F/fsqrt.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, rm encoding: match: 010110000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fsub.s.yaml b/arch/inst/F/fsub.s.yaml index ecce09860..e43070103 100644 --- a/arch/inst/F/fsub.s.yaml +++ b/arch/inst/F/fsub.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0000100------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fsw.yaml b/arch/inst/F/fsw.yaml index d2f23782a..47745eefb 100644 --- a/arch/inst/F/fsw.yaml +++ b/arch/inst/F/fsw.yaml @@ -14,12 +14,12 @@ assembly: fs2, xs1, imm encoding: match: -----------------010-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: fs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: fs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | write_memory<32>(virtual_address, f[fs2][31:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/H/hfence.gvma.yaml b/arch/inst/H/hfence.gvma.yaml index 4bffc4c60..a06d3c70e 100644 --- a/arch/inst/H/hfence.gvma.yaml +++ b/arch/inst/H/hfence.gvma.yaml @@ -5,16 +5,16 @@ kind: instruction name: hfence.gvma long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hfence.vvma.yaml b/arch/inst/H/hfence.vvma.yaml index dd015039f..08f1e10c2 100644 --- a/arch/inst/H/hfence.vvma.yaml +++ b/arch/inst/H/hfence.vvma.yaml @@ -5,16 +5,16 @@ kind: instruction name: hfence.vvma long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0010001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hlv.b.yaml b/arch/inst/H/hlv.b.yaml index c89ccd5c6..8704d0fe8 100644 --- a/arch/inst/H/hlv.b.yaml +++ b/arch/inst/H/hlv.b.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011000000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.bu.yaml b/arch/inst/H/hlv.bu.yaml index 5938d786a..44441cafa 100644 --- a/arch/inst/H/hlv.bu.yaml +++ b/arch/inst/H/hlv.bu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.bu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011000000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.d.yaml b/arch/inst/H/hlv.d.yaml index 98c27700b..96683b010 100644 --- a/arch/inst/H/hlv.d.yaml +++ b/arch/inst/H/hlv.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011011000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.h.yaml b/arch/inst/H/hlv.h.yaml index 6abbd7d9b..ca472fcb1 100644 --- a/arch/inst/H/hlv.h.yaml +++ b/arch/inst/H/hlv.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.hu.yaml b/arch/inst/H/hlv.hu.yaml index 99614784c..9935245a2 100644 --- a/arch/inst/H/hlv.hu.yaml +++ b/arch/inst/H/hlv.hu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.hu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.w.yaml b/arch/inst/H/hlv.w.yaml index 53d318cad..d1e9b8405 100644 --- a/arch/inst/H/hlv.w.yaml +++ b/arch/inst/H/hlv.w.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.wu.yaml b/arch/inst/H/hlv.wu.yaml index 2b8d652c9..5957f331d 100644 --- a/arch/inst/H/hlv.wu.yaml +++ b/arch/inst/H/hlv.wu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlvx.hu.yaml b/arch/inst/H/hlvx.hu.yaml index b527451cd..c9ebbca6d 100644 --- a/arch/inst/H/hlvx.hu.yaml +++ b/arch/inst/H/hlvx.hu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlvx.hu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000011-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlvx.wu.yaml b/arch/inst/H/hlvx.wu.yaml index d764afeb3..3f2c36976 100644 --- a/arch/inst/H/hlvx.wu.yaml +++ b/arch/inst/H/hlvx.wu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlvx.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000011-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hsv.b.yaml b/arch/inst/H/hsv.b.yaml index 03da5add6..0e8a8f68c 100644 --- a/arch/inst/H/hsv.b.yaml +++ b/arch/inst/H/hsv.b.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110001----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.d.yaml b/arch/inst/H/hsv.d.yaml index cda8a6b5b..9cf6e2daf 100644 --- a/arch/inst/H/hsv.d.yaml +++ b/arch/inst/H/hsv.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110111----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.h.yaml b/arch/inst/H/hsv.h.yaml index 2ceb5b6b7..51dd805a1 100644 --- a/arch/inst/H/hsv.h.yaml +++ b/arch/inst/H/hsv.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110011----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.w.yaml b/arch/inst/H/hsv.w.yaml index 2379bc83a..87ccaa132 100644 --- a/arch/inst/H/hsv.w.yaml +++ b/arch/inst/H/hsv.w.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110101----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/I/add.yaml b/arch/inst/I/add.yaml index e7038315a..6466549d4 100644 --- a/arch/inst/I/add.yaml +++ b/arch/inst/I/add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] + X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 74adf7a40..f7c6e5bce 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------000-----0010011 variables: - - name: imm - $inherits: common/inst_variable_types.yaml#/itype_imm - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + $inherits: common/inst_variable_types.yaml#/itype_imm + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] + imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index 9060c51ee..40a71c753 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, imm encoding: match: -----------------000-----0011011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | XReg operand = sext(X[rs1], 31); X[rd] = sext(operand + imm, 31); - - sail(): | { let result : xlenbits = sign_extend(imm) + X(rs1); diff --git a/arch/inst/I/addw.yaml b/arch/inst/I/addw.yaml index 2abb97ed7..4a87e73c9 100644 --- a/arch/inst/I/addw.yaml +++ b/arch/inst/I/addw.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | XReg operand2 = sext(X[rs2], 31); X[rd] = sext(operand1 + operand2, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/and.yaml b/arch/inst/I/and.yaml index 85a3a2022..7a1892779 100644 --- a/arch/inst/I/and.yaml +++ b/arch/inst/I/and.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] & X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 708d67edb..111918792 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------111-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] & imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/auipc.yaml b/arch/inst/I/auipc.yaml index 3aa89876e..df2cac9f3 100644 --- a/arch/inst/I/auipc.yaml +++ b/arch/inst/I/auipc.yaml @@ -10,11 +10,11 @@ assembly: xd, imm encoding: match: -------------------------0010111 variables: - - name: imm - location: 31-12 - left_shift: 12 - - name: rd - location: 11-7 + - name: imm + location: 31-12 + left_shift: 12 + - name: rd + location: 11-7 access: s: always u: always @@ -23,7 +23,6 @@ access: data_independent_timing: true operation(): X[rd] = $pc + imm; - sail(): | { let off : xlenbits = sign_extend(imm @ 0x000); diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index a58721bb6..de4b33736 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------000-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,7 +34,6 @@ operation(): | jump_halfword($pc + imm); } - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index 41369cb8e..d6ed0b270 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------101-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bgeu.yaml b/arch/inst/I/bgeu.yaml index daa2a490f..e2a2a4821 100644 --- a/arch/inst/I/bgeu.yaml +++ b/arch/inst/I/bgeu.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------111-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index beed9ad24..444d76114 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------100-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bltu.yaml b/arch/inst/I/bltu.yaml index bfc1ab77f..caedfe048 100644 --- a/arch/inst/I/bltu.yaml +++ b/arch/inst/I/bltu.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------110-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index 96c72a066..97f7ed018 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------001-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/ebreak.yaml b/arch/inst/I/ebreak.yaml index c13b7435f..918a6f392 100644 --- a/arch/inst/I/ebreak.yaml +++ b/arch/inst/I/ebreak.yaml @@ -18,9 +18,9 @@ description: | As EBREAK causes a synchronous exception, it is not considered to retire, and should not increment the `minstret` CSR. definedBy: I -assembly: '' +assembly: "" encoding: - match: '00000000000100000000000001110011' + match: "00000000000100000000000001110011" access: s: always u: always @@ -33,8 +33,6 @@ operation(): | eei_ebreak(); } - - sail(): | { handle_mem_exception(PC, E_Breakpoint()); diff --git a/arch/inst/I/ecall.yaml b/arch/inst/I/ecall.yaml index 205b43201..1c78c4967 100644 --- a/arch/inst/I/ecall.yaml +++ b/arch/inst/I/ecall.yaml @@ -21,9 +21,9 @@ description: | As ECALL causes a synchronous exception, it is not considered to retire, and should not increment the `minstret` CSR. definedBy: I -assembly: '' +assembly: "" encoding: - match: '00000000000000000000000001110011' + match: "00000000000000000000000001110011" access: s: always u: always @@ -56,8 +56,6 @@ operation(): | } } - - sail(): | { let t : sync_exception = diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index b5173ec68..430272017 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -125,16 +125,16 @@ assembly: "TODO" encoding: match: -----------------000-----0001111 variables: - - name: fm - location: 31-28 - - name: pred - location: 27-24 - - name: succ - location: 23-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fm + location: 31-28 + - name: pred + location: 27-24 + - name: succ + location: 23-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -203,12 +203,10 @@ operation(): | ); } pseudoinstructions: -- when: (pred == 0x3) && (succ == 0x3) && (fm == 1) - to: fence.tso -- when: (pred == 1) && (succ == 0) && (fm == 0) && (rd == 0) && (rs1 == 0) - to: pause - - + - when: (pred == 0x3) && (succ == 0x3) && (fm == 1) + to: fence.tso + - when: (pred == 1) && (succ == 0) && (fm == 0) && (rd == 0) && (rs1 == 0) + to: pause sail(): | { diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index 7c0b299d3..f0db80a91 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -12,12 +12,12 @@ assembly: xd, imm encoding: match: -------------------------1101111 variables: - - name: imm - location: 31|19-12|20|30-21 - left_shift: 1 - sign_extend: true - - name: rd - location: 11-7 + - name: imm + location: 31|19-12|20|30-21 + left_shift: 1 + sign_extend: true + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | jump_halfword($pc + imm); X[rd] = retrun_addr; - - sail(): | { let t : xlenbits = PC + sign_extend(imm); diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index d3591fd2f..5ef484c11 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -12,12 +12,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------000-----1100111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | jump(X[rs1] + imm); X[rd] = returnaddr; - - sail(): | { /* For the sequential model, the memory-model definition doesn't work directly diff --git a/arch/inst/I/lb.yaml b/arch/inst/I/lb.yaml index 96c27ead6..170707be9 100644 --- a/arch/inst/I/lb.yaml +++ b/arch/inst/I/lb.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------000-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lbu.yaml b/arch/inst/I/lbu.yaml index c04ff027f..efb7d9697 100644 --- a/arch/inst/I/lbu.yaml +++ b/arch/inst/I/lbu.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------100-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<8>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/ld.yaml b/arch/inst/I/ld.yaml index dc00e7d60..e4c39adc0 100644 --- a/arch/inst/I/ld.yaml +++ b/arch/inst/I/ld.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------011-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<64>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lh.yaml b/arch/inst/I/lh.yaml index 22cfcfc0e..86b5b95f0 100644 --- a/arch/inst/I/lh.yaml +++ b/arch/inst/I/lh.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------001-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lhu.yaml b/arch/inst/I/lhu.yaml index 7c5da3396..95e8a60ee 100644 --- a/arch/inst/I/lhu.yaml +++ b/arch/inst/I/lhu.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------101-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<16>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lui.yaml b/arch/inst/I/lui.yaml index 2401cf14a..be47ea173 100644 --- a/arch/inst/I/lui.yaml +++ b/arch/inst/I/lui.yaml @@ -10,11 +10,11 @@ assembly: xd, imm encoding: match: -------------------------0110111 variables: - - name: imm - location: 31-12 - left_shift: 12 - - name: rd - location: 11-7 + - name: imm + location: 31-12 + left_shift: 12 + - name: rd + location: 11-7 access: s: always u: always @@ -23,8 +23,6 @@ access: data_independent_timing: true operation(): X[rd] = imm; - - sail(): | { let off : xlenbits = sign_extend(imm @ 0x000); diff --git a/arch/inst/I/lw.yaml b/arch/inst/I/lw.yaml index db9e08794..c950ddbdf 100644 --- a/arch/inst/I/lw.yaml +++ b/arch/inst/I/lw.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------010-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<32>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lwu.yaml b/arch/inst/I/lwu.yaml index d20029bc5..0c35b3ad9 100644 --- a/arch/inst/I/lwu.yaml +++ b/arch/inst/I/lwu.yaml @@ -14,12 +14,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------110-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = read_memory<32>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/mret.yaml b/arch/inst/I/mret.yaml index 114f68c33..f22c58bb4 100644 --- a/arch/inst/I/mret.yaml +++ b/arch/inst/I/mret.yaml @@ -12,7 +12,7 @@ access: vs: never vu: never encoding: - match: '00110000001000000000000001110011' + match: "00110000001000000000000001110011" operation(): | if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) { CSR[mstatus].MPRV = 0; @@ -29,8 +29,6 @@ operation(): | CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; $pc = $bits(CSR[mepc]); - - sail(): | { if cur_privilege != Machine diff --git a/arch/inst/I/or.yaml b/arch/inst/I/or.yaml index 0297a0cce..0eeee6aec 100644 --- a/arch/inst/I/or.yaml +++ b/arch/inst/I/or.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] | X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/ori.yaml b/arch/inst/I/ori.yaml index 6785c87e3..d2cc79d29 100644 --- a/arch/inst/I/ori.yaml +++ b/arch/inst/I/ori.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------110-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ pseudoinstructions: - when: (rd == 0) && (imm[4:0] == 3) to: prefetch.w offset - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sb.yaml b/arch/inst/I/sb.yaml index f0382d77a..303c435c0 100644 --- a/arch/inst/I/sb.yaml +++ b/arch/inst/I/sb.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------000-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<8>(virtual_address, X[rs2][7:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sd.yaml b/arch/inst/I/sd.yaml index 0875a4966..8ac4ab4a4 100644 --- a/arch/inst/I/sd.yaml +++ b/arch/inst/I/sd.yaml @@ -13,13 +13,13 @@ assembly: xs2, imm(xs1) encoding: match: -----------------011-----0100011 variables: - - name: imm - location: 31-25|11-7 - sign_extend: true - - name: rs1 - location: 19-15 - - name: rs2 - location: 24-20 + - name: imm + location: 31-25|11-7 + sign_extend: true + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | write_memory<64>(virtual_address, X[rs2], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sh.yaml b/arch/inst/I/sh.yaml index 8cfee4641..f7fb2db7a 100644 --- a/arch/inst/I/sh.yaml +++ b/arch/inst/I/sh.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------001-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<16>(virtual_address, X[rs2][15:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sll.yaml b/arch/inst/I/sll.yaml index 5695aeaf1..53faae394 100644 --- a/arch/inst/I/sll.yaml +++ b/arch/inst/I/sll.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] << X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slli.yaml b/arch/inst/I/slli.yaml index 81a703f00..12c53e32d 100644 --- a/arch/inst/I/slli.yaml +++ b/arch/inst/I/slli.yaml @@ -11,21 +11,21 @@ encoding: RV32: match: 0000000----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000000-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -36,8 +36,6 @@ operation(): | # shamt is between 0-(XLEN-1) X[rd] = X[rs1] << shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slliw.yaml b/arch/inst/I/slliw.yaml index b8092139f..b952b97df 100644 --- a/arch/inst/I/slliw.yaml +++ b/arch/inst/I/slliw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, shamt encoding: match: 0000000----------001-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | # shamt is between 0-32 X[rd] = sext(X[rs1] << shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sllw.yaml b/arch/inst/I/sllw.yaml index f540ff056..1e354d13d 100644 --- a/arch/inst/I/sllw.yaml +++ b/arch/inst/I/sllw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------001-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = sext(X[rs1] << X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index 1d1db5f42..d24ce3e2d 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, rs2 encoding: match: 0000000----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = ($signed(src1) < $signed(src2)) ? '1 : '0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slti.yaml b/arch/inst/I/slti.yaml index 84fd55a48..9431cca6e 100644 --- a/arch/inst/I/slti.yaml +++ b/arch/inst/I/slti.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, imm encoding: match: -----------------010-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ data_independent_timing: true operation(): | X[rd] = ($signed(X[rs1]) < $signed(imm)) ? '1 : '0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index 14af783bb..33e3c0d88 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, imm encoding: match: -----------------011-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ data_independent_timing: true operation(): | X[rd] = (X[rs1] < imm) ? 1 : 0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index b7087619b..e07da0b3e 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ data_independent_timing: true operation(): | X[rd] = (X[rs1] < X[rs2]) ? 1 : 0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sra.yaml b/arch/inst/I/sra.yaml index 55ad5e33f..855bbc9f1 100644 --- a/arch/inst/I/sra.yaml +++ b/arch/inst/I/sra.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] >>> X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srai.yaml b/arch/inst/I/srai.yaml index 862372f2a..33ae74ee0 100644 --- a/arch/inst/I/srai.yaml +++ b/arch/inst/I/srai.yaml @@ -13,21 +13,21 @@ encoding: RV32: match: 0100000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | # shamt is between 0-63 X[rd] = X[rs1] >>> shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sraiw.yaml b/arch/inst/I/sraiw.yaml index 42fd48d10..89e413c3d 100644 --- a/arch/inst/I/sraiw.yaml +++ b/arch/inst/I/sraiw.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, shamt encoding: match: 0100000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | XReg operand = sext(X[rs1], 31); X[rd] = sext(operand >>> shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sraw.yaml b/arch/inst/I/sraw.yaml index 716fd413d..46ff0b5cd 100644 --- a/arch/inst/I/sraw.yaml +++ b/arch/inst/I/sraw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(operand1 >>> X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/srl.yaml b/arch/inst/I/srl.yaml index 3219a49ab..aac000855 100644 --- a/arch/inst/I/srl.yaml +++ b/arch/inst/I/srl.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] >> X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srli.yaml b/arch/inst/I/srli.yaml index 376ffc0cc..d0e525725 100644 --- a/arch/inst/I/srli.yaml +++ b/arch/inst/I/srli.yaml @@ -10,21 +10,21 @@ encoding: RV32: match: 0000000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -35,8 +35,6 @@ operation(): | # shamt is between 0-63 X[rd] = X[rs1] >> shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srliw.yaml b/arch/inst/I/srliw.yaml index db87361ea..b859e0fa4 100644 --- a/arch/inst/I/srliw.yaml +++ b/arch/inst/I/srliw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, shamt encoding: match: 0000000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(operand >> shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/srlw.yaml b/arch/inst/I/srlw.yaml index 7945a7285..5e24f68d8 100644 --- a/arch/inst/I/srlw.yaml +++ b/arch/inst/I/srlw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = sext(X[rs1][31:0] >> X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index 85c792159..a4bbb98a7 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | XReg t1 = X[rs2]; X[rd] = t0 - t1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 8bc7e276f..d39c1b7e5 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | Bits<32> t1 = X[rs2][31:0]; X[rd] = sext(t0 - t1, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sw.yaml b/arch/inst/I/sw.yaml index 0912e0448..a95dcf3f8 100644 --- a/arch/inst/I/sw.yaml +++ b/arch/inst/I/sw.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------010-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<32>(virtual_address, X[rs2][31:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/wfi.yaml b/arch/inst/I/wfi.yaml index ce574396e..4c05807ee 100644 --- a/arch/inst/I/wfi.yaml +++ b/arch/inst/I/wfi.yaml @@ -47,7 +47,7 @@ description: | definedBy: Sm assembly: "" encoding: - match: '00010000010100000000000001110011' + match: "00010000010100000000000001110011" access: s: sometimes u: sometimes @@ -111,8 +111,6 @@ operation(): | # passed, so now do the wait wfi(); - - sail(): | match cur_privilege { Machine => { platform_wfi(); RETIRE_SUCCESS }, diff --git a/arch/inst/I/xor.yaml b/arch/inst/I/xor.yaml index e3438951d..ba2efc726 100644 --- a/arch/inst/I/xor.yaml +++ b/arch/inst/I/xor.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] ^ X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index d92c30742..2a588aa50 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------100-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] ^ imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/M/div.yaml b/arch/inst/M/div.yaml index 32b003a2d..652784552 100644 --- a/arch/inst/M/div.yaml +++ b/arch/inst/M/div.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -50,7 +50,6 @@ operation(): | X[rd] = $signed(src1) / $signed(src2); } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divu.yaml b/arch/inst/M/divu.yaml index 75c43ff8d..71ce0a624 100644 --- a/arch/inst/M/divu.yaml +++ b/arch/inst/M/divu.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -42,7 +42,6 @@ operation(): | X[rd] = src1 / src2; } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index 09e928a5b..d5e22cd25 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 4a1674859..13031feb0 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -19,12 +19,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -56,8 +56,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/mul.yaml b/arch/inst/M/mul.yaml index 26c440799..b4187b368 100644 --- a/arch/inst/M/mul.yaml +++ b/arch/inst/M/mul.yaml @@ -23,12 +23,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -45,7 +45,6 @@ operation(): | X[rd] = (src1 * src2)[XLEN-1:0]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulh.yaml b/arch/inst/M/mulh.yaml index 3bb7d5b0a..d36c6b79f 100644 --- a/arch/inst/M/mulh.yaml +++ b/arch/inst/M/mulh.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | # grab the high half of the result, and put it in rd X[rd] = (src1 * src2)[(xlen()*8'd2)-1:xlen()]; - - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulhsu.yaml b/arch/inst/M/mulhsu.yaml index 3fc37753b..7b92c2af5 100644 --- a/arch/inst/M/mulhsu.yaml +++ b/arch/inst/M/mulhsu.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -46,7 +46,6 @@ operation(): | X[rd] = (src1 * src2)[(XLEN*8'd2)-1:XLEN]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulhu.yaml b/arch/inst/M/mulhu.yaml index 436668a0c..123e089cf 100644 --- a/arch/inst/M/mulhu.yaml +++ b/arch/inst/M/mulhu.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -45,7 +45,6 @@ operation(): | X[rd] = (src1 * src2)[(XLEN*8'd2)-1:XLEN]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index bd6573725..d2a24afee 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -21,12 +21,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | # return the sign-extended result X[rd] = {{32{sign_bit}}, result}; - - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/rem.yaml b/arch/inst/M/rem.yaml index 06367f68c..acd700674 100644 --- a/arch/inst/M/rem.yaml +++ b/arch/inst/M/rem.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -48,7 +48,6 @@ operation(): | X[rd] = $signed(src1) % $signed(src2); } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remu.yaml b/arch/inst/M/remu.yaml index c668b94b5..0d00d5005 100644 --- a/arch/inst/M/remu.yaml +++ b/arch/inst/M/remu.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,7 +38,6 @@ operation(): | X[rd] = src1 % src2; } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index 4a4b348fa..c765fa4a6 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -14,12 +14,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------111-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index 2c2a1500a..f03753412 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------110-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -54,7 +54,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - sail(): | { if extension("M") then { diff --git a/arch/inst/Q/fadd.q.yaml b/arch/inst/Q/fadd.q.yaml index 3c9886e77..32c561bbb 100644 --- a/arch/inst/Q/fadd.q.yaml +++ b/arch/inst/Q/fadd.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0000011------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fclass.q.yaml b/arch/inst/Q/fclass.q.yaml index 230ff7773..fb099eae8 100644 --- a/arch/inst/Q/fclass.q.yaml +++ b/arch/inst/Q/fclass.q.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1 encoding: match: 111001100000-----001-----1010011 variables: - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.d.q.yaml b/arch/inst/Q/fcvt.d.q.yaml index 899950f8a..cd88087b8 100644 --- a/arch/inst/Q/fcvt.d.q.yaml +++ b/arch/inst/Q/fcvt.d.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, rm encoding: match: 010000100011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.h.q.yaml b/arch/inst/Q/fcvt.h.q.yaml index 223ed9024..8c56e8f78 100644 --- a/arch/inst/Q/fcvt.h.q.yaml +++ b/arch/inst/Q/fcvt.h.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.h.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfh] assembly: xd, qs1, rm encoding: match: 010001000011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.l.q.yaml b/arch/inst/Q/fcvt.l.q.yaml index aae2df1a0..b417279ee 100644 --- a/arch/inst/Q/fcvt.l.q.yaml +++ b/arch/inst/Q/fcvt.l.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.l.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: xd, qs1, rm encoding: match: 110001100010-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.lu.q.yaml b/arch/inst/Q/fcvt.lu.q.yaml index 1c75d28f0..ef9bcabd2 100644 --- a/arch/inst/Q/fcvt.lu.q.yaml +++ b/arch/inst/Q/fcvt.lu.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.lu.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, hs1, rm encoding: match: 110001100011-------------1010011 variables: - - name: hs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: hs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.d.yaml b/arch/inst/Q/fcvt.q.d.yaml index ce1ae3943..5272b5d1f 100644 --- a/arch/inst/Q/fcvt.q.d.yaml +++ b/arch/inst/Q/fcvt.q.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: dd, fs1, rm encoding: match: 010001100001-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: dd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: dd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.h.yaml b/arch/inst/Q/fcvt.q.h.yaml index 541f2e10b..2b7e7fe09 100644 --- a/arch/inst/Q/fcvt.q.h.yaml +++ b/arch/inst/Q/fcvt.q.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfh] assembly: hd, qs1, rm encoding: match: 010001100010-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: hd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: hd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.l.yaml b/arch/inst/Q/fcvt.q.l.yaml index 092d57110..a9f1b7639 100644 --- a/arch/inst/Q/fcvt.q.l.yaml +++ b/arch/inst/Q/fcvt.q.l.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, xs1, rm encoding: match: 110101100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.lu.yaml b/arch/inst/Q/fcvt.q.lu.yaml index 01572ba4a..a3ec07da4 100644 --- a/arch/inst/Q/fcvt.q.lu.yaml +++ b/arch/inst/Q/fcvt.q.lu.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, xs1, rm encoding: match: 110101100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.s.yaml b/arch/inst/Q/fcvt.q.s.yaml index 6f4024c5b..0583e9229 100644 --- a/arch/inst/Q/fcvt.q.s.yaml +++ b/arch/inst/Q/fcvt.q.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, fs1, rm encoding: match: 010001100000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.w.yaml b/arch/inst/Q/fcvt.q.w.yaml index d92b57d35..3303a5da4 100644 --- a/arch/inst/Q/fcvt.q.w.yaml +++ b/arch/inst/Q/fcvt.q.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: fd, xs1, rm encoding: match: 110101100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.wu.yaml b/arch/inst/Q/fcvt.q.wu.yaml index 05c0da5e1..7a27e4e43 100644 --- a/arch/inst/Q/fcvt.q.wu.yaml +++ b/arch/inst/Q/fcvt.q.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, xs1, rm encoding: match: 110101100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.s.q.yaml b/arch/inst/Q/fcvt.s.q.yaml index a772446da..92d048728 100644 --- a/arch/inst/Q/fcvt.s.q.yaml +++ b/arch/inst/Q/fcvt.s.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: fd, qs1, rm encoding: match: 010000000011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.w.q.yaml b/arch/inst/Q/fcvt.w.q.yaml index 93b69f624..9fb598fbb 100644 --- a/arch/inst/Q/fcvt.w.q.yaml +++ b/arch/inst/Q/fcvt.w.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, rm encoding: match: 110001100000-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.wu.q.yaml b/arch/inst/Q/fcvt.wu.q.yaml index 5d66b2af9..688cc1a11 100644 --- a/arch/inst/Q/fcvt.wu.q.yaml +++ b/arch/inst/Q/fcvt.wu.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, xs1, rm encoding: match: 110001100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fdiv.q.yaml b/arch/inst/Q/fdiv.q.yaml index 63e3fd2f8..2ccbf8daf 100644 --- a/arch/inst/Q/fdiv.q.yaml +++ b/arch/inst/Q/fdiv.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0001111------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/feq.q.yaml b/arch/inst/Q/feq.q.yaml index 14286fb68..f792e1e39 100644 --- a/arch/inst/Q/feq.q.yaml +++ b/arch/inst/Q/feq.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fle.q.yaml b/arch/inst/Q/fle.q.yaml index 9ad903ba2..0c8c441cc 100644 --- a/arch/inst/Q/fle.q.yaml +++ b/arch/inst/Q/fle.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------000-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fleq.q.yaml b/arch/inst/Q/fleq.q.yaml index 5cb9b831e..cd6ed983a 100644 --- a/arch/inst/Q/fleq.q.yaml +++ b/arch/inst/Q/fleq.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: xd, qs1, qs2 encoding: match: 1010011----------100-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fli.q.yaml b/arch/inst/Q/fli.q.yaml index aa7273830..5d8005c9b 100644 --- a/arch/inst/Q/fli.q.yaml +++ b/arch/inst/Q/fli.q.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: fd, qs1 encoding: match: 111101100001-----000-----1010011 variables: - - name: qs1 - location: 19-15 - - name: fd - location: 11-7 + - name: qs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/flq.yaml b/arch/inst/Q/flq.yaml index d013be44a..434467100 100644 --- a/arch/inst/Q/flq.yaml +++ b/arch/inst/Q/flq.yaml @@ -5,18 +5,18 @@ kind: instruction name: flq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, xs1, imm encoding: match: -----------------100-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: qd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/flt.q.yaml b/arch/inst/Q/flt.q.yaml index 5a400c776..ef0ea0ee1 100644 --- a/arch/inst/Q/flt.q.yaml +++ b/arch/inst/Q/flt.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fltq.q.yaml b/arch/inst/Q/fltq.q.yaml index b80f30f47..d5a341ff1 100644 --- a/arch/inst/Q/fltq.q.yaml +++ b/arch/inst/Q/fltq.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 1010011----------101-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmadd.q.yaml b/arch/inst/Q/fmadd.q.yaml index 7977f8f95..25a384af8 100644 --- a/arch/inst/Q/fmadd.q.yaml +++ b/arch/inst/Q/fmadd.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1000011 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmax.q.yaml b/arch/inst/Q/fmax.q.yaml index ff2069f09..60ba1c250 100644 --- a/arch/inst/Q/fmax.q.yaml +++ b/arch/inst/Q/fmax.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010111----------001-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmaxm.q.yaml b/arch/inst/Q/fmaxm.q.yaml index 9ecca0aec..2cf629674 100644 --- a/arch/inst/Q/fmaxm.q.yaml +++ b/arch/inst/Q/fmaxm.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 0010111----------011-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmin.q.yaml b/arch/inst/Q/fmin.q.yaml index 62f30485b..bf44bb8d1 100644 --- a/arch/inst/Q/fmin.q.yaml +++ b/arch/inst/Q/fmin.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, xs1, xs2 encoding: match: 0010111----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fminm.q.yaml b/arch/inst/Q/fminm.q.yaml index 516edc0bc..750626e14 100644 --- a/arch/inst/Q/fminm.q.yaml +++ b/arch/inst/Q/fminm.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 0010111----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmsub.q.yaml b/arch/inst/Q/fmsub.q.yaml index c92ed5350..d89c36c47 100644 --- a/arch/inst/Q/fmsub.q.yaml +++ b/arch/inst/Q/fmsub.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1000111 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmul.q.yaml b/arch/inst/Q/fmul.q.yaml index c983cf8fb..f7088036a 100644 --- a/arch/inst/Q/fmul.q.yaml +++ b/arch/inst/Q/fmul.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0001011------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmvh.x.q.yaml b/arch/inst/Q/fmvh.x.q.yaml index f067240ac..4e22012a2 100644 --- a/arch/inst/Q/fmvh.x.q.yaml +++ b/arch/inst/Q/fmvh.x.q.yaml @@ -5,7 +5,7 @@ kind: instruction name: fmvh.x.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] base: 64 @@ -13,10 +13,10 @@ assembly: xd, qs1 encoding: match: 111001100001-----000-----1010011 variables: - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmvp.q.x.yaml b/arch/inst/Q/fmvp.q.x.yaml index 258e7ccc8..e05d06368 100644 --- a/arch/inst/Q/fmvp.q.x.yaml +++ b/arch/inst/Q/fmvp.q.x.yaml @@ -5,7 +5,7 @@ kind: instruction name: fmvp.q.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] base: 64 @@ -13,12 +13,12 @@ assembly: qd, xs1, xs2 encoding: match: 1011011----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fnmadd.q.yaml b/arch/inst/Q/fnmadd.q.yaml index de290b9f3..5bd3b6d4b 100644 --- a/arch/inst/Q/fnmadd.q.yaml +++ b/arch/inst/Q/fnmadd.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1001111 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fnmsub.q.yaml b/arch/inst/Q/fnmsub.q.yaml index 805f14c42..8ef81fe0c 100644 --- a/arch/inst/Q/fnmsub.q.yaml +++ b/arch/inst/Q/fnmsub.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1001011 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fround.q.yaml b/arch/inst/Q/fround.q.yaml index ea1718ab4..a430445f3 100644 --- a/arch/inst/Q/fround.q.yaml +++ b/arch/inst/Q/fround.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, rm encoding: match: 010001100100-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/froundnx.q.yaml b/arch/inst/Q/froundnx.q.yaml index ffea7e08c..360bc9fc2 100644 --- a/arch/inst/Q/froundnx.q.yaml +++ b/arch/inst/Q/froundnx.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, rm encoding: match: 010001100101-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fsgnj.q.yaml b/arch/inst/Q/fsgnj.q.yaml index 489b84990..20dbe8eef 100644 --- a/arch/inst/Q/fsgnj.q.yaml +++ b/arch/inst/Q/fsgnj.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------000-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fmv.q + - when: (rs2 == rs1) + to: fmv.q operation(): | diff --git a/arch/inst/Q/fsgnjn.q.yaml b/arch/inst/Q/fsgnjn.q.yaml index 3dc53bba5..c0e6e2dc4 100644 --- a/arch/inst/Q/fsgnjn.q.yaml +++ b/arch/inst/Q/fsgnjn.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------001-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fneg.q + - when: (rs2 == rs1) + to: fneg.q operation(): | diff --git a/arch/inst/Q/fsgnjx.q.yaml b/arch/inst/Q/fsgnjx.q.yaml index 2cec0796a..f3f2b13d8 100644 --- a/arch/inst/Q/fsgnjx.q.yaml +++ b/arch/inst/Q/fsgnjx.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fabs.q + - when: (rs2 == rs1) + to: fabs.q operation(): | diff --git a/arch/inst/Q/fsq.yaml b/arch/inst/Q/fsq.yaml index 1b74624a5..dfe6e4ad4 100644 --- a/arch/inst/Q/fsq.yaml +++ b/arch/inst/Q/fsq.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xs1, qs2, imm encoding: match: -----------------100-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: qs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: qs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/Q/fsqrt.q.yaml b/arch/inst/Q/fsqrt.q.yaml index 9fa9ab346..9c0e11e53 100644 --- a/arch/inst/Q/fsqrt.q.yaml +++ b/arch/inst/Q/fsqrt.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, rm encoding: match: 010111100000-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fsub.q.yaml b/arch/inst/Q/fsub.q.yaml index 0db8b161c..554abb1a7 100644 --- a/arch/inst/Q/fsub.q.yaml +++ b/arch/inst/Q/fsub.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0000111------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/S/sfence.vma.yaml b/arch/inst/S/sfence.vma.yaml index 8852bf1cf..ac877929a 100644 --- a/arch/inst/S/sfence.vma.yaml +++ b/arch/inst/S/sfence.vma.yaml @@ -211,10 +211,10 @@ assembly: xs1, xs2 encoding: match: 0001001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: never @@ -305,8 +305,6 @@ operation(): | # else, silently do nothing } - - sail(): | { let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1)); diff --git a/arch/inst/S/sret.yaml b/arch/inst/S/sret.yaml index 3dd2755d1..3f003f392 100644 --- a/arch/inst/S/sret.yaml +++ b/arch/inst/S/sret.yaml @@ -47,7 +47,7 @@ description: | definedBy: S assembly: "" encoding: - match: '00010000001000000000000001110011' + match: "00010000001000000000000001110011" access: s: sometimes u: never @@ -126,7 +126,6 @@ operation(): | $pc = $bits(CSR[vsepc]); } - sail(): | { let sret_illegal : bool = match cur_privilege { diff --git a/arch/inst/Sdext/dret.yaml b/arch/inst/Sdext/dret.yaml index e8e21a0ea..ee65a75d5 100644 --- a/arch/inst/Sdext/dret.yaml +++ b/arch/inst/Sdext/dret.yaml @@ -5,11 +5,11 @@ kind: instruction name: dret long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Sdext assembly: dret encoding: - match: '01111011001000000000000001110011' + match: "01111011001000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index f5bd33fb3..b8f99a943 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -5,11 +5,11 @@ kind: instruction name: sctrclr long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Smdbltrp assembly: sctrclr encoding: - match: '00010000010000000000000001110011' + match: "00010000010000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Smrnmi/mnret.yaml b/arch/inst/Smrnmi/mnret.yaml index 5019c47bd..a91ce53c1 100644 --- a/arch/inst/Smrnmi/mnret.yaml +++ b/arch/inst/Smrnmi/mnret.yaml @@ -5,11 +5,11 @@ kind: instruction name: mnret long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Smrnmi assembly: mnret encoding: - match: '01110000001000000000000001110011' + match: "01110000001000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Svinval/hinval.gvma.yaml b/arch/inst/Svinval/hinval.gvma.yaml index e53479102..d8caa7663 100644 --- a/arch/inst/Svinval/hinval.gvma.yaml +++ b/arch/inst/Svinval/hinval.gvma.yaml @@ -6,15 +6,15 @@ name: hinval.gvma long_name: Invalidate cached address translations definedBy: allOf: - - Svinval - - H + - Svinval + - H encoding: match: 0110011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: | `hinval.gvma` has the same semantics as `sinval.vma` except that it combines with `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.gvma` and uses VMID instead of ASID. diff --git a/arch/inst/Svinval/hinval.vvma.yaml b/arch/inst/Svinval/hinval.vvma.yaml index 4b65e53c2..5af922825 100644 --- a/arch/inst/Svinval/hinval.vvma.yaml +++ b/arch/inst/Svinval/hinval.vvma.yaml @@ -6,15 +6,15 @@ name: hinval.vvma long_name: Invalidate cached address translations definedBy: allOf: - - Svinval - - H + - Svinval + - H encoding: match: 0010011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: | `hinval.vvma` has the same semantics as `sinval.vma` except that it combines with `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.vvma`. diff --git a/arch/inst/Svinval/sinval.vma.yaml b/arch/inst/Svinval/sinval.vma.yaml index 76f77099e..8ef06b74f 100644 --- a/arch/inst/Svinval/sinval.vma.yaml +++ b/arch/inst/Svinval/sinval.vma.yaml @@ -8,10 +8,10 @@ definedBy: Svinval encoding: match: 0001011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: The `sinval.vma` instruction invalidates any address-translation cache entries that an `sfence.vma` instruction with the same values of rs1 and rs2 would invalidate. diff --git a/arch/inst/V/vaadd.vv.yaml b/arch/inst/V/vaadd.vv.yaml index 3cbcf1241..0b6966fe7 100644 --- a/arch/inst/V/vaadd.vv.yaml +++ b/arch/inst/V/vaadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaadd.vx.yaml b/arch/inst/V/vaadd.vx.yaml index e80615613..03e13b0d4 100644 --- a/arch/inst/V/vaadd.vx.yaml +++ b/arch/inst/V/vaadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaaddu.vv.yaml b/arch/inst/V/vaaddu.vv.yaml index 6c9876175..3b9c7562f 100644 --- a/arch/inst/V/vaaddu.vv.yaml +++ b/arch/inst/V/vaaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaaddu.vx.yaml b/arch/inst/V/vaaddu.vx.yaml index ed14af74b..90164d1ef 100644 --- a/arch/inst/V/vaaddu.vx.yaml +++ b/arch/inst/V/vaaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vim.yaml b/arch/inst/V/vadc.vim.yaml index a071d8dce..fe2eefa6c 100644 --- a/arch/inst/V/vadc.vim.yaml +++ b/arch/inst/V/vadc.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100000----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vvm.yaml b/arch/inst/V/vadc.vvm.yaml index 8d3df8a97..a2049511e 100644 --- a/arch/inst/V/vadc.vvm.yaml +++ b/arch/inst/V/vadc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100000----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vxm.yaml b/arch/inst/V/vadc.vxm.yaml index 5ea996a2a..b2e2c3978 100644 --- a/arch/inst/V/vadc.vxm.yaml +++ b/arch/inst/V/vadc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100000----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadd.vi.yaml b/arch/inst/V/vadd.vi.yaml index d1f92d001..c12f08144 100644 --- a/arch/inst/V/vadd.vi.yaml +++ b/arch/inst/V/vadd.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 000000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadd.vv.yaml b/arch/inst/V/vadd.vv.yaml index 889991a14..a280ed6b4 100644 --- a/arch/inst/V/vadd.vv.yaml +++ b/arch/inst/V/vadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vadd.vx.yaml b/arch/inst/V/vadd.vx.yaml index fde718be1..61127518b 100644 --- a/arch/inst/V/vadd.vx.yaml +++ b/arch/inst/V/vadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vand.vi.yaml b/arch/inst/V/vand.vi.yaml index fe43e62fd..d6916defd 100644 --- a/arch/inst/V/vand.vi.yaml +++ b/arch/inst/V/vand.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vand.vv.yaml b/arch/inst/V/vand.vv.yaml index f01644810..afb8dc228 100644 --- a/arch/inst/V/vand.vv.yaml +++ b/arch/inst/V/vand.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vand.vx.yaml b/arch/inst/V/vand.vx.yaml index efeb6977b..6b6318c25 100644 --- a/arch/inst/V/vand.vx.yaml +++ b/arch/inst/V/vand.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasub.vv.yaml b/arch/inst/V/vasub.vv.yaml index 7d1b7c282..645f2a589 100644 --- a/arch/inst/V/vasub.vv.yaml +++ b/arch/inst/V/vasub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasub.vx.yaml b/arch/inst/V/vasub.vx.yaml index 54e8f87c6..d7112c432 100644 --- a/arch/inst/V/vasub.vx.yaml +++ b/arch/inst/V/vasub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasubu.vv.yaml b/arch/inst/V/vasubu.vv.yaml index bc24e0a97..c1005068d 100644 --- a/arch/inst/V/vasubu.vv.yaml +++ b/arch/inst/V/vasubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasubu.vx.yaml b/arch/inst/V/vasubu.vx.yaml index af8d897cc..0b21717cd 100644 --- a/arch/inst/V/vasubu.vx.yaml +++ b/arch/inst/V/vasubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vcompress.vm.yaml b/arch/inst/V/vcompress.vm.yaml index fd84e7a33..84653e204 100644 --- a/arch/inst/V/vcompress.vm.yaml +++ b/arch/inst/V/vcompress.vm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vcompress.vm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0101111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vcpop.m.yaml b/arch/inst/V/vcpop.m.yaml index 19bea2ad8..b51722188 100644 --- a/arch/inst/V/vcpop.m.yaml +++ b/arch/inst/V/vcpop.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vcpop.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xd encoding: match: 010000------10000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vdiv.vv.yaml b/arch/inst/V/vdiv.vv.yaml index a11d7fca2..e97abdf49 100644 --- a/arch/inst/V/vdiv.vv.yaml +++ b/arch/inst/V/vdiv.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdiv.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdiv.vx.yaml b/arch/inst/V/vdiv.vx.yaml index 88fbb442a..cc006e8a1 100644 --- a/arch/inst/V/vdiv.vx.yaml +++ b/arch/inst/V/vdiv.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdiv.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdivu.vv.yaml b/arch/inst/V/vdivu.vv.yaml index c0f330bb1..d7b4d8ea4 100644 --- a/arch/inst/V/vdivu.vv.yaml +++ b/arch/inst/V/vdivu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdivu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdivu.vx.yaml b/arch/inst/V/vdivu.vx.yaml index ebf0b05f1..cbe3bfe30 100644 --- a/arch/inst/V/vdivu.vx.yaml +++ b/arch/inst/V/vdivu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdivu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfadd.vf.yaml b/arch/inst/V/vfadd.vf.yaml index 43a191d64..5aee28612 100644 --- a/arch/inst/V/vfadd.vf.yaml +++ b/arch/inst/V/vfadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfadd.vv.yaml b/arch/inst/V/vfadd.vv.yaml index e53b9c030..156a55057 100644 --- a/arch/inst/V/vfadd.vv.yaml +++ b/arch/inst/V/vfadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfclass.v.yaml b/arch/inst/V/vfclass.v.yaml index 72947448c..b78b61c39 100644 --- a/arch/inst/V/vfclass.v.yaml +++ b/arch/inst/V/vfclass.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfclass.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------10000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.f.x.v.yaml b/arch/inst/V/vfcvt.f.x.v.yaml index c94dd1143..2a543ff27 100644 --- a/arch/inst/V/vfcvt.f.x.v.yaml +++ b/arch/inst/V/vfcvt.f.x.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.f.x.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.f.xu.v.yaml b/arch/inst/V/vfcvt.f.xu.v.yaml index f0b93c864..78ae990d5 100644 --- a/arch/inst/V/vfcvt.f.xu.v.yaml +++ b/arch/inst/V/vfcvt.f.xu.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.f.xu.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.rtz.x.f.v.yaml b/arch/inst/V/vfcvt.rtz.x.f.v.yaml index f2f2d7a34..1cd361737 100644 --- a/arch/inst/V/vfcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.rtz.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml index 111c59984..44c874e15 100644 --- a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.rtz.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.x.f.v.yaml b/arch/inst/V/vfcvt.x.f.v.yaml index 8cca1f4db..51af8e423 100644 --- a/arch/inst/V/vfcvt.x.f.v.yaml +++ b/arch/inst/V/vfcvt.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.xu.f.v.yaml b/arch/inst/V/vfcvt.xu.f.v.yaml index 7fa8aae9b..a411ca375 100644 --- a/arch/inst/V/vfcvt.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfdiv.vf.yaml b/arch/inst/V/vfdiv.vf.yaml index 131540b4e..2a01a08b6 100644 --- a/arch/inst/V/vfdiv.vf.yaml +++ b/arch/inst/V/vfdiv.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfdiv.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfdiv.vv.yaml b/arch/inst/V/vfdiv.vv.yaml index 6590ecbf6..756d7b686 100644 --- a/arch/inst/V/vfdiv.vv.yaml +++ b/arch/inst/V/vfdiv.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfdiv.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfirst.m.yaml b/arch/inst/V/vfirst.m.yaml index c05ebe85c..32dc051c7 100644 --- a/arch/inst/V/vfirst.m.yaml +++ b/arch/inst/V/vfirst.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfirst.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xd encoding: match: 010000------10001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfmacc.vf.yaml b/arch/inst/V/vfmacc.vf.yaml index 9c6529d0c..9344bec1f 100644 --- a/arch/inst/V/vfmacc.vf.yaml +++ b/arch/inst/V/vfmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmacc.vv.yaml b/arch/inst/V/vfmacc.vv.yaml index ae596e3e3..c47710add 100644 --- a/arch/inst/V/vfmacc.vv.yaml +++ b/arch/inst/V/vfmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmadd.vf.yaml b/arch/inst/V/vfmadd.vf.yaml index 14d73f06f..11fc3a7fa 100644 --- a/arch/inst/V/vfmadd.vf.yaml +++ b/arch/inst/V/vfmadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmadd.vv.yaml b/arch/inst/V/vfmadd.vv.yaml index 2541125be..91364916f 100644 --- a/arch/inst/V/vfmadd.vv.yaml +++ b/arch/inst/V/vfmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmax.vf.yaml b/arch/inst/V/vfmax.vf.yaml index 0cc30b734..e4ce7d1db 100644 --- a/arch/inst/V/vfmax.vf.yaml +++ b/arch/inst/V/vfmax.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmax.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmax.vv.yaml b/arch/inst/V/vfmax.vv.yaml index 743ea0f91..ade095ba5 100644 --- a/arch/inst/V/vfmax.vv.yaml +++ b/arch/inst/V/vfmax.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmax.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmerge.vfm.yaml b/arch/inst/V/vfmerge.vfm.yaml index 86dd3a028..45d2f63d3 100644 --- a/arch/inst/V/vfmerge.vfm.yaml +++ b/arch/inst/V/vfmerge.vfm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfmerge.vfm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0101110----------101-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmin.vf.yaml b/arch/inst/V/vfmin.vf.yaml index ab540d32b..49037450c 100644 --- a/arch/inst/V/vfmin.vf.yaml +++ b/arch/inst/V/vfmin.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmin.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmin.vv.yaml b/arch/inst/V/vfmin.vv.yaml index 991efa7e8..5ccf62497 100644 --- a/arch/inst/V/vfmin.vv.yaml +++ b/arch/inst/V/vfmin.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmin.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsac.vf.yaml b/arch/inst/V/vfmsac.vf.yaml index 34c3c371b..401febe42 100644 --- a/arch/inst/V/vfmsac.vf.yaml +++ b/arch/inst/V/vfmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsac.vv.yaml b/arch/inst/V/vfmsac.vv.yaml index 1e734383a..3ff6fb6c0 100644 --- a/arch/inst/V/vfmsac.vv.yaml +++ b/arch/inst/V/vfmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsub.vf.yaml b/arch/inst/V/vfmsub.vf.yaml index ced3598cb..9029bbfe4 100644 --- a/arch/inst/V/vfmsub.vf.yaml +++ b/arch/inst/V/vfmsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsub.vv.yaml b/arch/inst/V/vfmsub.vv.yaml index e33500bb5..6564812fc 100644 --- a/arch/inst/V/vfmsub.vv.yaml +++ b/arch/inst/V/vfmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmul.vf.yaml b/arch/inst/V/vfmul.vf.yaml index 74a603000..c12c2b1a4 100644 --- a/arch/inst/V/vfmul.vf.yaml +++ b/arch/inst/V/vfmul.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmul.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmul.vv.yaml b/arch/inst/V/vfmul.vv.yaml index f1cb3a8c7..f4a2fc240 100644 --- a/arch/inst/V/vfmul.vv.yaml +++ b/arch/inst/V/vfmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.f.s.yaml b/arch/inst/V/vfmv.f.s.yaml index c3f72cd96..b1107b27f 100644 --- a/arch/inst/V/vfmv.f.s.yaml +++ b/arch/inst/V/vfmv.f.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.f.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xd encoding: match: 0100001-----00000001-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.s.f.yaml b/arch/inst/V/vfmv.s.f.yaml index 80b57dc40..37c250ef7 100644 --- a/arch/inst/V/vfmv.s.f.yaml +++ b/arch/inst/V/vfmv.s.f.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.s.f long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010000100000-----101-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.v.f.yaml b/arch/inst/V/vfmv.v.f.yaml index e1fe60deb..28e2405a8 100644 --- a/arch/inst/V/vfmv.v.f.yaml +++ b/arch/inst/V/vfmv.v.f.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.v.f long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010111100000-----101-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.f.w.yaml b/arch/inst/V/vfncvt.f.f.w.yaml index d07719336..6f3779646 100644 --- a/arch/inst/V/vfncvt.f.f.w.yaml +++ b/arch/inst/V/vfncvt.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.x.w.yaml b/arch/inst/V/vfncvt.f.x.w.yaml index 64076200d..021461724 100644 --- a/arch/inst/V/vfncvt.f.x.w.yaml +++ b/arch/inst/V/vfncvt.f.x.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.x.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.xu.w.yaml b/arch/inst/V/vfncvt.f.xu.w.yaml index 1ffb9a8cb..46a2663ba 100644 --- a/arch/inst/V/vfncvt.f.xu.w.yaml +++ b/arch/inst/V/vfncvt.f.xu.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.xu.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rod.f.f.w.yaml b/arch/inst/V/vfncvt.rod.f.f.w.yaml index 7b5c051c7..02555f003 100644 --- a/arch/inst/V/vfncvt.rod.f.f.w.yaml +++ b/arch/inst/V/vfncvt.rod.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rod.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rtz.x.f.w.yaml b/arch/inst/V/vfncvt.rtz.x.f.w.yaml index a4537a2e7..ebcbdd4b4 100644 --- a/arch/inst/V/vfncvt.rtz.x.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.x.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rtz.x.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml index 62bede1c4..0b3f874d5 100644 --- a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rtz.xu.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.x.f.w.yaml b/arch/inst/V/vfncvt.x.f.w.yaml index 75ff14b03..f0877ef3f 100644 --- a/arch/inst/V/vfncvt.x.f.w.yaml +++ b/arch/inst/V/vfncvt.x.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.x.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.xu.f.w.yaml b/arch/inst/V/vfncvt.xu.f.w.yaml index 37345ccd0..e0560c4db 100644 --- a/arch/inst/V/vfncvt.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.xu.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.xu.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmacc.vf.yaml b/arch/inst/V/vfnmacc.vf.yaml index b2c079a45..a4d07f05d 100644 --- a/arch/inst/V/vfnmacc.vf.yaml +++ b/arch/inst/V/vfnmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmacc.vv.yaml b/arch/inst/V/vfnmacc.vv.yaml index 7d09fa94d..109d253f2 100644 --- a/arch/inst/V/vfnmacc.vv.yaml +++ b/arch/inst/V/vfnmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmadd.vf.yaml b/arch/inst/V/vfnmadd.vf.yaml index 4023db2a3..96b4c2cb5 100644 --- a/arch/inst/V/vfnmadd.vf.yaml +++ b/arch/inst/V/vfnmadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmadd.vv.yaml b/arch/inst/V/vfnmadd.vv.yaml index 2f25198c4..c180cfa5b 100644 --- a/arch/inst/V/vfnmadd.vv.yaml +++ b/arch/inst/V/vfnmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsac.vf.yaml b/arch/inst/V/vfnmsac.vf.yaml index 2e2a4c720..77d9b7fd0 100644 --- a/arch/inst/V/vfnmsac.vf.yaml +++ b/arch/inst/V/vfnmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsac.vv.yaml b/arch/inst/V/vfnmsac.vv.yaml index 28eddb89c..8531bcae5 100644 --- a/arch/inst/V/vfnmsac.vv.yaml +++ b/arch/inst/V/vfnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsub.vf.yaml b/arch/inst/V/vfnmsub.vf.yaml index efab79dae..61aa40ed2 100644 --- a/arch/inst/V/vfnmsub.vf.yaml +++ b/arch/inst/V/vfnmsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsub.vv.yaml b/arch/inst/V/vfnmsub.vv.yaml index d279ebff9..fb18f3493 100644 --- a/arch/inst/V/vfnmsub.vv.yaml +++ b/arch/inst/V/vfnmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrdiv.vf.yaml b/arch/inst/V/vfrdiv.vf.yaml index 78f64d7f1..2b36ad2c5 100644 --- a/arch/inst/V/vfrdiv.vf.yaml +++ b/arch/inst/V/vfrdiv.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfrdiv.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrec7.v.yaml b/arch/inst/V/vfrec7.v.yaml index 40a7439bd..e63995f7e 100644 --- a/arch/inst/V/vfrec7.v.yaml +++ b/arch/inst/V/vfrec7.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfrec7.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfredmax.vs.yaml b/arch/inst/V/vfredmax.vs.yaml index 12277a66b..6473da80f 100644 --- a/arch/inst/V/vfredmax.vs.yaml +++ b/arch/inst/V/vfredmax.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredmax.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredmin.vs.yaml b/arch/inst/V/vfredmin.vs.yaml index b4609fd35..2edeecb2b 100644 --- a/arch/inst/V/vfredmin.vs.yaml +++ b/arch/inst/V/vfredmin.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredmin.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredosum.vs.yaml b/arch/inst/V/vfredosum.vs.yaml index bea668e79..67d6af832 100644 --- a/arch/inst/V/vfredosum.vs.yaml +++ b/arch/inst/V/vfredosum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredosum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredusum.vs.yaml b/arch/inst/V/vfredusum.vs.yaml index b8e38ee7d..a46ab889d 100644 --- a/arch/inst/V/vfredusum.vs.yaml +++ b/arch/inst/V/vfredusum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredusum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfrsqrt7.v.yaml b/arch/inst/V/vfrsqrt7.v.yaml index fbbf128cd..8294f7010 100644 --- a/arch/inst/V/vfrsqrt7.v.yaml +++ b/arch/inst/V/vfrsqrt7.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfrsqrt7.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrsub.vf.yaml b/arch/inst/V/vfrsub.vf.yaml index 1dea2de7e..6f9f52465 100644 --- a/arch/inst/V/vfrsub.vf.yaml +++ b/arch/inst/V/vfrsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfrsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnj.vf.yaml b/arch/inst/V/vfsgnj.vf.yaml index b5bad7a7b..95f9a0483 100644 --- a/arch/inst/V/vfsgnj.vf.yaml +++ b/arch/inst/V/vfsgnj.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnj.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnj.vv.yaml b/arch/inst/V/vfsgnj.vv.yaml index c62ba75b2..58fbf938c 100644 --- a/arch/inst/V/vfsgnj.vv.yaml +++ b/arch/inst/V/vfsgnj.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnj.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjn.vf.yaml b/arch/inst/V/vfsgnjn.vf.yaml index aadd118ee..1ebc15601 100644 --- a/arch/inst/V/vfsgnjn.vf.yaml +++ b/arch/inst/V/vfsgnjn.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjn.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjn.vv.yaml b/arch/inst/V/vfsgnjn.vv.yaml index f5e6507af..e6a04c953 100644 --- a/arch/inst/V/vfsgnjn.vv.yaml +++ b/arch/inst/V/vfsgnjn.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjn.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjx.vf.yaml b/arch/inst/V/vfsgnjx.vf.yaml index 39e3e1bcc..21860c151 100644 --- a/arch/inst/V/vfsgnjx.vf.yaml +++ b/arch/inst/V/vfsgnjx.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjx.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjx.vv.yaml b/arch/inst/V/vfsgnjx.vv.yaml index 7f674c9dc..31f6fa429 100644 --- a/arch/inst/V/vfsgnjx.vv.yaml +++ b/arch/inst/V/vfsgnjx.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjx.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfslide1down.vf.yaml b/arch/inst/V/vfslide1down.vf.yaml index e30cfe155..988f74f06 100644 --- a/arch/inst/V/vfslide1down.vf.yaml +++ b/arch/inst/V/vfslide1down.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfslide1down.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfslide1up.vf.yaml b/arch/inst/V/vfslide1up.vf.yaml index eb6f1da87..2846b287b 100644 --- a/arch/inst/V/vfslide1up.vf.yaml +++ b/arch/inst/V/vfslide1up.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfslide1up.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsqrt.v.yaml b/arch/inst/V/vfsqrt.v.yaml index 9fa78136e..fad2f602b 100644 --- a/arch/inst/V/vfsqrt.v.yaml +++ b/arch/inst/V/vfsqrt.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfsqrt.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsub.vf.yaml b/arch/inst/V/vfsub.vf.yaml index d55004891..319c49e7f 100644 --- a/arch/inst/V/vfsub.vf.yaml +++ b/arch/inst/V/vfsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsub.vv.yaml b/arch/inst/V/vfsub.vv.yaml index 099d1ca6e..e28ca0eaf 100644 --- a/arch/inst/V/vfsub.vv.yaml +++ b/arch/inst/V/vfsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.vf.yaml b/arch/inst/V/vfwadd.vf.yaml index 8449fafc3..62ee2ff69 100644 --- a/arch/inst/V/vfwadd.vf.yaml +++ b/arch/inst/V/vfwadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.vv.yaml b/arch/inst/V/vfwadd.vv.yaml index fdc57af86..af3c01af8 100644 --- a/arch/inst/V/vfwadd.vv.yaml +++ b/arch/inst/V/vfwadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.wf.yaml b/arch/inst/V/vfwadd.wf.yaml index 6a169ba6a..6e27a8d14 100644 --- a/arch/inst/V/vfwadd.wf.yaml +++ b/arch/inst/V/vfwadd.wf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.wf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.wv.yaml b/arch/inst/V/vfwadd.wv.yaml index 668fde563..a5b5157ae 100644 --- a/arch/inst/V/vfwadd.wv.yaml +++ b/arch/inst/V/vfwadd.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.f.v.yaml b/arch/inst/V/vfwcvt.f.f.v.yaml index 13891efc9..c261e3e3c 100644 --- a/arch/inst/V/vfwcvt.f.f.v.yaml +++ b/arch/inst/V/vfwcvt.f.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.x.v.yaml b/arch/inst/V/vfwcvt.f.x.v.yaml index a4cac43c7..2ac1e9401 100644 --- a/arch/inst/V/vfwcvt.f.x.v.yaml +++ b/arch/inst/V/vfwcvt.f.x.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.x.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.xu.v.yaml b/arch/inst/V/vfwcvt.f.xu.v.yaml index 2451307f0..73bde966c 100644 --- a/arch/inst/V/vfwcvt.f.xu.v.yaml +++ b/arch/inst/V/vfwcvt.f.xu.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.xu.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml index ccd031fbb..cd30932ab 100644 --- a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.rtz.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml index 2df02a61b..a828b78e5 100644 --- a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.rtz.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.x.f.v.yaml b/arch/inst/V/vfwcvt.x.f.v.yaml index b6337cd14..4e69948bc 100644 --- a/arch/inst/V/vfwcvt.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.xu.f.v.yaml b/arch/inst/V/vfwcvt.xu.f.v.yaml index dc47501e7..a93aef64e 100644 --- a/arch/inst/V/vfwcvt.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmacc.vf.yaml b/arch/inst/V/vfwmacc.vf.yaml index bb3c336f8..7baff68b9 100644 --- a/arch/inst/V/vfwmacc.vf.yaml +++ b/arch/inst/V/vfwmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmacc.vv.yaml b/arch/inst/V/vfwmacc.vv.yaml index 18452f228..9e24da41e 100644 --- a/arch/inst/V/vfwmacc.vv.yaml +++ b/arch/inst/V/vfwmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmsac.vf.yaml b/arch/inst/V/vfwmsac.vf.yaml index 2b4821948..e1b5bbab3 100644 --- a/arch/inst/V/vfwmsac.vf.yaml +++ b/arch/inst/V/vfwmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmsac.vv.yaml b/arch/inst/V/vfwmsac.vv.yaml index 06a86bfb5..b2c9e3efd 100644 --- a/arch/inst/V/vfwmsac.vv.yaml +++ b/arch/inst/V/vfwmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmul.vf.yaml b/arch/inst/V/vfwmul.vf.yaml index c1b8c8982..fb34150d3 100644 --- a/arch/inst/V/vfwmul.vf.yaml +++ b/arch/inst/V/vfwmul.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmul.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmul.vv.yaml b/arch/inst/V/vfwmul.vv.yaml index e91a5c378..874a1c4cf 100644 --- a/arch/inst/V/vfwmul.vv.yaml +++ b/arch/inst/V/vfwmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmacc.vf.yaml b/arch/inst/V/vfwnmacc.vf.yaml index 67e5dcfe6..0111d351f 100644 --- a/arch/inst/V/vfwnmacc.vf.yaml +++ b/arch/inst/V/vfwnmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmacc.vv.yaml b/arch/inst/V/vfwnmacc.vv.yaml index 396840026..583c88594 100644 --- a/arch/inst/V/vfwnmacc.vv.yaml +++ b/arch/inst/V/vfwnmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmsac.vf.yaml b/arch/inst/V/vfwnmsac.vf.yaml index f5dc85df9..78dfdb841 100644 --- a/arch/inst/V/vfwnmsac.vf.yaml +++ b/arch/inst/V/vfwnmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmsac.vv.yaml b/arch/inst/V/vfwnmsac.vv.yaml index 17af8f339..915aa3aa1 100644 --- a/arch/inst/V/vfwnmsac.vv.yaml +++ b/arch/inst/V/vfwnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwredosum.vs.yaml b/arch/inst/V/vfwredosum.vs.yaml index ea97af98a..9c8e0d4aa 100644 --- a/arch/inst/V/vfwredosum.vs.yaml +++ b/arch/inst/V/vfwredosum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwredosum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfwredusum.vs.yaml b/arch/inst/V/vfwredusum.vs.yaml index b0e69de55..e04a02d0f 100644 --- a/arch/inst/V/vfwredusum.vs.yaml +++ b/arch/inst/V/vfwredusum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwredusum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfwsub.vf.yaml b/arch/inst/V/vfwsub.vf.yaml index d06f57f18..59a755dc2 100644 --- a/arch/inst/V/vfwsub.vf.yaml +++ b/arch/inst/V/vfwsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.vv.yaml b/arch/inst/V/vfwsub.vv.yaml index 02b06af2f..06e45d828 100644 --- a/arch/inst/V/vfwsub.vv.yaml +++ b/arch/inst/V/vfwsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.wf.yaml b/arch/inst/V/vfwsub.wf.yaml index 1ec5f744c..8b49b9772 100644 --- a/arch/inst/V/vfwsub.wf.yaml +++ b/arch/inst/V/vfwsub.wf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.wf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.wv.yaml b/arch/inst/V/vfwsub.wv.yaml index c60ee91d1..8412d8981 100644 --- a/arch/inst/V/vfwsub.wv.yaml +++ b/arch/inst/V/vfwsub.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vid.v.yaml b/arch/inst/V/vid.v.yaml index b5c27cc73..509ad1f9b 100644 --- a/arch/inst/V/vid.v.yaml +++ b/arch/inst/V/vid.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vid.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vd encoding: match: 010100-0000010001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/viota.m.yaml b/arch/inst/V/viota.m.yaml index 1991cdaa9..312dfe959 100644 --- a/arch/inst/V/viota.m.yaml +++ b/arch/inst/V/viota.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: viota.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------10000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vl1re16.v.yaml b/arch/inst/V/vl1re16.v.yaml index 0a6cb1075..97c243877 100644 --- a/arch/inst/V/vl1re16.v.yaml +++ b/arch/inst/V/vl1re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re32.v.yaml b/arch/inst/V/vl1re32.v.yaml index 294c7203e..f2e08f12b 100644 --- a/arch/inst/V/vl1re32.v.yaml +++ b/arch/inst/V/vl1re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re64.v.yaml b/arch/inst/V/vl1re64.v.yaml index 0c1a4e6a3..bd4ab27dc 100644 --- a/arch/inst/V/vl1re64.v.yaml +++ b/arch/inst/V/vl1re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re8.v.yaml b/arch/inst/V/vl1re8.v.yaml index 799791033..dacab09b3 100644 --- a/arch/inst/V/vl1re8.v.yaml +++ b/arch/inst/V/vl1re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re16.v.yaml b/arch/inst/V/vl2re16.v.yaml index e0cab471f..bc1a67666 100644 --- a/arch/inst/V/vl2re16.v.yaml +++ b/arch/inst/V/vl2re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re32.v.yaml b/arch/inst/V/vl2re32.v.yaml index e8e6aeb44..34bbc9537 100644 --- a/arch/inst/V/vl2re32.v.yaml +++ b/arch/inst/V/vl2re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re64.v.yaml b/arch/inst/V/vl2re64.v.yaml index 785489b92..bccb7e19b 100644 --- a/arch/inst/V/vl2re64.v.yaml +++ b/arch/inst/V/vl2re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re8.v.yaml b/arch/inst/V/vl2re8.v.yaml index 70f528b52..bc11729ce 100644 --- a/arch/inst/V/vl2re8.v.yaml +++ b/arch/inst/V/vl2re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re16.v.yaml b/arch/inst/V/vl4re16.v.yaml index 6a8533926..d3759bed8 100644 --- a/arch/inst/V/vl4re16.v.yaml +++ b/arch/inst/V/vl4re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re32.v.yaml b/arch/inst/V/vl4re32.v.yaml index 50ffcb9b7..556b565aa 100644 --- a/arch/inst/V/vl4re32.v.yaml +++ b/arch/inst/V/vl4re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re64.v.yaml b/arch/inst/V/vl4re64.v.yaml index 8db40b0c6..e00f0a875 100644 --- a/arch/inst/V/vl4re64.v.yaml +++ b/arch/inst/V/vl4re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re8.v.yaml b/arch/inst/V/vl4re8.v.yaml index 0361ac50a..78dc9fb41 100644 --- a/arch/inst/V/vl4re8.v.yaml +++ b/arch/inst/V/vl4re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re16.v.yaml b/arch/inst/V/vl8re16.v.yaml index 26214f47d..aefaacb6a 100644 --- a/arch/inst/V/vl8re16.v.yaml +++ b/arch/inst/V/vl8re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re32.v.yaml b/arch/inst/V/vl8re32.v.yaml index b55e4987f..f3add1efe 100644 --- a/arch/inst/V/vl8re32.v.yaml +++ b/arch/inst/V/vl8re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re64.v.yaml b/arch/inst/V/vl8re64.v.yaml index 1d992927d..283754478 100644 --- a/arch/inst/V/vl8re64.v.yaml +++ b/arch/inst/V/vl8re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re8.v.yaml b/arch/inst/V/vl8re8.v.yaml index e871bb99d..fce3b23fb 100644 --- a/arch/inst/V/vl8re8.v.yaml +++ b/arch/inst/V/vl8re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vle16.v.yaml b/arch/inst/V/vle16.v.yaml index b936f52ac..40884f375 100644 --- a/arch/inst/V/vle16.v.yaml +++ b/arch/inst/V/vle16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle16ff.v.yaml b/arch/inst/V/vle16ff.v.yaml index 50b881227..ec6f9aa68 100644 --- a/arch/inst/V/vle16ff.v.yaml +++ b/arch/inst/V/vle16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle32.v.yaml b/arch/inst/V/vle32.v.yaml index 492542605..15e973e69 100644 --- a/arch/inst/V/vle32.v.yaml +++ b/arch/inst/V/vle32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle32ff.v.yaml b/arch/inst/V/vle32ff.v.yaml index 4de0bad43..120324919 100644 --- a/arch/inst/V/vle32ff.v.yaml +++ b/arch/inst/V/vle32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle64.v.yaml b/arch/inst/V/vle64.v.yaml index 75a9f9bb0..aff28632f 100644 --- a/arch/inst/V/vle64.v.yaml +++ b/arch/inst/V/vle64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle64ff.v.yaml b/arch/inst/V/vle64ff.v.yaml index d9efeff02..421d1bda8 100644 --- a/arch/inst/V/vle64ff.v.yaml +++ b/arch/inst/V/vle64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle8.v.yaml b/arch/inst/V/vle8.v.yaml index a36a00ac1..68493ddfd 100644 --- a/arch/inst/V/vle8.v.yaml +++ b/arch/inst/V/vle8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle8ff.v.yaml b/arch/inst/V/vle8ff.v.yaml index e53ade80d..19bfd6824 100644 --- a/arch/inst/V/vle8ff.v.yaml +++ b/arch/inst/V/vle8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlm.v.yaml b/arch/inst/V/vlm.v.yaml index e7b17a708..bbcb34dff 100644 --- a/arch/inst/V/vlm.v.yaml +++ b/arch/inst/V/vlm.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vlm.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101011-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW = 8; diff --git a/arch/inst/V/vloxei16.v.yaml b/arch/inst/V/vloxei16.v.yaml index 333150bfc..fbe93e535 100644 --- a/arch/inst/V/vloxei16.v.yaml +++ b/arch/inst/V/vloxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei32.v.yaml b/arch/inst/V/vloxei32.v.yaml index 42334c5ef..0bb146ad4 100644 --- a/arch/inst/V/vloxei32.v.yaml +++ b/arch/inst/V/vloxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei64.v.yaml b/arch/inst/V/vloxei64.v.yaml index cc45f490e..0befceaff 100644 --- a/arch/inst/V/vloxei64.v.yaml +++ b/arch/inst/V/vloxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei8.v.yaml b/arch/inst/V/vloxei8.v.yaml index 3db6d4ebb..5a3ff0d66 100644 --- a/arch/inst/V/vloxei8.v.yaml +++ b/arch/inst/V/vloxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxseg2ei16.v.yaml b/arch/inst/V/vloxseg2ei16.v.yaml index 8c0275846..8f50632ea 100644 --- a/arch/inst/V/vloxseg2ei16.v.yaml +++ b/arch/inst/V/vloxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei32.v.yaml b/arch/inst/V/vloxseg2ei32.v.yaml index 8cf8eed09..88ffd0171 100644 --- a/arch/inst/V/vloxseg2ei32.v.yaml +++ b/arch/inst/V/vloxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei64.v.yaml b/arch/inst/V/vloxseg2ei64.v.yaml index b441647b1..fdf116edb 100644 --- a/arch/inst/V/vloxseg2ei64.v.yaml +++ b/arch/inst/V/vloxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei8.v.yaml b/arch/inst/V/vloxseg2ei8.v.yaml index 507fe4f0a..19fe4e96d 100644 --- a/arch/inst/V/vloxseg2ei8.v.yaml +++ b/arch/inst/V/vloxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei16.v.yaml b/arch/inst/V/vloxseg3ei16.v.yaml index 674b1aa84..f1ae7c255 100644 --- a/arch/inst/V/vloxseg3ei16.v.yaml +++ b/arch/inst/V/vloxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei32.v.yaml b/arch/inst/V/vloxseg3ei32.v.yaml index a2a61f851..628db505c 100644 --- a/arch/inst/V/vloxseg3ei32.v.yaml +++ b/arch/inst/V/vloxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei64.v.yaml b/arch/inst/V/vloxseg3ei64.v.yaml index 61cc36c82..1d1237a17 100644 --- a/arch/inst/V/vloxseg3ei64.v.yaml +++ b/arch/inst/V/vloxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei8.v.yaml b/arch/inst/V/vloxseg3ei8.v.yaml index cd4398986..d89edd83c 100644 --- a/arch/inst/V/vloxseg3ei8.v.yaml +++ b/arch/inst/V/vloxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei16.v.yaml b/arch/inst/V/vloxseg4ei16.v.yaml index a62650087..26983baed 100644 --- a/arch/inst/V/vloxseg4ei16.v.yaml +++ b/arch/inst/V/vloxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei32.v.yaml b/arch/inst/V/vloxseg4ei32.v.yaml index d97c7fb95..796d50b06 100644 --- a/arch/inst/V/vloxseg4ei32.v.yaml +++ b/arch/inst/V/vloxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei64.v.yaml b/arch/inst/V/vloxseg4ei64.v.yaml index fcfb19b82..95b41eca7 100644 --- a/arch/inst/V/vloxseg4ei64.v.yaml +++ b/arch/inst/V/vloxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei8.v.yaml b/arch/inst/V/vloxseg4ei8.v.yaml index d5c0d5054..24dfe586e 100644 --- a/arch/inst/V/vloxseg4ei8.v.yaml +++ b/arch/inst/V/vloxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei16.v.yaml b/arch/inst/V/vloxseg5ei16.v.yaml index 3512fb892..593634d18 100644 --- a/arch/inst/V/vloxseg5ei16.v.yaml +++ b/arch/inst/V/vloxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei32.v.yaml b/arch/inst/V/vloxseg5ei32.v.yaml index 3068b99f0..9aae903bc 100644 --- a/arch/inst/V/vloxseg5ei32.v.yaml +++ b/arch/inst/V/vloxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei64.v.yaml b/arch/inst/V/vloxseg5ei64.v.yaml index 4a1e73e51..ec8a28854 100644 --- a/arch/inst/V/vloxseg5ei64.v.yaml +++ b/arch/inst/V/vloxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei8.v.yaml b/arch/inst/V/vloxseg5ei8.v.yaml index df2afc27a..7234de35c 100644 --- a/arch/inst/V/vloxseg5ei8.v.yaml +++ b/arch/inst/V/vloxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei16.v.yaml b/arch/inst/V/vloxseg6ei16.v.yaml index f7b0fbdcc..d44349ade 100644 --- a/arch/inst/V/vloxseg6ei16.v.yaml +++ b/arch/inst/V/vloxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei32.v.yaml b/arch/inst/V/vloxseg6ei32.v.yaml index a42e7f335..ae574b966 100644 --- a/arch/inst/V/vloxseg6ei32.v.yaml +++ b/arch/inst/V/vloxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei64.v.yaml b/arch/inst/V/vloxseg6ei64.v.yaml index 24c9a89a1..e9f8c1afb 100644 --- a/arch/inst/V/vloxseg6ei64.v.yaml +++ b/arch/inst/V/vloxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei8.v.yaml b/arch/inst/V/vloxseg6ei8.v.yaml index af5bc5faa..8aa0692e5 100644 --- a/arch/inst/V/vloxseg6ei8.v.yaml +++ b/arch/inst/V/vloxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei16.v.yaml b/arch/inst/V/vloxseg7ei16.v.yaml index 9f113daec..a2cf87d8e 100644 --- a/arch/inst/V/vloxseg7ei16.v.yaml +++ b/arch/inst/V/vloxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei32.v.yaml b/arch/inst/V/vloxseg7ei32.v.yaml index dc92014b1..cdcd71aca 100644 --- a/arch/inst/V/vloxseg7ei32.v.yaml +++ b/arch/inst/V/vloxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei64.v.yaml b/arch/inst/V/vloxseg7ei64.v.yaml index 0efc0ce4e..0c65b7526 100644 --- a/arch/inst/V/vloxseg7ei64.v.yaml +++ b/arch/inst/V/vloxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei8.v.yaml b/arch/inst/V/vloxseg7ei8.v.yaml index a87175475..7fde4e306 100644 --- a/arch/inst/V/vloxseg7ei8.v.yaml +++ b/arch/inst/V/vloxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei16.v.yaml b/arch/inst/V/vloxseg8ei16.v.yaml index 820eb7d13..e2fbc18c9 100644 --- a/arch/inst/V/vloxseg8ei16.v.yaml +++ b/arch/inst/V/vloxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei32.v.yaml b/arch/inst/V/vloxseg8ei32.v.yaml index 9d733a3e2..d8ecb7ed4 100644 --- a/arch/inst/V/vloxseg8ei32.v.yaml +++ b/arch/inst/V/vloxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei64.v.yaml b/arch/inst/V/vloxseg8ei64.v.yaml index ff37314bf..94dd8167d 100644 --- a/arch/inst/V/vloxseg8ei64.v.yaml +++ b/arch/inst/V/vloxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei8.v.yaml b/arch/inst/V/vloxseg8ei8.v.yaml index 689a55354..3ceb6da14 100644 --- a/arch/inst/V/vloxseg8ei8.v.yaml +++ b/arch/inst/V/vloxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlse16.v.yaml b/arch/inst/V/vlse16.v.yaml index f82b34253..3741a01bd 100644 --- a/arch/inst/V/vlse16.v.yaml +++ b/arch/inst/V/vlse16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse32.v.yaml b/arch/inst/V/vlse32.v.yaml index 6ba2a8abe..8fee226d4 100644 --- a/arch/inst/V/vlse32.v.yaml +++ b/arch/inst/V/vlse32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse64.v.yaml b/arch/inst/V/vlse64.v.yaml index 76e1be064..bfb8bf3b4 100644 --- a/arch/inst/V/vlse64.v.yaml +++ b/arch/inst/V/vlse64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse8.v.yaml b/arch/inst/V/vlse8.v.yaml index ad57806cf..14de61233 100644 --- a/arch/inst/V/vlse8.v.yaml +++ b/arch/inst/V/vlse8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlseg2e16.v.yaml b/arch/inst/V/vlseg2e16.v.yaml index fb571d744..5cb311625 100644 --- a/arch/inst/V/vlseg2e16.v.yaml +++ b/arch/inst/V/vlseg2e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e16ff.v.yaml b/arch/inst/V/vlseg2e16ff.v.yaml index 0bcfe9e14..fffc3cbeb 100644 --- a/arch/inst/V/vlseg2e16ff.v.yaml +++ b/arch/inst/V/vlseg2e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e32.v.yaml b/arch/inst/V/vlseg2e32.v.yaml index d81a1047e..3f8a2133c 100644 --- a/arch/inst/V/vlseg2e32.v.yaml +++ b/arch/inst/V/vlseg2e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e32ff.v.yaml b/arch/inst/V/vlseg2e32ff.v.yaml index d1a6348b5..614aa1d37 100644 --- a/arch/inst/V/vlseg2e32ff.v.yaml +++ b/arch/inst/V/vlseg2e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e64.v.yaml b/arch/inst/V/vlseg2e64.v.yaml index 2c93a9442..9abcc5b7a 100644 --- a/arch/inst/V/vlseg2e64.v.yaml +++ b/arch/inst/V/vlseg2e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e64ff.v.yaml b/arch/inst/V/vlseg2e64ff.v.yaml index ca5ad1b9d..01cee8e7a 100644 --- a/arch/inst/V/vlseg2e64ff.v.yaml +++ b/arch/inst/V/vlseg2e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e8.v.yaml b/arch/inst/V/vlseg2e8.v.yaml index 9d80b185b..ee7d0ee60 100644 --- a/arch/inst/V/vlseg2e8.v.yaml +++ b/arch/inst/V/vlseg2e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e8ff.v.yaml b/arch/inst/V/vlseg2e8ff.v.yaml index 427db8eae..954bbc8db 100644 --- a/arch/inst/V/vlseg2e8ff.v.yaml +++ b/arch/inst/V/vlseg2e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e16.v.yaml b/arch/inst/V/vlseg3e16.v.yaml index f5d7e5545..898e2e94e 100644 --- a/arch/inst/V/vlseg3e16.v.yaml +++ b/arch/inst/V/vlseg3e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e16ff.v.yaml b/arch/inst/V/vlseg3e16ff.v.yaml index 76d8d97c4..b1a040ef0 100644 --- a/arch/inst/V/vlseg3e16ff.v.yaml +++ b/arch/inst/V/vlseg3e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e32.v.yaml b/arch/inst/V/vlseg3e32.v.yaml index d982464fe..16c93f5be 100644 --- a/arch/inst/V/vlseg3e32.v.yaml +++ b/arch/inst/V/vlseg3e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e32ff.v.yaml b/arch/inst/V/vlseg3e32ff.v.yaml index 1634338f1..419d3d028 100644 --- a/arch/inst/V/vlseg3e32ff.v.yaml +++ b/arch/inst/V/vlseg3e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e64.v.yaml b/arch/inst/V/vlseg3e64.v.yaml index 4de2fb503..9e2990a10 100644 --- a/arch/inst/V/vlseg3e64.v.yaml +++ b/arch/inst/V/vlseg3e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e64ff.v.yaml b/arch/inst/V/vlseg3e64ff.v.yaml index 0f73b786a..e6c162a72 100644 --- a/arch/inst/V/vlseg3e64ff.v.yaml +++ b/arch/inst/V/vlseg3e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e8.v.yaml b/arch/inst/V/vlseg3e8.v.yaml index f858ec9c7..d80c4c04e 100644 --- a/arch/inst/V/vlseg3e8.v.yaml +++ b/arch/inst/V/vlseg3e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e8ff.v.yaml b/arch/inst/V/vlseg3e8ff.v.yaml index aeed7424b..ca25deb26 100644 --- a/arch/inst/V/vlseg3e8ff.v.yaml +++ b/arch/inst/V/vlseg3e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e16.v.yaml b/arch/inst/V/vlseg4e16.v.yaml index e017e0983..5434d4672 100644 --- a/arch/inst/V/vlseg4e16.v.yaml +++ b/arch/inst/V/vlseg4e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e16ff.v.yaml b/arch/inst/V/vlseg4e16ff.v.yaml index 3144cc777..7b63f6c81 100644 --- a/arch/inst/V/vlseg4e16ff.v.yaml +++ b/arch/inst/V/vlseg4e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e32.v.yaml b/arch/inst/V/vlseg4e32.v.yaml index eaf5e45e9..8a4c98f82 100644 --- a/arch/inst/V/vlseg4e32.v.yaml +++ b/arch/inst/V/vlseg4e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e32ff.v.yaml b/arch/inst/V/vlseg4e32ff.v.yaml index fc92eeb66..edce5384f 100644 --- a/arch/inst/V/vlseg4e32ff.v.yaml +++ b/arch/inst/V/vlseg4e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e64.v.yaml b/arch/inst/V/vlseg4e64.v.yaml index e7630b5e6..95d861e70 100644 --- a/arch/inst/V/vlseg4e64.v.yaml +++ b/arch/inst/V/vlseg4e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e64ff.v.yaml b/arch/inst/V/vlseg4e64ff.v.yaml index b64e45fa2..574e0b934 100644 --- a/arch/inst/V/vlseg4e64ff.v.yaml +++ b/arch/inst/V/vlseg4e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e8.v.yaml b/arch/inst/V/vlseg4e8.v.yaml index 471bcc07d..72e625c5f 100644 --- a/arch/inst/V/vlseg4e8.v.yaml +++ b/arch/inst/V/vlseg4e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e8ff.v.yaml b/arch/inst/V/vlseg4e8ff.v.yaml index 67165fa3d..bb6104fde 100644 --- a/arch/inst/V/vlseg4e8ff.v.yaml +++ b/arch/inst/V/vlseg4e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e16.v.yaml b/arch/inst/V/vlseg5e16.v.yaml index 9ba626b4a..ac5fad6cc 100644 --- a/arch/inst/V/vlseg5e16.v.yaml +++ b/arch/inst/V/vlseg5e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e16ff.v.yaml b/arch/inst/V/vlseg5e16ff.v.yaml index 2f1eaa609..aea4907b1 100644 --- a/arch/inst/V/vlseg5e16ff.v.yaml +++ b/arch/inst/V/vlseg5e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e32.v.yaml b/arch/inst/V/vlseg5e32.v.yaml index eb45144de..df90200f6 100644 --- a/arch/inst/V/vlseg5e32.v.yaml +++ b/arch/inst/V/vlseg5e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e32ff.v.yaml b/arch/inst/V/vlseg5e32ff.v.yaml index e0cc52c87..8923077d8 100644 --- a/arch/inst/V/vlseg5e32ff.v.yaml +++ b/arch/inst/V/vlseg5e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e64.v.yaml b/arch/inst/V/vlseg5e64.v.yaml index e989cc4a4..b9295db7d 100644 --- a/arch/inst/V/vlseg5e64.v.yaml +++ b/arch/inst/V/vlseg5e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e64ff.v.yaml b/arch/inst/V/vlseg5e64ff.v.yaml index 06440b792..634ab86b7 100644 --- a/arch/inst/V/vlseg5e64ff.v.yaml +++ b/arch/inst/V/vlseg5e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e8.v.yaml b/arch/inst/V/vlseg5e8.v.yaml index e853590c0..60bb7affa 100644 --- a/arch/inst/V/vlseg5e8.v.yaml +++ b/arch/inst/V/vlseg5e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e8ff.v.yaml b/arch/inst/V/vlseg5e8ff.v.yaml index e77ecaefe..42f28df02 100644 --- a/arch/inst/V/vlseg5e8ff.v.yaml +++ b/arch/inst/V/vlseg5e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e16.v.yaml b/arch/inst/V/vlseg6e16.v.yaml index 8f546c7db..5aa54afe3 100644 --- a/arch/inst/V/vlseg6e16.v.yaml +++ b/arch/inst/V/vlseg6e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e16ff.v.yaml b/arch/inst/V/vlseg6e16ff.v.yaml index 352ed9489..60eb36b58 100644 --- a/arch/inst/V/vlseg6e16ff.v.yaml +++ b/arch/inst/V/vlseg6e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e32.v.yaml b/arch/inst/V/vlseg6e32.v.yaml index 3ec853fd6..6478c2ea2 100644 --- a/arch/inst/V/vlseg6e32.v.yaml +++ b/arch/inst/V/vlseg6e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e32ff.v.yaml b/arch/inst/V/vlseg6e32ff.v.yaml index e6ee66553..55f0239ec 100644 --- a/arch/inst/V/vlseg6e32ff.v.yaml +++ b/arch/inst/V/vlseg6e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e64.v.yaml b/arch/inst/V/vlseg6e64.v.yaml index d281c07ea..c630d640b 100644 --- a/arch/inst/V/vlseg6e64.v.yaml +++ b/arch/inst/V/vlseg6e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e64ff.v.yaml b/arch/inst/V/vlseg6e64ff.v.yaml index 64bccae0b..7f2d2a1b1 100644 --- a/arch/inst/V/vlseg6e64ff.v.yaml +++ b/arch/inst/V/vlseg6e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e8.v.yaml b/arch/inst/V/vlseg6e8.v.yaml index 6205f7654..fc071cf6d 100644 --- a/arch/inst/V/vlseg6e8.v.yaml +++ b/arch/inst/V/vlseg6e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e8ff.v.yaml b/arch/inst/V/vlseg6e8ff.v.yaml index 96772b71f..0d1003c67 100644 --- a/arch/inst/V/vlseg6e8ff.v.yaml +++ b/arch/inst/V/vlseg6e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e16.v.yaml b/arch/inst/V/vlseg7e16.v.yaml index 80608625b..059b5cb40 100644 --- a/arch/inst/V/vlseg7e16.v.yaml +++ b/arch/inst/V/vlseg7e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e16ff.v.yaml b/arch/inst/V/vlseg7e16ff.v.yaml index ad5a0c8e7..8a494b3a8 100644 --- a/arch/inst/V/vlseg7e16ff.v.yaml +++ b/arch/inst/V/vlseg7e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e32.v.yaml b/arch/inst/V/vlseg7e32.v.yaml index c03e22bd0..46144daa2 100644 --- a/arch/inst/V/vlseg7e32.v.yaml +++ b/arch/inst/V/vlseg7e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e32ff.v.yaml b/arch/inst/V/vlseg7e32ff.v.yaml index 502219914..f3b5926ba 100644 --- a/arch/inst/V/vlseg7e32ff.v.yaml +++ b/arch/inst/V/vlseg7e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e64.v.yaml b/arch/inst/V/vlseg7e64.v.yaml index 9198968c5..2bc956014 100644 --- a/arch/inst/V/vlseg7e64.v.yaml +++ b/arch/inst/V/vlseg7e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e64ff.v.yaml b/arch/inst/V/vlseg7e64ff.v.yaml index f19ae2b3d..55d191980 100644 --- a/arch/inst/V/vlseg7e64ff.v.yaml +++ b/arch/inst/V/vlseg7e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e8.v.yaml b/arch/inst/V/vlseg7e8.v.yaml index 8d5b00522..b9f55a454 100644 --- a/arch/inst/V/vlseg7e8.v.yaml +++ b/arch/inst/V/vlseg7e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e8ff.v.yaml b/arch/inst/V/vlseg7e8ff.v.yaml index 6b70df5dd..f27a57aec 100644 --- a/arch/inst/V/vlseg7e8ff.v.yaml +++ b/arch/inst/V/vlseg7e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e16.v.yaml b/arch/inst/V/vlseg8e16.v.yaml index 123b19b57..abb6f90ae 100644 --- a/arch/inst/V/vlseg8e16.v.yaml +++ b/arch/inst/V/vlseg8e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e16ff.v.yaml b/arch/inst/V/vlseg8e16ff.v.yaml index 638b68a82..0fd2a96a7 100644 --- a/arch/inst/V/vlseg8e16ff.v.yaml +++ b/arch/inst/V/vlseg8e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e32.v.yaml b/arch/inst/V/vlseg8e32.v.yaml index 39b89cdad..a0abea2d5 100644 --- a/arch/inst/V/vlseg8e32.v.yaml +++ b/arch/inst/V/vlseg8e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e32ff.v.yaml b/arch/inst/V/vlseg8e32ff.v.yaml index a2ab52d77..2d4f2aa7f 100644 --- a/arch/inst/V/vlseg8e32ff.v.yaml +++ b/arch/inst/V/vlseg8e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e64.v.yaml b/arch/inst/V/vlseg8e64.v.yaml index f7952833b..cd01f7e35 100644 --- a/arch/inst/V/vlseg8e64.v.yaml +++ b/arch/inst/V/vlseg8e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e64ff.v.yaml b/arch/inst/V/vlseg8e64ff.v.yaml index 28c0e9a73..73fe0b9d6 100644 --- a/arch/inst/V/vlseg8e64ff.v.yaml +++ b/arch/inst/V/vlseg8e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e8.v.yaml b/arch/inst/V/vlseg8e8.v.yaml index 7b1c864ae..1e73f3734 100644 --- a/arch/inst/V/vlseg8e8.v.yaml +++ b/arch/inst/V/vlseg8e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e8ff.v.yaml b/arch/inst/V/vlseg8e8ff.v.yaml index 503786f11..c3c5feebd 100644 --- a/arch/inst/V/vlseg8e8ff.v.yaml +++ b/arch/inst/V/vlseg8e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e16.v.yaml b/arch/inst/V/vlsseg2e16.v.yaml index a8700b96d..b7d6b5a03 100644 --- a/arch/inst/V/vlsseg2e16.v.yaml +++ b/arch/inst/V/vlsseg2e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e32.v.yaml b/arch/inst/V/vlsseg2e32.v.yaml index 06df364b8..80b1db91f 100644 --- a/arch/inst/V/vlsseg2e32.v.yaml +++ b/arch/inst/V/vlsseg2e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e64.v.yaml b/arch/inst/V/vlsseg2e64.v.yaml index ad42e35e3..e035d8b3d 100644 --- a/arch/inst/V/vlsseg2e64.v.yaml +++ b/arch/inst/V/vlsseg2e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e8.v.yaml b/arch/inst/V/vlsseg2e8.v.yaml index f5d11dfac..5905d81de 100644 --- a/arch/inst/V/vlsseg2e8.v.yaml +++ b/arch/inst/V/vlsseg2e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e16.v.yaml b/arch/inst/V/vlsseg3e16.v.yaml index e56df9143..a2d5fbef9 100644 --- a/arch/inst/V/vlsseg3e16.v.yaml +++ b/arch/inst/V/vlsseg3e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e32.v.yaml b/arch/inst/V/vlsseg3e32.v.yaml index 836a5cccc..5fca1695d 100644 --- a/arch/inst/V/vlsseg3e32.v.yaml +++ b/arch/inst/V/vlsseg3e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e64.v.yaml b/arch/inst/V/vlsseg3e64.v.yaml index 0fbc2ece1..00ca5c5da 100644 --- a/arch/inst/V/vlsseg3e64.v.yaml +++ b/arch/inst/V/vlsseg3e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e8.v.yaml b/arch/inst/V/vlsseg3e8.v.yaml index d9f270297..ede6a526b 100644 --- a/arch/inst/V/vlsseg3e8.v.yaml +++ b/arch/inst/V/vlsseg3e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e16.v.yaml b/arch/inst/V/vlsseg4e16.v.yaml index 2946801a2..65a461e23 100644 --- a/arch/inst/V/vlsseg4e16.v.yaml +++ b/arch/inst/V/vlsseg4e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e32.v.yaml b/arch/inst/V/vlsseg4e32.v.yaml index f9e9adb8e..44d11d662 100644 --- a/arch/inst/V/vlsseg4e32.v.yaml +++ b/arch/inst/V/vlsseg4e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e64.v.yaml b/arch/inst/V/vlsseg4e64.v.yaml index 7091310b9..bc10dc6b2 100644 --- a/arch/inst/V/vlsseg4e64.v.yaml +++ b/arch/inst/V/vlsseg4e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e8.v.yaml b/arch/inst/V/vlsseg4e8.v.yaml index e7755782f..e76dfb062 100644 --- a/arch/inst/V/vlsseg4e8.v.yaml +++ b/arch/inst/V/vlsseg4e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e16.v.yaml b/arch/inst/V/vlsseg5e16.v.yaml index d96600999..3ba3917d9 100644 --- a/arch/inst/V/vlsseg5e16.v.yaml +++ b/arch/inst/V/vlsseg5e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e32.v.yaml b/arch/inst/V/vlsseg5e32.v.yaml index 36dcfda26..a0a1700ed 100644 --- a/arch/inst/V/vlsseg5e32.v.yaml +++ b/arch/inst/V/vlsseg5e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e64.v.yaml b/arch/inst/V/vlsseg5e64.v.yaml index 43ef731d9..85a4db701 100644 --- a/arch/inst/V/vlsseg5e64.v.yaml +++ b/arch/inst/V/vlsseg5e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e8.v.yaml b/arch/inst/V/vlsseg5e8.v.yaml index 512237dfc..958b4ca06 100644 --- a/arch/inst/V/vlsseg5e8.v.yaml +++ b/arch/inst/V/vlsseg5e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e16.v.yaml b/arch/inst/V/vlsseg6e16.v.yaml index fda481b60..657f53387 100644 --- a/arch/inst/V/vlsseg6e16.v.yaml +++ b/arch/inst/V/vlsseg6e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e32.v.yaml b/arch/inst/V/vlsseg6e32.v.yaml index 3e4927eb4..c1e5f2ce1 100644 --- a/arch/inst/V/vlsseg6e32.v.yaml +++ b/arch/inst/V/vlsseg6e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e64.v.yaml b/arch/inst/V/vlsseg6e64.v.yaml index 379f481bb..7fc49445d 100644 --- a/arch/inst/V/vlsseg6e64.v.yaml +++ b/arch/inst/V/vlsseg6e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e8.v.yaml b/arch/inst/V/vlsseg6e8.v.yaml index 16080240a..b017bc5bc 100644 --- a/arch/inst/V/vlsseg6e8.v.yaml +++ b/arch/inst/V/vlsseg6e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e16.v.yaml b/arch/inst/V/vlsseg7e16.v.yaml index 464b1013d..77d7921de 100644 --- a/arch/inst/V/vlsseg7e16.v.yaml +++ b/arch/inst/V/vlsseg7e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e32.v.yaml b/arch/inst/V/vlsseg7e32.v.yaml index 990fcab16..a186fb690 100644 --- a/arch/inst/V/vlsseg7e32.v.yaml +++ b/arch/inst/V/vlsseg7e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e64.v.yaml b/arch/inst/V/vlsseg7e64.v.yaml index 7dc4459c3..3fe69afff 100644 --- a/arch/inst/V/vlsseg7e64.v.yaml +++ b/arch/inst/V/vlsseg7e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e8.v.yaml b/arch/inst/V/vlsseg7e8.v.yaml index de905eaf9..f78d539f4 100644 --- a/arch/inst/V/vlsseg7e8.v.yaml +++ b/arch/inst/V/vlsseg7e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e16.v.yaml b/arch/inst/V/vlsseg8e16.v.yaml index d563b2387..b2caab9ec 100644 --- a/arch/inst/V/vlsseg8e16.v.yaml +++ b/arch/inst/V/vlsseg8e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e32.v.yaml b/arch/inst/V/vlsseg8e32.v.yaml index a37c82d99..5effd73f6 100644 --- a/arch/inst/V/vlsseg8e32.v.yaml +++ b/arch/inst/V/vlsseg8e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e64.v.yaml b/arch/inst/V/vlsseg8e64.v.yaml index c9a6e417c..6d0fc68ad 100644 --- a/arch/inst/V/vlsseg8e64.v.yaml +++ b/arch/inst/V/vlsseg8e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e8.v.yaml b/arch/inst/V/vlsseg8e8.v.yaml index 71d8ed23d..84e902899 100644 --- a/arch/inst/V/vlsseg8e8.v.yaml +++ b/arch/inst/V/vlsseg8e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxei16.v.yaml b/arch/inst/V/vluxei16.v.yaml index 69010d3ea..268991b9e 100644 --- a/arch/inst/V/vluxei16.v.yaml +++ b/arch/inst/V/vluxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei32.v.yaml b/arch/inst/V/vluxei32.v.yaml index eee624fab..49e5eb45b 100644 --- a/arch/inst/V/vluxei32.v.yaml +++ b/arch/inst/V/vluxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei64.v.yaml b/arch/inst/V/vluxei64.v.yaml index 3429c2c32..4f9b114fa 100644 --- a/arch/inst/V/vluxei64.v.yaml +++ b/arch/inst/V/vluxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei8.v.yaml b/arch/inst/V/vluxei8.v.yaml index 64cffe056..fd3c8fd00 100644 --- a/arch/inst/V/vluxei8.v.yaml +++ b/arch/inst/V/vluxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxseg2ei16.v.yaml b/arch/inst/V/vluxseg2ei16.v.yaml index fa80ccdc7..e95d49b1f 100644 --- a/arch/inst/V/vluxseg2ei16.v.yaml +++ b/arch/inst/V/vluxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei32.v.yaml b/arch/inst/V/vluxseg2ei32.v.yaml index 9d5656f6e..31b98fdf5 100644 --- a/arch/inst/V/vluxseg2ei32.v.yaml +++ b/arch/inst/V/vluxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei64.v.yaml b/arch/inst/V/vluxseg2ei64.v.yaml index 38996c623..deef06eee 100644 --- a/arch/inst/V/vluxseg2ei64.v.yaml +++ b/arch/inst/V/vluxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei8.v.yaml b/arch/inst/V/vluxseg2ei8.v.yaml index 6c714e570..f71e23efd 100644 --- a/arch/inst/V/vluxseg2ei8.v.yaml +++ b/arch/inst/V/vluxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei16.v.yaml b/arch/inst/V/vluxseg3ei16.v.yaml index 5d4ba029c..d5c985f7b 100644 --- a/arch/inst/V/vluxseg3ei16.v.yaml +++ b/arch/inst/V/vluxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei32.v.yaml b/arch/inst/V/vluxseg3ei32.v.yaml index 6a4ecd498..3ba831308 100644 --- a/arch/inst/V/vluxseg3ei32.v.yaml +++ b/arch/inst/V/vluxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei64.v.yaml b/arch/inst/V/vluxseg3ei64.v.yaml index dad4d516e..c557efe27 100644 --- a/arch/inst/V/vluxseg3ei64.v.yaml +++ b/arch/inst/V/vluxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei8.v.yaml b/arch/inst/V/vluxseg3ei8.v.yaml index e162ada5c..05c53af76 100644 --- a/arch/inst/V/vluxseg3ei8.v.yaml +++ b/arch/inst/V/vluxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei16.v.yaml b/arch/inst/V/vluxseg4ei16.v.yaml index e6e85799f..36541bf07 100644 --- a/arch/inst/V/vluxseg4ei16.v.yaml +++ b/arch/inst/V/vluxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei32.v.yaml b/arch/inst/V/vluxseg4ei32.v.yaml index 16bfdda26..83a50c046 100644 --- a/arch/inst/V/vluxseg4ei32.v.yaml +++ b/arch/inst/V/vluxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei64.v.yaml b/arch/inst/V/vluxseg4ei64.v.yaml index 65de58e16..f2c389394 100644 --- a/arch/inst/V/vluxseg4ei64.v.yaml +++ b/arch/inst/V/vluxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei8.v.yaml b/arch/inst/V/vluxseg4ei8.v.yaml index d0ab23954..8d23a879d 100644 --- a/arch/inst/V/vluxseg4ei8.v.yaml +++ b/arch/inst/V/vluxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei16.v.yaml b/arch/inst/V/vluxseg5ei16.v.yaml index cb8c43f71..d8aa2cf59 100644 --- a/arch/inst/V/vluxseg5ei16.v.yaml +++ b/arch/inst/V/vluxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei32.v.yaml b/arch/inst/V/vluxseg5ei32.v.yaml index 3bf89d6af..c43a04e86 100644 --- a/arch/inst/V/vluxseg5ei32.v.yaml +++ b/arch/inst/V/vluxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei64.v.yaml b/arch/inst/V/vluxseg5ei64.v.yaml index ddb29d4bb..0e827a325 100644 --- a/arch/inst/V/vluxseg5ei64.v.yaml +++ b/arch/inst/V/vluxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei8.v.yaml b/arch/inst/V/vluxseg5ei8.v.yaml index 01870a1c5..40019e9b9 100644 --- a/arch/inst/V/vluxseg5ei8.v.yaml +++ b/arch/inst/V/vluxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei16.v.yaml b/arch/inst/V/vluxseg6ei16.v.yaml index 3326c77ff..1db16ac36 100644 --- a/arch/inst/V/vluxseg6ei16.v.yaml +++ b/arch/inst/V/vluxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei32.v.yaml b/arch/inst/V/vluxseg6ei32.v.yaml index 596227162..e39b63452 100644 --- a/arch/inst/V/vluxseg6ei32.v.yaml +++ b/arch/inst/V/vluxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei64.v.yaml b/arch/inst/V/vluxseg6ei64.v.yaml index ef5b21469..1ec381f08 100644 --- a/arch/inst/V/vluxseg6ei64.v.yaml +++ b/arch/inst/V/vluxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei8.v.yaml b/arch/inst/V/vluxseg6ei8.v.yaml index 93db5170d..933ffe429 100644 --- a/arch/inst/V/vluxseg6ei8.v.yaml +++ b/arch/inst/V/vluxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei16.v.yaml b/arch/inst/V/vluxseg7ei16.v.yaml index 0d0d1223b..185db29df 100644 --- a/arch/inst/V/vluxseg7ei16.v.yaml +++ b/arch/inst/V/vluxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei32.v.yaml b/arch/inst/V/vluxseg7ei32.v.yaml index 09661bd0d..9f157aecc 100644 --- a/arch/inst/V/vluxseg7ei32.v.yaml +++ b/arch/inst/V/vluxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei64.v.yaml b/arch/inst/V/vluxseg7ei64.v.yaml index da5490090..a163420e5 100644 --- a/arch/inst/V/vluxseg7ei64.v.yaml +++ b/arch/inst/V/vluxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei8.v.yaml b/arch/inst/V/vluxseg7ei8.v.yaml index 9bf03adc4..e488f9d69 100644 --- a/arch/inst/V/vluxseg7ei8.v.yaml +++ b/arch/inst/V/vluxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei16.v.yaml b/arch/inst/V/vluxseg8ei16.v.yaml index b64e783f4..2b99804c8 100644 --- a/arch/inst/V/vluxseg8ei16.v.yaml +++ b/arch/inst/V/vluxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei32.v.yaml b/arch/inst/V/vluxseg8ei32.v.yaml index 5f53f3b23..729bcaa03 100644 --- a/arch/inst/V/vluxseg8ei32.v.yaml +++ b/arch/inst/V/vluxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei64.v.yaml b/arch/inst/V/vluxseg8ei64.v.yaml index 6a5eaffaa..500087bbe 100644 --- a/arch/inst/V/vluxseg8ei64.v.yaml +++ b/arch/inst/V/vluxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei8.v.yaml b/arch/inst/V/vluxseg8ei8.v.yaml index 0775f15d8..51c5c5e6a 100644 --- a/arch/inst/V/vluxseg8ei8.v.yaml +++ b/arch/inst/V/vluxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmacc.vv.yaml b/arch/inst/V/vmacc.vv.yaml index 2cfaba7c9..5672d0a62 100644 --- a/arch/inst/V/vmacc.vv.yaml +++ b/arch/inst/V/vmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmacc.vx.yaml b/arch/inst/V/vmacc.vx.yaml index eae603250..567e470f4 100644 --- a/arch/inst/V/vmacc.vx.yaml +++ b/arch/inst/V/vmacc.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmacc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vi.yaml b/arch/inst/V/vmadc.vi.yaml index 06f7081b9..2805add37 100644 --- a/arch/inst/V/vmadc.vi.yaml +++ b/arch/inst/V/vmadc.vi.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100011----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vim.yaml b/arch/inst/V/vmadc.vim.yaml index f7add6ff8..f28cca0d2 100644 --- a/arch/inst/V/vmadc.vim.yaml +++ b/arch/inst/V/vmadc.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100010----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vv.yaml b/arch/inst/V/vmadc.vv.yaml index 18f0baafd..6cbedeccd 100644 --- a/arch/inst/V/vmadc.vv.yaml +++ b/arch/inst/V/vmadc.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100011----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vvm.yaml b/arch/inst/V/vmadc.vvm.yaml index a367b3624..48715e476 100644 --- a/arch/inst/V/vmadc.vvm.yaml +++ b/arch/inst/V/vmadc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100010----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vx.yaml b/arch/inst/V/vmadc.vx.yaml index e216e96b5..639d677d5 100644 --- a/arch/inst/V/vmadc.vx.yaml +++ b/arch/inst/V/vmadc.vx.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100011----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vxm.yaml b/arch/inst/V/vmadc.vxm.yaml index 42be4e178..892977830 100644 --- a/arch/inst/V/vmadc.vxm.yaml +++ b/arch/inst/V/vmadc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100010----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadd.vv.yaml b/arch/inst/V/vmadd.vv.yaml index d126ca055..3e1b9742c 100644 --- a/arch/inst/V/vmadd.vv.yaml +++ b/arch/inst/V/vmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadd.vx.yaml b/arch/inst/V/vmadd.vx.yaml index 605641cd1..284c06910 100644 --- a/arch/inst/V/vmadd.vx.yaml +++ b/arch/inst/V/vmadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmand.mm.yaml b/arch/inst/V/vmand.mm.yaml index 71b3d684b..12c96c2cd 100644 --- a/arch/inst/V/vmand.mm.yaml +++ b/arch/inst/V/vmand.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmand.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110011----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmandn.mm.yaml b/arch/inst/V/vmandn.mm.yaml index 78e38995c..f20981b6e 100644 --- a/arch/inst/V/vmandn.mm.yaml +++ b/arch/inst/V/vmandn.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmandn.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110001----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmax.vv.yaml b/arch/inst/V/vmax.vv.yaml index c3047be50..d280f75e7 100644 --- a/arch/inst/V/vmax.vv.yaml +++ b/arch/inst/V/vmax.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmax.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmax.vx.yaml b/arch/inst/V/vmax.vx.yaml index 6766e0453..d46e15dc1 100644 --- a/arch/inst/V/vmax.vx.yaml +++ b/arch/inst/V/vmax.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmax.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmaxu.vv.yaml b/arch/inst/V/vmaxu.vv.yaml index 986712f51..cbda87776 100644 --- a/arch/inst/V/vmaxu.vv.yaml +++ b/arch/inst/V/vmaxu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmaxu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmaxu.vx.yaml b/arch/inst/V/vmaxu.vx.yaml index b5c164962..11ce724d4 100644 --- a/arch/inst/V/vmaxu.vx.yaml +++ b/arch/inst/V/vmaxu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmaxu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmerge.vim.yaml b/arch/inst/V/vmerge.vim.yaml index 80a4b3b5f..9cf80d229 100644 --- a/arch/inst/V/vmerge.vim.yaml +++ b/arch/inst/V/vmerge.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0101110----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmerge.vvm.yaml b/arch/inst/V/vmerge.vvm.yaml index ad5f77d97..b697a2f83 100644 --- a/arch/inst/V/vmerge.vvm.yaml +++ b/arch/inst/V/vmerge.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0101110----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmerge.vxm.yaml b/arch/inst/V/vmerge.vxm.yaml index 1dbddcaba..fab9487e1 100644 --- a/arch/inst/V/vmerge.vxm.yaml +++ b/arch/inst/V/vmerge.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0101110----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmfeq.vf.yaml b/arch/inst/V/vmfeq.vf.yaml index 3e9412057..2c9506897 100644 --- a/arch/inst/V/vmfeq.vf.yaml +++ b/arch/inst/V/vmfeq.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfeq.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfeq.vv.yaml b/arch/inst/V/vmfeq.vv.yaml index 2663d6d03..18585c143 100644 --- a/arch/inst/V/vmfeq.vv.yaml +++ b/arch/inst/V/vmfeq.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfeq.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfge.vf.yaml b/arch/inst/V/vmfge.vf.yaml index 2e7cf5ff3..02719fdf3 100644 --- a/arch/inst/V/vmfge.vf.yaml +++ b/arch/inst/V/vmfge.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfge.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfgt.vf.yaml b/arch/inst/V/vmfgt.vf.yaml index 13197e570..0a59ae4ff 100644 --- a/arch/inst/V/vmfgt.vf.yaml +++ b/arch/inst/V/vmfgt.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfgt.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfle.vf.yaml b/arch/inst/V/vmfle.vf.yaml index f85b9dbf5..c6cf50f93 100644 --- a/arch/inst/V/vmfle.vf.yaml +++ b/arch/inst/V/vmfle.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfle.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfle.vv.yaml b/arch/inst/V/vmfle.vv.yaml index 318034f10..13a7a16b0 100644 --- a/arch/inst/V/vmfle.vv.yaml +++ b/arch/inst/V/vmfle.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfle.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmflt.vf.yaml b/arch/inst/V/vmflt.vf.yaml index 77d68c838..805fce920 100644 --- a/arch/inst/V/vmflt.vf.yaml +++ b/arch/inst/V/vmflt.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmflt.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmflt.vv.yaml b/arch/inst/V/vmflt.vv.yaml index 676841f71..a5f85749c 100644 --- a/arch/inst/V/vmflt.vv.yaml +++ b/arch/inst/V/vmflt.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmflt.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfne.vf.yaml b/arch/inst/V/vmfne.vf.yaml index adf5cd410..069bb187c 100644 --- a/arch/inst/V/vmfne.vf.yaml +++ b/arch/inst/V/vmfne.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfne.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfne.vv.yaml b/arch/inst/V/vmfne.vv.yaml index a5078c955..7652613a9 100644 --- a/arch/inst/V/vmfne.vv.yaml +++ b/arch/inst/V/vmfne.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfne.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmin.vv.yaml b/arch/inst/V/vmin.vv.yaml index 4b5c9cad9..1921b1c2e 100644 --- a/arch/inst/V/vmin.vv.yaml +++ b/arch/inst/V/vmin.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmin.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmin.vx.yaml b/arch/inst/V/vmin.vx.yaml index 12be058ed..5c1688142 100644 --- a/arch/inst/V/vmin.vx.yaml +++ b/arch/inst/V/vmin.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmin.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vminu.vv.yaml b/arch/inst/V/vminu.vv.yaml index 897d4b120..5c8ad591c 100644 --- a/arch/inst/V/vminu.vv.yaml +++ b/arch/inst/V/vminu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vminu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vminu.vx.yaml b/arch/inst/V/vminu.vx.yaml index 890b56430..5ad49941a 100644 --- a/arch/inst/V/vminu.vx.yaml +++ b/arch/inst/V/vminu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vminu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmnand.mm.yaml b/arch/inst/V/vmnand.mm.yaml index e32a80db4..24ae63b6a 100644 --- a/arch/inst/V/vmnand.mm.yaml +++ b/arch/inst/V/vmnand.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmnand.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111011----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmnor.mm.yaml b/arch/inst/V/vmnor.mm.yaml index e0ccff3e3..e0aa1d8fd 100644 --- a/arch/inst/V/vmnor.mm.yaml +++ b/arch/inst/V/vmnor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmnor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111101----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmor.mm.yaml b/arch/inst/V/vmor.mm.yaml index 81e64a938..6f2c1d91a 100644 --- a/arch/inst/V/vmor.mm.yaml +++ b/arch/inst/V/vmor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110101----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmorn.mm.yaml b/arch/inst/V/vmorn.mm.yaml index 89e53e8fe..754592837 100644 --- a/arch/inst/V/vmorn.mm.yaml +++ b/arch/inst/V/vmorn.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmorn.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111001----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmsbc.vv.yaml b/arch/inst/V/vmsbc.vv.yaml index f7fa84ea2..f0002611b 100644 --- a/arch/inst/V/vmsbc.vv.yaml +++ b/arch/inst/V/vmsbc.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100111----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vvm.yaml b/arch/inst/V/vmsbc.vvm.yaml index c4837da15..53f82a250 100644 --- a/arch/inst/V/vmsbc.vvm.yaml +++ b/arch/inst/V/vmsbc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100110----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vx.yaml b/arch/inst/V/vmsbc.vx.yaml index 2caf127ca..86ac315ec 100644 --- a/arch/inst/V/vmsbc.vx.yaml +++ b/arch/inst/V/vmsbc.vx.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100111----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vxm.yaml b/arch/inst/V/vmsbc.vxm.yaml index f0865388b..71e018765 100644 --- a/arch/inst/V/vmsbc.vxm.yaml +++ b/arch/inst/V/vmsbc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100110----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbf.m.yaml b/arch/inst/V/vmsbf.m.yaml index fe85db16a..9d242a585 100644 --- a/arch/inst/V/vmsbf.m.yaml +++ b/arch/inst/V/vmsbf.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbf.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vi.yaml b/arch/inst/V/vmseq.vi.yaml index fc52fa6a6..ac5705655 100644 --- a/arch/inst/V/vmseq.vi.yaml +++ b/arch/inst/V/vmseq.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vv.yaml b/arch/inst/V/vmseq.vv.yaml index cfb1bb786..7e611a1a3 100644 --- a/arch/inst/V/vmseq.vv.yaml +++ b/arch/inst/V/vmseq.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vx.yaml b/arch/inst/V/vmseq.vx.yaml index 55003e0e7..eff36fb71 100644 --- a/arch/inst/V/vmseq.vx.yaml +++ b/arch/inst/V/vmseq.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgt.vi.yaml b/arch/inst/V/vmsgt.vi.yaml index 946b787fb..8536d5c10 100644 --- a/arch/inst/V/vmsgt.vi.yaml +++ b/arch/inst/V/vmsgt.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgt.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgt.vx.yaml b/arch/inst/V/vmsgt.vx.yaml index fd878324b..98e1427e2 100644 --- a/arch/inst/V/vmsgt.vx.yaml +++ b/arch/inst/V/vmsgt.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgt.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgtu.vi.yaml b/arch/inst/V/vmsgtu.vi.yaml index 9119f759c..52f999cd5 100644 --- a/arch/inst/V/vmsgtu.vi.yaml +++ b/arch/inst/V/vmsgtu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgtu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgtu.vx.yaml b/arch/inst/V/vmsgtu.vx.yaml index 5943925ef..44ebb47f6 100644 --- a/arch/inst/V/vmsgtu.vx.yaml +++ b/arch/inst/V/vmsgtu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgtu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsif.m.yaml b/arch/inst/V/vmsif.m.yaml index 008210658..1790f1ef3 100644 --- a/arch/inst/V/vmsif.m.yaml +++ b/arch/inst/V/vmsif.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsif.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00011010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vi.yaml b/arch/inst/V/vmsle.vi.yaml index a7d5d7367..1901822f6 100644 --- a/arch/inst/V/vmsle.vi.yaml +++ b/arch/inst/V/vmsle.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vv.yaml b/arch/inst/V/vmsle.vv.yaml index 6a41afaaa..7d0cbed76 100644 --- a/arch/inst/V/vmsle.vv.yaml +++ b/arch/inst/V/vmsle.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vx.yaml b/arch/inst/V/vmsle.vx.yaml index a8474a388..b6183dd83 100644 --- a/arch/inst/V/vmsle.vx.yaml +++ b/arch/inst/V/vmsle.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vi.yaml b/arch/inst/V/vmsleu.vi.yaml index 0adb60845..8e222c8ee 100644 --- a/arch/inst/V/vmsleu.vi.yaml +++ b/arch/inst/V/vmsleu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vv.yaml b/arch/inst/V/vmsleu.vv.yaml index 953e32a48..45635d603 100644 --- a/arch/inst/V/vmsleu.vv.yaml +++ b/arch/inst/V/vmsleu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vx.yaml b/arch/inst/V/vmsleu.vx.yaml index 7a1122585..04d5acc73 100644 --- a/arch/inst/V/vmsleu.vx.yaml +++ b/arch/inst/V/vmsleu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmslt.vv.yaml b/arch/inst/V/vmslt.vv.yaml index f275667bd..82749272f 100644 --- a/arch/inst/V/vmslt.vv.yaml +++ b/arch/inst/V/vmslt.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmslt.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmslt.vx.yaml b/arch/inst/V/vmslt.vx.yaml index b44cd616b..65b858618 100644 --- a/arch/inst/V/vmslt.vx.yaml +++ b/arch/inst/V/vmslt.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmslt.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsltu.vv.yaml b/arch/inst/V/vmsltu.vv.yaml index 7da2e1662..3b3cec1af 100644 --- a/arch/inst/V/vmsltu.vv.yaml +++ b/arch/inst/V/vmsltu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsltu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsltu.vx.yaml b/arch/inst/V/vmsltu.vx.yaml index 92d8ecbce..a22e63185 100644 --- a/arch/inst/V/vmsltu.vx.yaml +++ b/arch/inst/V/vmsltu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsltu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vi.yaml b/arch/inst/V/vmsne.vi.yaml index 8f9fe39bb..f817fb451 100644 --- a/arch/inst/V/vmsne.vi.yaml +++ b/arch/inst/V/vmsne.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vv.yaml b/arch/inst/V/vmsne.vv.yaml index 69cb50f33..2ac5b85a3 100644 --- a/arch/inst/V/vmsne.vv.yaml +++ b/arch/inst/V/vmsne.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vx.yaml b/arch/inst/V/vmsne.vx.yaml index 0e642b27e..826577646 100644 --- a/arch/inst/V/vmsne.vx.yaml +++ b/arch/inst/V/vmsne.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsof.m.yaml b/arch/inst/V/vmsof.m.yaml index 6d6ff006f..da6f3d05b 100644 --- a/arch/inst/V/vmsof.m.yaml +++ b/arch/inst/V/vmsof.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsof.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmul.vv.yaml b/arch/inst/V/vmul.vv.yaml index 7d91cd8a5..a4210779d 100644 --- a/arch/inst/V/vmul.vv.yaml +++ b/arch/inst/V/vmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmul.vx.yaml b/arch/inst/V/vmul.vx.yaml index e05e8672d..310e32ebd 100644 --- a/arch/inst/V/vmul.vx.yaml +++ b/arch/inst/V/vmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulh.vv.yaml b/arch/inst/V/vmulh.vv.yaml index e189c650e..53e4b0cdf 100644 --- a/arch/inst/V/vmulh.vv.yaml +++ b/arch/inst/V/vmulh.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulh.vx.yaml b/arch/inst/V/vmulh.vx.yaml index 4cf640bad..b3303e0b9 100644 --- a/arch/inst/V/vmulh.vx.yaml +++ b/arch/inst/V/vmulh.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulh.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhsu.vv.yaml b/arch/inst/V/vmulhsu.vv.yaml index bb9a147cf..5b86934be 100644 --- a/arch/inst/V/vmulhsu.vv.yaml +++ b/arch/inst/V/vmulhsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhsu.vx.yaml b/arch/inst/V/vmulhsu.vx.yaml index f81024ed1..133fc39f2 100644 --- a/arch/inst/V/vmulhsu.vx.yaml +++ b/arch/inst/V/vmulhsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhu.vv.yaml b/arch/inst/V/vmulhu.vv.yaml index a78c29831..c52e92b95 100644 --- a/arch/inst/V/vmulhu.vv.yaml +++ b/arch/inst/V/vmulhu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhu.vx.yaml b/arch/inst/V/vmulhu.vx.yaml index 1ab5613bb..8997d372f 100644 --- a/arch/inst/V/vmulhu.vx.yaml +++ b/arch/inst/V/vmulhu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.s.x.yaml b/arch/inst/V/vmv.s.x.yaml index 2d4a35558..668b3eac6 100644 --- a/arch/inst/V/vmv.s.x.yaml +++ b/arch/inst/V/vmv.s.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.s.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010000100000-----110-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.i.yaml b/arch/inst/V/vmv.v.i.yaml index dee7de9ec..94adc6c7d 100644 --- a/arch/inst/V/vmv.v.i.yaml +++ b/arch/inst/V/vmv.v.i.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.i long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vd, imm encoding: match: 010111100000-----011-----1010111 variables: - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.v.yaml b/arch/inst/V/vmv.v.v.yaml index 29cdff608..bd4775fc5 100644 --- a/arch/inst/V/vmv.v.v.yaml +++ b/arch/inst/V/vmv.v.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs1, vd encoding: match: 010111100000-----000-----1010111 variables: - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.x.yaml b/arch/inst/V/vmv.v.x.yaml index 5efb079a0..7ddc9569e 100644 --- a/arch/inst/V/vmv.v.x.yaml +++ b/arch/inst/V/vmv.v.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010111100000-----100-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.x.s.yaml b/arch/inst/V/vmv.x.s.yaml index 40aed3db6..ae424d3dd 100644 --- a/arch/inst/V/vmv.x.s.yaml +++ b/arch/inst/V/vmv.x.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.x.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xd encoding: match: 0100001-----00000010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv1r.v.yaml b/arch/inst/V/vmv1r.v.yaml index 4d3d470ed..e6be91c90 100644 --- a/arch/inst/V/vmv1r.v.yaml +++ b/arch/inst/V/vmv1r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv1r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00000011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv2r.v.yaml b/arch/inst/V/vmv2r.v.yaml index 88b8705a1..98de56eb6 100644 --- a/arch/inst/V/vmv2r.v.yaml +++ b/arch/inst/V/vmv2r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv2r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00001011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv4r.v.yaml b/arch/inst/V/vmv4r.v.yaml index 99ac5a720..525b1e736 100644 --- a/arch/inst/V/vmv4r.v.yaml +++ b/arch/inst/V/vmv4r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv4r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00011011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv8r.v.yaml b/arch/inst/V/vmv8r.v.yaml index 66074274c..d2b6fe8ba 100644 --- a/arch/inst/V/vmv8r.v.yaml +++ b/arch/inst/V/vmv8r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv8r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00111011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmxnor.mm.yaml b/arch/inst/V/vmxnor.mm.yaml index e4f9dbf04..426539a0a 100644 --- a/arch/inst/V/vmxnor.mm.yaml +++ b/arch/inst/V/vmxnor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmxnor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmxor.mm.yaml b/arch/inst/V/vmxor.mm.yaml index ec0ea44ef..1e035d0ad 100644 --- a/arch/inst/V/vmxor.mm.yaml +++ b/arch/inst/V/vmxor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmxor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wi.yaml b/arch/inst/V/vnclip.wi.yaml index e231052ab..9effdbccd 100644 --- a/arch/inst/V/vnclip.wi.yaml +++ b/arch/inst/V/vnclip.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wv.yaml b/arch/inst/V/vnclip.wv.yaml index faca59c93..bdb5b5127 100644 --- a/arch/inst/V/vnclip.wv.yaml +++ b/arch/inst/V/vnclip.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wx.yaml b/arch/inst/V/vnclip.wx.yaml index ee879075e..ade93bcf0 100644 --- a/arch/inst/V/vnclip.wx.yaml +++ b/arch/inst/V/vnclip.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wi.yaml b/arch/inst/V/vnclipu.wi.yaml index 7cf326ed0..8ff4cfea1 100644 --- a/arch/inst/V/vnclipu.wi.yaml +++ b/arch/inst/V/vnclipu.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wv.yaml b/arch/inst/V/vnclipu.wv.yaml index b4a565a40..286cb1705 100644 --- a/arch/inst/V/vnclipu.wv.yaml +++ b/arch/inst/V/vnclipu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wx.yaml b/arch/inst/V/vnclipu.wx.yaml index af13d2fe9..f25012a8b 100644 --- a/arch/inst/V/vnclipu.wx.yaml +++ b/arch/inst/V/vnclipu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsac.vv.yaml b/arch/inst/V/vnmsac.vv.yaml index f9426f75c..cc878e7d3 100644 --- a/arch/inst/V/vnmsac.vv.yaml +++ b/arch/inst/V/vnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsac.vx.yaml b/arch/inst/V/vnmsac.vx.yaml index 307b1d45a..17ae1f83a 100644 --- a/arch/inst/V/vnmsac.vx.yaml +++ b/arch/inst/V/vnmsac.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsac.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsub.vv.yaml b/arch/inst/V/vnmsub.vv.yaml index 23c4cfdaf..57c1ac53c 100644 --- a/arch/inst/V/vnmsub.vv.yaml +++ b/arch/inst/V/vnmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsub.vx.yaml b/arch/inst/V/vnmsub.vx.yaml index 95270f1a9..49bb3f4b3 100644 --- a/arch/inst/V/vnmsub.vx.yaml +++ b/arch/inst/V/vnmsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wi.yaml b/arch/inst/V/vnsra.wi.yaml index 67e6aaa0f..dd25b2645 100644 --- a/arch/inst/V/vnsra.wi.yaml +++ b/arch/inst/V/vnsra.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wv.yaml b/arch/inst/V/vnsra.wv.yaml index a9e6be115..e016d2fef 100644 --- a/arch/inst/V/vnsra.wv.yaml +++ b/arch/inst/V/vnsra.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wx.yaml b/arch/inst/V/vnsra.wx.yaml index f8e6b0559..663fbca1a 100644 --- a/arch/inst/V/vnsra.wx.yaml +++ b/arch/inst/V/vnsra.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wi.yaml b/arch/inst/V/vnsrl.wi.yaml index 7b35f84f1..a46b6644b 100644 --- a/arch/inst/V/vnsrl.wi.yaml +++ b/arch/inst/V/vnsrl.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wv.yaml b/arch/inst/V/vnsrl.wv.yaml index 3c8c95679..1822c68f8 100644 --- a/arch/inst/V/vnsrl.wv.yaml +++ b/arch/inst/V/vnsrl.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wx.yaml b/arch/inst/V/vnsrl.wx.yaml index 92b3679cf..2a65a17df 100644 --- a/arch/inst/V/vnsrl.wx.yaml +++ b/arch/inst/V/vnsrl.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vor.vi.yaml b/arch/inst/V/vor.vi.yaml index 99f59df67..a3739c34d 100644 --- a/arch/inst/V/vor.vi.yaml +++ b/arch/inst/V/vor.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001010-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vor.vv.yaml b/arch/inst/V/vor.vv.yaml index c83208473..276e2c82e 100644 --- a/arch/inst/V/vor.vv.yaml +++ b/arch/inst/V/vor.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vor.vx.yaml b/arch/inst/V/vor.vx.yaml index 9ad6b20d1..2633fb284 100644 --- a/arch/inst/V/vor.vx.yaml +++ b/arch/inst/V/vor.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredand.vs.yaml b/arch/inst/V/vredand.vs.yaml index 135ed6bb3..7679f5f5c 100644 --- a/arch/inst/V/vredand.vs.yaml +++ b/arch/inst/V/vredand.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredand.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmax.vs.yaml b/arch/inst/V/vredmax.vs.yaml index 9d1b12a38..5f6901270 100644 --- a/arch/inst/V/vredmax.vs.yaml +++ b/arch/inst/V/vredmax.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmax.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmaxu.vs.yaml b/arch/inst/V/vredmaxu.vs.yaml index 977d71dac..76c5a0396 100644 --- a/arch/inst/V/vredmaxu.vs.yaml +++ b/arch/inst/V/vredmaxu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmaxu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmin.vs.yaml b/arch/inst/V/vredmin.vs.yaml index df9b4ba46..f7e412441 100644 --- a/arch/inst/V/vredmin.vs.yaml +++ b/arch/inst/V/vredmin.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmin.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredminu.vs.yaml b/arch/inst/V/vredminu.vs.yaml index f3ee165cb..b54e850d6 100644 --- a/arch/inst/V/vredminu.vs.yaml +++ b/arch/inst/V/vredminu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredminu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredor.vs.yaml b/arch/inst/V/vredor.vs.yaml index 121bee827..676a9903e 100644 --- a/arch/inst/V/vredor.vs.yaml +++ b/arch/inst/V/vredor.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredor.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredsum.vs.yaml b/arch/inst/V/vredsum.vs.yaml index be0b41c8b..42826d911 100644 --- a/arch/inst/V/vredsum.vs.yaml +++ b/arch/inst/V/vredsum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredsum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredxor.vs.yaml b/arch/inst/V/vredxor.vs.yaml index b9500c5ac..5203454a6 100644 --- a/arch/inst/V/vredxor.vs.yaml +++ b/arch/inst/V/vredxor.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredxor.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrem.vv.yaml b/arch/inst/V/vrem.vv.yaml index 54b445872..39f6b5228 100644 --- a/arch/inst/V/vrem.vv.yaml +++ b/arch/inst/V/vrem.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrem.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrem.vx.yaml b/arch/inst/V/vrem.vx.yaml index 976f7a73b..4d487b0b2 100644 --- a/arch/inst/V/vrem.vx.yaml +++ b/arch/inst/V/vrem.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrem.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vremu.vv.yaml b/arch/inst/V/vremu.vv.yaml index 4262b9e29..f166b2c60 100644 --- a/arch/inst/V/vremu.vv.yaml +++ b/arch/inst/V/vremu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vremu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vremu.vx.yaml b/arch/inst/V/vremu.vx.yaml index 3709f7afc..1e80ef3c4 100644 --- a/arch/inst/V/vremu.vx.yaml +++ b/arch/inst/V/vremu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vremu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrgather.vi.yaml b/arch/inst/V/vrgather.vi.yaml index 8f8c6f157..1e81be3cf 100644 --- a/arch/inst/V/vrgather.vi.yaml +++ b/arch/inst/V/vrgather.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgather.vv.yaml b/arch/inst/V/vrgather.vv.yaml index 17c92e6d4..dd538e277 100644 --- a/arch/inst/V/vrgather.vv.yaml +++ b/arch/inst/V/vrgather.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgather.vx.yaml b/arch/inst/V/vrgather.vx.yaml index 10763af3b..eae65325d 100644 --- a/arch/inst/V/vrgather.vx.yaml +++ b/arch/inst/V/vrgather.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgatherei16.vv.yaml b/arch/inst/V/vrgatherei16.vv.yaml index 3edfd3f2b..f823b9ed6 100644 --- a/arch/inst/V/vrgatherei16.vv.yaml +++ b/arch/inst/V/vrgatherei16.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgatherei16.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrsub.vi.yaml b/arch/inst/V/vrsub.vi.yaml index 5e369d5e1..b5b332738 100644 --- a/arch/inst/V/vrsub.vi.yaml +++ b/arch/inst/V/vrsub.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrsub.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 000011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrsub.vx.yaml b/arch/inst/V/vrsub.vx.yaml index 2981fdbe0..8891c4031 100644 --- a/arch/inst/V/vrsub.vx.yaml +++ b/arch/inst/V/vrsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vs1r.v.yaml b/arch/inst/V/vs1r.v.yaml index 16af81c2f..766dc6573 100644 --- a/arch/inst/V/vs1r.v.yaml +++ b/arch/inst/V/vs1r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs1r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 000000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs2r.v.yaml b/arch/inst/V/vs2r.v.yaml index ca01f05fd..f9ecdeead 100644 --- a/arch/inst/V/vs2r.v.yaml +++ b/arch/inst/V/vs2r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs2r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 001000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs4r.v.yaml b/arch/inst/V/vs4r.v.yaml index a035f4cc4..57fc54fa5 100644 --- a/arch/inst/V/vs4r.v.yaml +++ b/arch/inst/V/vs4r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs4r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 011000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs8r.v.yaml b/arch/inst/V/vs8r.v.yaml index 31126a57f..e5c66e617 100644 --- a/arch/inst/V/vs8r.v.yaml +++ b/arch/inst/V/vs8r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs8r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 111000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsadd.vi.yaml b/arch/inst/V/vsadd.vi.yaml index 59d37d92d..7a9a80e2a 100644 --- a/arch/inst/V/vsadd.vi.yaml +++ b/arch/inst/V/vsadd.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsadd.vv.yaml b/arch/inst/V/vsadd.vv.yaml index 6a9e51dc6..e1a4d0dda 100644 --- a/arch/inst/V/vsadd.vv.yaml +++ b/arch/inst/V/vsadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsadd.vx.yaml b/arch/inst/V/vsadd.vx.yaml index cd4d2f1f5..b4046c81c 100644 --- a/arch/inst/V/vsadd.vx.yaml +++ b/arch/inst/V/vsadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsaddu.vi.yaml b/arch/inst/V/vsaddu.vi.yaml index 0aac71bce..6828c2cda 100644 --- a/arch/inst/V/vsaddu.vi.yaml +++ b/arch/inst/V/vsaddu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsaddu.vv.yaml b/arch/inst/V/vsaddu.vv.yaml index e2514e2c7..3b75a0cb6 100644 --- a/arch/inst/V/vsaddu.vv.yaml +++ b/arch/inst/V/vsaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsaddu.vx.yaml b/arch/inst/V/vsaddu.vx.yaml index 5cfbc7fc2..9806bcb73 100644 --- a/arch/inst/V/vsaddu.vx.yaml +++ b/arch/inst/V/vsaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsbc.vvm.yaml b/arch/inst/V/vsbc.vvm.yaml index 646653fc5..0c3cd660e 100644 --- a/arch/inst/V/vsbc.vvm.yaml +++ b/arch/inst/V/vsbc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsbc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100100----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsbc.vxm.yaml b/arch/inst/V/vsbc.vxm.yaml index f3a6fabcb..31b5511dd 100644 --- a/arch/inst/V/vsbc.vxm.yaml +++ b/arch/inst/V/vsbc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsbc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100100----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vse16.v.yaml b/arch/inst/V/vse16.v.yaml index 46f1bef23..97ad5521e 100644 --- a/arch/inst/V/vse16.v.yaml +++ b/arch/inst/V/vse16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse32.v.yaml b/arch/inst/V/vse32.v.yaml index 9db60760d..45d3cd35d 100644 --- a/arch/inst/V/vse32.v.yaml +++ b/arch/inst/V/vse32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse64.v.yaml b/arch/inst/V/vse64.v.yaml index 3fbfabaed..3b21d66e4 100644 --- a/arch/inst/V/vse64.v.yaml +++ b/arch/inst/V/vse64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse8.v.yaml b/arch/inst/V/vse8.v.yaml index b3be72b1e..ed2eefef5 100644 --- a/arch/inst/V/vse8.v.yaml +++ b/arch/inst/V/vse8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsetivli.yaml b/arch/inst/V/vsetivli.yaml index 623b27b24..e45be1043 100644 --- a/arch/inst/V/vsetivli.yaml +++ b/arch/inst/V/vsetivli.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetivli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xd, imm encoding: match: 11---------------111-----1010111 variables: - - name: zimm10 - location: 29-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: zimm10 + location: 29-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let VLEN_pow = get_vlen_pow(); diff --git a/arch/inst/V/vsetvl.yaml b/arch/inst/V/vsetvl.yaml index a66a6759f..ca13695d8 100644 --- a/arch/inst/V/vsetvl.yaml +++ b/arch/inst/V/vsetvl.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetvl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs2, xs1, xd encoding: match: 1000000----------111-----1010111 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsetvli.yaml b/arch/inst/V/vsetvli.yaml index 93995b765..aeb3569bb 100644 --- a/arch/inst/V/vsetvli.yaml +++ b/arch/inst/V/vsetvli.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetvli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, xd, imm encoding: match: 0----------------111-----1010111 variables: - - name: zimm11 - location: 30-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: zimm11 + location: 30-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let VLEN_pow = get_vlen_pow(); diff --git a/arch/inst/V/vsext.vf2.yaml b/arch/inst/V/vsext.vf2.yaml index 2a16a1202..4ad76d17f 100644 --- a/arch/inst/V/vsext.vf2.yaml +++ b/arch/inst/V/vsext.vf2.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00111010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsext.vf4.yaml b/arch/inst/V/vsext.vf4.yaml index 430cd84ab..008a0f629 100644 --- a/arch/inst/V/vsext.vf4.yaml +++ b/arch/inst/V/vsext.vf4.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00101010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsext.vf8.yaml b/arch/inst/V/vsext.vf8.yaml index 4c1c171a7..864e4141d 100644 --- a/arch/inst/V/vsext.vf8.yaml +++ b/arch/inst/V/vsext.vf8.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00011010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslide1down.vx.yaml b/arch/inst/V/vslide1down.vx.yaml index fdf239d02..47ac7e37b 100644 --- a/arch/inst/V/vslide1down.vx.yaml +++ b/arch/inst/V/vslide1down.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslide1down.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslide1up.vx.yaml b/arch/inst/V/vslide1up.vx.yaml index 12201fa9d..05335c0fd 100644 --- a/arch/inst/V/vslide1up.vx.yaml +++ b/arch/inst/V/vslide1up.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslide1up.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslidedown.vi.yaml b/arch/inst/V/vslidedown.vi.yaml index 5253fa5aa..dfadb71b6 100644 --- a/arch/inst/V/vslidedown.vi.yaml +++ b/arch/inst/V/vslidedown.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslidedown.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslidedown.vx.yaml b/arch/inst/V/vslidedown.vx.yaml index ed5f7b066..2b73f1063 100644 --- a/arch/inst/V/vslidedown.vx.yaml +++ b/arch/inst/V/vslidedown.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslidedown.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslideup.vi.yaml b/arch/inst/V/vslideup.vi.yaml index cdda8b516..0a9ce8b46 100644 --- a/arch/inst/V/vslideup.vi.yaml +++ b/arch/inst/V/vslideup.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslideup.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslideup.vx.yaml b/arch/inst/V/vslideup.vx.yaml index 4ac68fa34..5f4df3da7 100644 --- a/arch/inst/V/vslideup.vx.yaml +++ b/arch/inst/V/vslideup.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslideup.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsll.vi.yaml b/arch/inst/V/vsll.vi.yaml index 317629bf0..bb7407f04 100644 --- a/arch/inst/V/vsll.vi.yaml +++ b/arch/inst/V/vsll.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsll.vv.yaml b/arch/inst/V/vsll.vv.yaml index 505eb734f..fcf60a37d 100644 --- a/arch/inst/V/vsll.vv.yaml +++ b/arch/inst/V/vsll.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsll.vx.yaml b/arch/inst/V/vsll.vx.yaml index 7f9222735..2c5f041f7 100644 --- a/arch/inst/V/vsll.vx.yaml +++ b/arch/inst/V/vsll.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsm.v.yaml b/arch/inst/V/vsm.v.yaml index a50fe111d..b8e7ace24 100644 --- a/arch/inst/V/vsm.v.yaml +++ b/arch/inst/V/vsm.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vsm.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 000000101011-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW = 8; diff --git a/arch/inst/V/vsmul.vv.yaml b/arch/inst/V/vsmul.vv.yaml index 33a0955db..856e75f82 100644 --- a/arch/inst/V/vsmul.vv.yaml +++ b/arch/inst/V/vsmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsmul.vx.yaml b/arch/inst/V/vsmul.vx.yaml index 8d76ae1ee..b70c9b089 100644 --- a/arch/inst/V/vsmul.vx.yaml +++ b/arch/inst/V/vsmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsoxei16.v.yaml b/arch/inst/V/vsoxei16.v.yaml index ded610f65..c0f6d4b0f 100644 --- a/arch/inst/V/vsoxei16.v.yaml +++ b/arch/inst/V/vsoxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei32.v.yaml b/arch/inst/V/vsoxei32.v.yaml index c66fc7baf..1c14c90db 100644 --- a/arch/inst/V/vsoxei32.v.yaml +++ b/arch/inst/V/vsoxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei64.v.yaml b/arch/inst/V/vsoxei64.v.yaml index 1077b0db4..f7bcf8faf 100644 --- a/arch/inst/V/vsoxei64.v.yaml +++ b/arch/inst/V/vsoxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei8.v.yaml b/arch/inst/V/vsoxei8.v.yaml index a45891a50..6b4107b6f 100644 --- a/arch/inst/V/vsoxei8.v.yaml +++ b/arch/inst/V/vsoxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxseg2ei16.v.yaml b/arch/inst/V/vsoxseg2ei16.v.yaml index e86e45ad3..780956218 100644 --- a/arch/inst/V/vsoxseg2ei16.v.yaml +++ b/arch/inst/V/vsoxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei32.v.yaml b/arch/inst/V/vsoxseg2ei32.v.yaml index 9b45cee7a..6ffd055d2 100644 --- a/arch/inst/V/vsoxseg2ei32.v.yaml +++ b/arch/inst/V/vsoxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei64.v.yaml b/arch/inst/V/vsoxseg2ei64.v.yaml index 95f803fbf..f11488f21 100644 --- a/arch/inst/V/vsoxseg2ei64.v.yaml +++ b/arch/inst/V/vsoxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei8.v.yaml b/arch/inst/V/vsoxseg2ei8.v.yaml index 4234761a3..48a1b8609 100644 --- a/arch/inst/V/vsoxseg2ei8.v.yaml +++ b/arch/inst/V/vsoxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei16.v.yaml b/arch/inst/V/vsoxseg3ei16.v.yaml index fe32adab1..89c24ecba 100644 --- a/arch/inst/V/vsoxseg3ei16.v.yaml +++ b/arch/inst/V/vsoxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei32.v.yaml b/arch/inst/V/vsoxseg3ei32.v.yaml index 3c66f7a41..66d2c99ad 100644 --- a/arch/inst/V/vsoxseg3ei32.v.yaml +++ b/arch/inst/V/vsoxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei64.v.yaml b/arch/inst/V/vsoxseg3ei64.v.yaml index ca20fe8fa..ef6dc0e5c 100644 --- a/arch/inst/V/vsoxseg3ei64.v.yaml +++ b/arch/inst/V/vsoxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei8.v.yaml b/arch/inst/V/vsoxseg3ei8.v.yaml index 4df149f00..8b6c8c664 100644 --- a/arch/inst/V/vsoxseg3ei8.v.yaml +++ b/arch/inst/V/vsoxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei16.v.yaml b/arch/inst/V/vsoxseg4ei16.v.yaml index 9a386ba92..9342ab053 100644 --- a/arch/inst/V/vsoxseg4ei16.v.yaml +++ b/arch/inst/V/vsoxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei32.v.yaml b/arch/inst/V/vsoxseg4ei32.v.yaml index 9bf3d9447..dca2a2629 100644 --- a/arch/inst/V/vsoxseg4ei32.v.yaml +++ b/arch/inst/V/vsoxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei64.v.yaml b/arch/inst/V/vsoxseg4ei64.v.yaml index 0b1d62d81..d2194a594 100644 --- a/arch/inst/V/vsoxseg4ei64.v.yaml +++ b/arch/inst/V/vsoxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei8.v.yaml b/arch/inst/V/vsoxseg4ei8.v.yaml index 078aa7a6c..81cfe37ff 100644 --- a/arch/inst/V/vsoxseg4ei8.v.yaml +++ b/arch/inst/V/vsoxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei16.v.yaml b/arch/inst/V/vsoxseg5ei16.v.yaml index 182b82153..f02483e2c 100644 --- a/arch/inst/V/vsoxseg5ei16.v.yaml +++ b/arch/inst/V/vsoxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei32.v.yaml b/arch/inst/V/vsoxseg5ei32.v.yaml index 865cd68d7..7024201e5 100644 --- a/arch/inst/V/vsoxseg5ei32.v.yaml +++ b/arch/inst/V/vsoxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei64.v.yaml b/arch/inst/V/vsoxseg5ei64.v.yaml index ba7330e7b..1aeac7261 100644 --- a/arch/inst/V/vsoxseg5ei64.v.yaml +++ b/arch/inst/V/vsoxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei8.v.yaml b/arch/inst/V/vsoxseg5ei8.v.yaml index 85dcb2bb9..dd72f35f7 100644 --- a/arch/inst/V/vsoxseg5ei8.v.yaml +++ b/arch/inst/V/vsoxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei16.v.yaml b/arch/inst/V/vsoxseg6ei16.v.yaml index 6a4630a84..859d840d2 100644 --- a/arch/inst/V/vsoxseg6ei16.v.yaml +++ b/arch/inst/V/vsoxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei32.v.yaml b/arch/inst/V/vsoxseg6ei32.v.yaml index 1ff23a132..21ab89a24 100644 --- a/arch/inst/V/vsoxseg6ei32.v.yaml +++ b/arch/inst/V/vsoxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei64.v.yaml b/arch/inst/V/vsoxseg6ei64.v.yaml index 3ccbd6450..e3128fde8 100644 --- a/arch/inst/V/vsoxseg6ei64.v.yaml +++ b/arch/inst/V/vsoxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei8.v.yaml b/arch/inst/V/vsoxseg6ei8.v.yaml index a40cae05f..a76414ef0 100644 --- a/arch/inst/V/vsoxseg6ei8.v.yaml +++ b/arch/inst/V/vsoxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei16.v.yaml b/arch/inst/V/vsoxseg7ei16.v.yaml index f6378ac9c..6b1ea51f0 100644 --- a/arch/inst/V/vsoxseg7ei16.v.yaml +++ b/arch/inst/V/vsoxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei32.v.yaml b/arch/inst/V/vsoxseg7ei32.v.yaml index 3359414cd..aa95e5612 100644 --- a/arch/inst/V/vsoxseg7ei32.v.yaml +++ b/arch/inst/V/vsoxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei64.v.yaml b/arch/inst/V/vsoxseg7ei64.v.yaml index c92e97431..0d123c019 100644 --- a/arch/inst/V/vsoxseg7ei64.v.yaml +++ b/arch/inst/V/vsoxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei8.v.yaml b/arch/inst/V/vsoxseg7ei8.v.yaml index 8be28249c..61ec4b9eb 100644 --- a/arch/inst/V/vsoxseg7ei8.v.yaml +++ b/arch/inst/V/vsoxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei16.v.yaml b/arch/inst/V/vsoxseg8ei16.v.yaml index 7231e6acc..8ad68b503 100644 --- a/arch/inst/V/vsoxseg8ei16.v.yaml +++ b/arch/inst/V/vsoxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei32.v.yaml b/arch/inst/V/vsoxseg8ei32.v.yaml index f1b306a0f..1f9e8ff9f 100644 --- a/arch/inst/V/vsoxseg8ei32.v.yaml +++ b/arch/inst/V/vsoxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei64.v.yaml b/arch/inst/V/vsoxseg8ei64.v.yaml index 71e1e6404..033e7583e 100644 --- a/arch/inst/V/vsoxseg8ei64.v.yaml +++ b/arch/inst/V/vsoxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei8.v.yaml b/arch/inst/V/vsoxseg8ei8.v.yaml index f2ae50725..11b3bf923 100644 --- a/arch/inst/V/vsoxseg8ei8.v.yaml +++ b/arch/inst/V/vsoxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsra.vi.yaml b/arch/inst/V/vsra.vi.yaml index 794126b65..077d49bfc 100644 --- a/arch/inst/V/vsra.vi.yaml +++ b/arch/inst/V/vsra.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsra.vv.yaml b/arch/inst/V/vsra.vv.yaml index 961684129..b46265e90 100644 --- a/arch/inst/V/vsra.vv.yaml +++ b/arch/inst/V/vsra.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsra.vx.yaml b/arch/inst/V/vsra.vx.yaml index ce374fd8d..405ab82cf 100644 --- a/arch/inst/V/vsra.vx.yaml +++ b/arch/inst/V/vsra.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vi.yaml b/arch/inst/V/vsrl.vi.yaml index a3186c341..acdfbc986 100644 --- a/arch/inst/V/vsrl.vi.yaml +++ b/arch/inst/V/vsrl.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vv.yaml b/arch/inst/V/vsrl.vv.yaml index 9ab40d644..a458251a6 100644 --- a/arch/inst/V/vsrl.vv.yaml +++ b/arch/inst/V/vsrl.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsrl.vx.yaml b/arch/inst/V/vsrl.vx.yaml index dc0fc032f..33400a4b9 100644 --- a/arch/inst/V/vsrl.vx.yaml +++ b/arch/inst/V/vsrl.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsse16.v.yaml b/arch/inst/V/vsse16.v.yaml index 2bfe4dcd6..554f3cbad 100644 --- a/arch/inst/V/vsse16.v.yaml +++ b/arch/inst/V/vsse16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse32.v.yaml b/arch/inst/V/vsse32.v.yaml index 3f543d07e..790271b4e 100644 --- a/arch/inst/V/vsse32.v.yaml +++ b/arch/inst/V/vsse32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse64.v.yaml b/arch/inst/V/vsse64.v.yaml index dbfba2161..65301a84b 100644 --- a/arch/inst/V/vsse64.v.yaml +++ b/arch/inst/V/vsse64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse8.v.yaml b/arch/inst/V/vsse8.v.yaml index 66257c58e..3dad5795d 100644 --- a/arch/inst/V/vsse8.v.yaml +++ b/arch/inst/V/vsse8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsseg2e16.v.yaml b/arch/inst/V/vsseg2e16.v.yaml index cd4e5be9d..7f3b2e3d3 100644 --- a/arch/inst/V/vsseg2e16.v.yaml +++ b/arch/inst/V/vsseg2e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e32.v.yaml b/arch/inst/V/vsseg2e32.v.yaml index 601e3b994..96e79cf76 100644 --- a/arch/inst/V/vsseg2e32.v.yaml +++ b/arch/inst/V/vsseg2e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e64.v.yaml b/arch/inst/V/vsseg2e64.v.yaml index 62ed3f80d..fb88709c7 100644 --- a/arch/inst/V/vsseg2e64.v.yaml +++ b/arch/inst/V/vsseg2e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e8.v.yaml b/arch/inst/V/vsseg2e8.v.yaml index e66d94ecb..88d987cee 100644 --- a/arch/inst/V/vsseg2e8.v.yaml +++ b/arch/inst/V/vsseg2e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e16.v.yaml b/arch/inst/V/vsseg3e16.v.yaml index ffde8ab7e..6ad792758 100644 --- a/arch/inst/V/vsseg3e16.v.yaml +++ b/arch/inst/V/vsseg3e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e32.v.yaml b/arch/inst/V/vsseg3e32.v.yaml index 68e204cc6..7f5036f7d 100644 --- a/arch/inst/V/vsseg3e32.v.yaml +++ b/arch/inst/V/vsseg3e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e64.v.yaml b/arch/inst/V/vsseg3e64.v.yaml index f32e623f2..6e0821deb 100644 --- a/arch/inst/V/vsseg3e64.v.yaml +++ b/arch/inst/V/vsseg3e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e8.v.yaml b/arch/inst/V/vsseg3e8.v.yaml index 4816d14c4..314c55bd8 100644 --- a/arch/inst/V/vsseg3e8.v.yaml +++ b/arch/inst/V/vsseg3e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e16.v.yaml b/arch/inst/V/vsseg4e16.v.yaml index 538a9b67d..b319f4e46 100644 --- a/arch/inst/V/vsseg4e16.v.yaml +++ b/arch/inst/V/vsseg4e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e32.v.yaml b/arch/inst/V/vsseg4e32.v.yaml index 41b149778..80f857393 100644 --- a/arch/inst/V/vsseg4e32.v.yaml +++ b/arch/inst/V/vsseg4e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e64.v.yaml b/arch/inst/V/vsseg4e64.v.yaml index 6203e1086..4e3ba8c29 100644 --- a/arch/inst/V/vsseg4e64.v.yaml +++ b/arch/inst/V/vsseg4e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e8.v.yaml b/arch/inst/V/vsseg4e8.v.yaml index 2514dfdbe..b8eb7e45b 100644 --- a/arch/inst/V/vsseg4e8.v.yaml +++ b/arch/inst/V/vsseg4e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e16.v.yaml b/arch/inst/V/vsseg5e16.v.yaml index 100f59fbf..d7a4f68e5 100644 --- a/arch/inst/V/vsseg5e16.v.yaml +++ b/arch/inst/V/vsseg5e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e32.v.yaml b/arch/inst/V/vsseg5e32.v.yaml index ad3a2cb19..3d3158a21 100644 --- a/arch/inst/V/vsseg5e32.v.yaml +++ b/arch/inst/V/vsseg5e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e64.v.yaml b/arch/inst/V/vsseg5e64.v.yaml index ff071f25c..13a817a58 100644 --- a/arch/inst/V/vsseg5e64.v.yaml +++ b/arch/inst/V/vsseg5e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e8.v.yaml b/arch/inst/V/vsseg5e8.v.yaml index fda9c36a0..73be34634 100644 --- a/arch/inst/V/vsseg5e8.v.yaml +++ b/arch/inst/V/vsseg5e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e16.v.yaml b/arch/inst/V/vsseg6e16.v.yaml index 4b2e5983e..d0780baf2 100644 --- a/arch/inst/V/vsseg6e16.v.yaml +++ b/arch/inst/V/vsseg6e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e32.v.yaml b/arch/inst/V/vsseg6e32.v.yaml index 1d08c1db3..54d50abbd 100644 --- a/arch/inst/V/vsseg6e32.v.yaml +++ b/arch/inst/V/vsseg6e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e64.v.yaml b/arch/inst/V/vsseg6e64.v.yaml index a267cb199..f6f5dfde5 100644 --- a/arch/inst/V/vsseg6e64.v.yaml +++ b/arch/inst/V/vsseg6e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e8.v.yaml b/arch/inst/V/vsseg6e8.v.yaml index b5e3a702d..5d0c35b2d 100644 --- a/arch/inst/V/vsseg6e8.v.yaml +++ b/arch/inst/V/vsseg6e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e16.v.yaml b/arch/inst/V/vsseg7e16.v.yaml index e0220080a..2a5443f0b 100644 --- a/arch/inst/V/vsseg7e16.v.yaml +++ b/arch/inst/V/vsseg7e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e32.v.yaml b/arch/inst/V/vsseg7e32.v.yaml index 3a6a88528..e23b7ea0a 100644 --- a/arch/inst/V/vsseg7e32.v.yaml +++ b/arch/inst/V/vsseg7e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e64.v.yaml b/arch/inst/V/vsseg7e64.v.yaml index b2935f7d6..23afb696c 100644 --- a/arch/inst/V/vsseg7e64.v.yaml +++ b/arch/inst/V/vsseg7e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e8.v.yaml b/arch/inst/V/vsseg7e8.v.yaml index 1851b32c2..8484d868c 100644 --- a/arch/inst/V/vsseg7e8.v.yaml +++ b/arch/inst/V/vsseg7e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e16.v.yaml b/arch/inst/V/vsseg8e16.v.yaml index 65e45fad9..f0d052453 100644 --- a/arch/inst/V/vsseg8e16.v.yaml +++ b/arch/inst/V/vsseg8e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e32.v.yaml b/arch/inst/V/vsseg8e32.v.yaml index 46bc8e9c7..ad61206dd 100644 --- a/arch/inst/V/vsseg8e32.v.yaml +++ b/arch/inst/V/vsseg8e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e64.v.yaml b/arch/inst/V/vsseg8e64.v.yaml index 736480a8c..fcfed3d01 100644 --- a/arch/inst/V/vsseg8e64.v.yaml +++ b/arch/inst/V/vsseg8e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e8.v.yaml b/arch/inst/V/vsseg8e8.v.yaml index 3903f33c7..4b0f9d106 100644 --- a/arch/inst/V/vsseg8e8.v.yaml +++ b/arch/inst/V/vsseg8e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssra.vi.yaml b/arch/inst/V/vssra.vi.yaml index d89c9d999..e3fce2d3b 100644 --- a/arch/inst/V/vssra.vi.yaml +++ b/arch/inst/V/vssra.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssra.vv.yaml b/arch/inst/V/vssra.vv.yaml index 7b8f6aa47..72f82eea9 100644 --- a/arch/inst/V/vssra.vv.yaml +++ b/arch/inst/V/vssra.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssra.vx.yaml b/arch/inst/V/vssra.vx.yaml index 24f3e5821..33f3cd692 100644 --- a/arch/inst/V/vssra.vx.yaml +++ b/arch/inst/V/vssra.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssrl.vi.yaml b/arch/inst/V/vssrl.vi.yaml index c763b4663..49ed2325d 100644 --- a/arch/inst/V/vssrl.vi.yaml +++ b/arch/inst/V/vssrl.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101010-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssrl.vv.yaml b/arch/inst/V/vssrl.vv.yaml index abc1547ff..6538af90a 100644 --- a/arch/inst/V/vssrl.vv.yaml +++ b/arch/inst/V/vssrl.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssrl.vx.yaml b/arch/inst/V/vssrl.vx.yaml index b5f8e4d92..e5ef08572 100644 --- a/arch/inst/V/vssrl.vx.yaml +++ b/arch/inst/V/vssrl.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssseg2e16.v.yaml b/arch/inst/V/vssseg2e16.v.yaml index 66ef1a90a..ae2407c8c 100644 --- a/arch/inst/V/vssseg2e16.v.yaml +++ b/arch/inst/V/vssseg2e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e32.v.yaml b/arch/inst/V/vssseg2e32.v.yaml index e562929f3..7c2a264b8 100644 --- a/arch/inst/V/vssseg2e32.v.yaml +++ b/arch/inst/V/vssseg2e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e64.v.yaml b/arch/inst/V/vssseg2e64.v.yaml index a6914aa38..24379b0d8 100644 --- a/arch/inst/V/vssseg2e64.v.yaml +++ b/arch/inst/V/vssseg2e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e8.v.yaml b/arch/inst/V/vssseg2e8.v.yaml index 8f70c1648..17159a08c 100644 --- a/arch/inst/V/vssseg2e8.v.yaml +++ b/arch/inst/V/vssseg2e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e16.v.yaml b/arch/inst/V/vssseg3e16.v.yaml index 94d3a0419..911a9e987 100644 --- a/arch/inst/V/vssseg3e16.v.yaml +++ b/arch/inst/V/vssseg3e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e32.v.yaml b/arch/inst/V/vssseg3e32.v.yaml index 16a6827d1..8f6b42e64 100644 --- a/arch/inst/V/vssseg3e32.v.yaml +++ b/arch/inst/V/vssseg3e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e64.v.yaml b/arch/inst/V/vssseg3e64.v.yaml index 2808af060..0acc82336 100644 --- a/arch/inst/V/vssseg3e64.v.yaml +++ b/arch/inst/V/vssseg3e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e8.v.yaml b/arch/inst/V/vssseg3e8.v.yaml index 0a19eeefd..8bf8e5151 100644 --- a/arch/inst/V/vssseg3e8.v.yaml +++ b/arch/inst/V/vssseg3e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e16.v.yaml b/arch/inst/V/vssseg4e16.v.yaml index 01bce54cc..5c44fa085 100644 --- a/arch/inst/V/vssseg4e16.v.yaml +++ b/arch/inst/V/vssseg4e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e32.v.yaml b/arch/inst/V/vssseg4e32.v.yaml index f506f43e2..55a124d85 100644 --- a/arch/inst/V/vssseg4e32.v.yaml +++ b/arch/inst/V/vssseg4e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e64.v.yaml b/arch/inst/V/vssseg4e64.v.yaml index f4206f314..18d38c200 100644 --- a/arch/inst/V/vssseg4e64.v.yaml +++ b/arch/inst/V/vssseg4e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e8.v.yaml b/arch/inst/V/vssseg4e8.v.yaml index ca7215e3b..d8f5bd991 100644 --- a/arch/inst/V/vssseg4e8.v.yaml +++ b/arch/inst/V/vssseg4e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e16.v.yaml b/arch/inst/V/vssseg5e16.v.yaml index 8762c52ab..8da14d438 100644 --- a/arch/inst/V/vssseg5e16.v.yaml +++ b/arch/inst/V/vssseg5e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e32.v.yaml b/arch/inst/V/vssseg5e32.v.yaml index 973965755..21934526b 100644 --- a/arch/inst/V/vssseg5e32.v.yaml +++ b/arch/inst/V/vssseg5e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e64.v.yaml b/arch/inst/V/vssseg5e64.v.yaml index 043883ad7..0448d2752 100644 --- a/arch/inst/V/vssseg5e64.v.yaml +++ b/arch/inst/V/vssseg5e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e8.v.yaml b/arch/inst/V/vssseg5e8.v.yaml index 2897b4d34..03ba844dc 100644 --- a/arch/inst/V/vssseg5e8.v.yaml +++ b/arch/inst/V/vssseg5e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e16.v.yaml b/arch/inst/V/vssseg6e16.v.yaml index b28278b12..dc7bf73f6 100644 --- a/arch/inst/V/vssseg6e16.v.yaml +++ b/arch/inst/V/vssseg6e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e32.v.yaml b/arch/inst/V/vssseg6e32.v.yaml index 81bceee89..42756c880 100644 --- a/arch/inst/V/vssseg6e32.v.yaml +++ b/arch/inst/V/vssseg6e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e64.v.yaml b/arch/inst/V/vssseg6e64.v.yaml index aa96b349b..070db4524 100644 --- a/arch/inst/V/vssseg6e64.v.yaml +++ b/arch/inst/V/vssseg6e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e8.v.yaml b/arch/inst/V/vssseg6e8.v.yaml index 893688b91..5cd66336d 100644 --- a/arch/inst/V/vssseg6e8.v.yaml +++ b/arch/inst/V/vssseg6e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e16.v.yaml b/arch/inst/V/vssseg7e16.v.yaml index 4a29f6b36..04ac66fa5 100644 --- a/arch/inst/V/vssseg7e16.v.yaml +++ b/arch/inst/V/vssseg7e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e32.v.yaml b/arch/inst/V/vssseg7e32.v.yaml index 9a1c17897..0e287ce0e 100644 --- a/arch/inst/V/vssseg7e32.v.yaml +++ b/arch/inst/V/vssseg7e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e64.v.yaml b/arch/inst/V/vssseg7e64.v.yaml index 682f8ed2b..06affd3f7 100644 --- a/arch/inst/V/vssseg7e64.v.yaml +++ b/arch/inst/V/vssseg7e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e8.v.yaml b/arch/inst/V/vssseg7e8.v.yaml index 5be77062c..83a707000 100644 --- a/arch/inst/V/vssseg7e8.v.yaml +++ b/arch/inst/V/vssseg7e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e16.v.yaml b/arch/inst/V/vssseg8e16.v.yaml index bd3acecbb..72077a601 100644 --- a/arch/inst/V/vssseg8e16.v.yaml +++ b/arch/inst/V/vssseg8e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e32.v.yaml b/arch/inst/V/vssseg8e32.v.yaml index 3e43ac8e4..aeeee12b3 100644 --- a/arch/inst/V/vssseg8e32.v.yaml +++ b/arch/inst/V/vssseg8e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e64.v.yaml b/arch/inst/V/vssseg8e64.v.yaml index ce587b8a6..1876cf425 100644 --- a/arch/inst/V/vssseg8e64.v.yaml +++ b/arch/inst/V/vssseg8e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e8.v.yaml b/arch/inst/V/vssseg8e8.v.yaml index 733f17a9c..a093b5e0e 100644 --- a/arch/inst/V/vssseg8e8.v.yaml +++ b/arch/inst/V/vssseg8e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssub.vv.yaml b/arch/inst/V/vssub.vv.yaml index fe57f480c..582595e08 100644 --- a/arch/inst/V/vssub.vv.yaml +++ b/arch/inst/V/vssub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssub.vx.yaml b/arch/inst/V/vssub.vx.yaml index ea715dcbd..e9aa1eafa 100644 --- a/arch/inst/V/vssub.vx.yaml +++ b/arch/inst/V/vssub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssubu.vv.yaml b/arch/inst/V/vssubu.vv.yaml index d74a1bbd0..52630eede 100644 --- a/arch/inst/V/vssubu.vv.yaml +++ b/arch/inst/V/vssubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssubu.vx.yaml b/arch/inst/V/vssubu.vx.yaml index b810030a6..cfd69dceb 100644 --- a/arch/inst/V/vssubu.vx.yaml +++ b/arch/inst/V/vssubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsub.vv.yaml b/arch/inst/V/vsub.vv.yaml index 9df0336ee..090a04356 100644 --- a/arch/inst/V/vsub.vv.yaml +++ b/arch/inst/V/vsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsub.vx.yaml b/arch/inst/V/vsub.vx.yaml index 64b319044..14f33d6ae 100644 --- a/arch/inst/V/vsub.vx.yaml +++ b/arch/inst/V/vsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsuxei16.v.yaml b/arch/inst/V/vsuxei16.v.yaml index 11de9a7e3..ac763081b 100644 --- a/arch/inst/V/vsuxei16.v.yaml +++ b/arch/inst/V/vsuxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei32.v.yaml b/arch/inst/V/vsuxei32.v.yaml index 8e2587fa3..5620ea6e0 100644 --- a/arch/inst/V/vsuxei32.v.yaml +++ b/arch/inst/V/vsuxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei64.v.yaml b/arch/inst/V/vsuxei64.v.yaml index 690030d76..7a415e73c 100644 --- a/arch/inst/V/vsuxei64.v.yaml +++ b/arch/inst/V/vsuxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei8.v.yaml b/arch/inst/V/vsuxei8.v.yaml index 26fd5fd07..24aa20685 100644 --- a/arch/inst/V/vsuxei8.v.yaml +++ b/arch/inst/V/vsuxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxseg2ei16.v.yaml b/arch/inst/V/vsuxseg2ei16.v.yaml index c6dd0cc86..959db0af0 100644 --- a/arch/inst/V/vsuxseg2ei16.v.yaml +++ b/arch/inst/V/vsuxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei32.v.yaml b/arch/inst/V/vsuxseg2ei32.v.yaml index 29c958694..41b9fb84d 100644 --- a/arch/inst/V/vsuxseg2ei32.v.yaml +++ b/arch/inst/V/vsuxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei64.v.yaml b/arch/inst/V/vsuxseg2ei64.v.yaml index 1004b0400..34a918de5 100644 --- a/arch/inst/V/vsuxseg2ei64.v.yaml +++ b/arch/inst/V/vsuxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei8.v.yaml b/arch/inst/V/vsuxseg2ei8.v.yaml index d17af839e..a43b5fc91 100644 --- a/arch/inst/V/vsuxseg2ei8.v.yaml +++ b/arch/inst/V/vsuxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei16.v.yaml b/arch/inst/V/vsuxseg3ei16.v.yaml index f996907a8..18575b61a 100644 --- a/arch/inst/V/vsuxseg3ei16.v.yaml +++ b/arch/inst/V/vsuxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei32.v.yaml b/arch/inst/V/vsuxseg3ei32.v.yaml index fa693dce2..ee3e9934b 100644 --- a/arch/inst/V/vsuxseg3ei32.v.yaml +++ b/arch/inst/V/vsuxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei64.v.yaml b/arch/inst/V/vsuxseg3ei64.v.yaml index 9402fb997..beb4804d5 100644 --- a/arch/inst/V/vsuxseg3ei64.v.yaml +++ b/arch/inst/V/vsuxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei8.v.yaml b/arch/inst/V/vsuxseg3ei8.v.yaml index a6df38193..5715a5bb7 100644 --- a/arch/inst/V/vsuxseg3ei8.v.yaml +++ b/arch/inst/V/vsuxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei16.v.yaml b/arch/inst/V/vsuxseg4ei16.v.yaml index bf4d87142..4740814c9 100644 --- a/arch/inst/V/vsuxseg4ei16.v.yaml +++ b/arch/inst/V/vsuxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei32.v.yaml b/arch/inst/V/vsuxseg4ei32.v.yaml index c730eff6c..09b1d93ef 100644 --- a/arch/inst/V/vsuxseg4ei32.v.yaml +++ b/arch/inst/V/vsuxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei64.v.yaml b/arch/inst/V/vsuxseg4ei64.v.yaml index c263a3317..661bd38f9 100644 --- a/arch/inst/V/vsuxseg4ei64.v.yaml +++ b/arch/inst/V/vsuxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei8.v.yaml b/arch/inst/V/vsuxseg4ei8.v.yaml index 64bbffc45..d6974e55e 100644 --- a/arch/inst/V/vsuxseg4ei8.v.yaml +++ b/arch/inst/V/vsuxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei16.v.yaml b/arch/inst/V/vsuxseg5ei16.v.yaml index 6b7ac97ea..784d59746 100644 --- a/arch/inst/V/vsuxseg5ei16.v.yaml +++ b/arch/inst/V/vsuxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei32.v.yaml b/arch/inst/V/vsuxseg5ei32.v.yaml index a5afbb597..272af17c6 100644 --- a/arch/inst/V/vsuxseg5ei32.v.yaml +++ b/arch/inst/V/vsuxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei64.v.yaml b/arch/inst/V/vsuxseg5ei64.v.yaml index a4c7a1e50..8486d9474 100644 --- a/arch/inst/V/vsuxseg5ei64.v.yaml +++ b/arch/inst/V/vsuxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei8.v.yaml b/arch/inst/V/vsuxseg5ei8.v.yaml index 4e3fa113b..de77fb9d1 100644 --- a/arch/inst/V/vsuxseg5ei8.v.yaml +++ b/arch/inst/V/vsuxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei16.v.yaml b/arch/inst/V/vsuxseg6ei16.v.yaml index 480cefc65..91141cc28 100644 --- a/arch/inst/V/vsuxseg6ei16.v.yaml +++ b/arch/inst/V/vsuxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei32.v.yaml b/arch/inst/V/vsuxseg6ei32.v.yaml index f504d7402..60137b99b 100644 --- a/arch/inst/V/vsuxseg6ei32.v.yaml +++ b/arch/inst/V/vsuxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei64.v.yaml b/arch/inst/V/vsuxseg6ei64.v.yaml index 3dc2a966e..ca3498a89 100644 --- a/arch/inst/V/vsuxseg6ei64.v.yaml +++ b/arch/inst/V/vsuxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei8.v.yaml b/arch/inst/V/vsuxseg6ei8.v.yaml index 2755d986b..1603d9766 100644 --- a/arch/inst/V/vsuxseg6ei8.v.yaml +++ b/arch/inst/V/vsuxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei16.v.yaml b/arch/inst/V/vsuxseg7ei16.v.yaml index b741b04f4..d6054b94b 100644 --- a/arch/inst/V/vsuxseg7ei16.v.yaml +++ b/arch/inst/V/vsuxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei32.v.yaml b/arch/inst/V/vsuxseg7ei32.v.yaml index 49ae744ff..ec5a1165e 100644 --- a/arch/inst/V/vsuxseg7ei32.v.yaml +++ b/arch/inst/V/vsuxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei64.v.yaml b/arch/inst/V/vsuxseg7ei64.v.yaml index eb7b21ba3..93b940bfa 100644 --- a/arch/inst/V/vsuxseg7ei64.v.yaml +++ b/arch/inst/V/vsuxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei8.v.yaml b/arch/inst/V/vsuxseg7ei8.v.yaml index dd52ac3d7..4f59f1ac9 100644 --- a/arch/inst/V/vsuxseg7ei8.v.yaml +++ b/arch/inst/V/vsuxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei16.v.yaml b/arch/inst/V/vsuxseg8ei16.v.yaml index ed979fec2..bcb839cce 100644 --- a/arch/inst/V/vsuxseg8ei16.v.yaml +++ b/arch/inst/V/vsuxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei32.v.yaml b/arch/inst/V/vsuxseg8ei32.v.yaml index 5ac1dcab0..187df64d4 100644 --- a/arch/inst/V/vsuxseg8ei32.v.yaml +++ b/arch/inst/V/vsuxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei64.v.yaml b/arch/inst/V/vsuxseg8ei64.v.yaml index f7dc31b9e..6bd7ba19a 100644 --- a/arch/inst/V/vsuxseg8ei64.v.yaml +++ b/arch/inst/V/vsuxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei8.v.yaml b/arch/inst/V/vsuxseg8ei8.v.yaml index 2099cd741..fde99e61f 100644 --- a/arch/inst/V/vsuxseg8ei8.v.yaml +++ b/arch/inst/V/vsuxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vwadd.vv.yaml b/arch/inst/V/vwadd.vv.yaml index 020370730..c1e5223c2 100644 --- a/arch/inst/V/vwadd.vv.yaml +++ b/arch/inst/V/vwadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.vx.yaml b/arch/inst/V/vwadd.vx.yaml index 010532791..1c6d1ea1c 100644 --- a/arch/inst/V/vwadd.vx.yaml +++ b/arch/inst/V/vwadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.wv.yaml b/arch/inst/V/vwadd.wv.yaml index a6a851919..9480da43a 100644 --- a/arch/inst/V/vwadd.wv.yaml +++ b/arch/inst/V/vwadd.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.wx.yaml b/arch/inst/V/vwadd.wx.yaml index fd78c086a..3d7c24bf3 100644 --- a/arch/inst/V/vwadd.wx.yaml +++ b/arch/inst/V/vwadd.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.vv.yaml b/arch/inst/V/vwaddu.vv.yaml index e0e0e20ab..66235b1d7 100644 --- a/arch/inst/V/vwaddu.vv.yaml +++ b/arch/inst/V/vwaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.vx.yaml b/arch/inst/V/vwaddu.vx.yaml index 87870e44e..8764aaa6a 100644 --- a/arch/inst/V/vwaddu.vx.yaml +++ b/arch/inst/V/vwaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.wv.yaml b/arch/inst/V/vwaddu.wv.yaml index 799fd3761..4b3396bb4 100644 --- a/arch/inst/V/vwaddu.wv.yaml +++ b/arch/inst/V/vwaddu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.wx.yaml b/arch/inst/V/vwaddu.wx.yaml index 8719530b1..8d614a193 100644 --- a/arch/inst/V/vwaddu.wx.yaml +++ b/arch/inst/V/vwaddu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmacc.vv.yaml b/arch/inst/V/vwmacc.vv.yaml index 78246982d..eaee84004 100644 --- a/arch/inst/V/vwmacc.vv.yaml +++ b/arch/inst/V/vwmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmacc.vx.yaml b/arch/inst/V/vwmacc.vx.yaml index 1faf42a62..0540830fd 100644 --- a/arch/inst/V/vwmacc.vx.yaml +++ b/arch/inst/V/vwmacc.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmacc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccsu.vv.yaml b/arch/inst/V/vwmaccsu.vv.yaml index 347cc21ff..fa51d44a3 100644 --- a/arch/inst/V/vwmaccsu.vv.yaml +++ b/arch/inst/V/vwmaccsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccsu.vx.yaml b/arch/inst/V/vwmaccsu.vx.yaml index bbb92960c..7797552f0 100644 --- a/arch/inst/V/vwmaccsu.vx.yaml +++ b/arch/inst/V/vwmaccsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccu.vv.yaml b/arch/inst/V/vwmaccu.vv.yaml index 6b2d0406c..9a9a0ac2d 100644 --- a/arch/inst/V/vwmaccu.vv.yaml +++ b/arch/inst/V/vwmaccu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccu.vx.yaml b/arch/inst/V/vwmaccu.vx.yaml index 0e3537eee..70d74dc7d 100644 --- a/arch/inst/V/vwmaccu.vx.yaml +++ b/arch/inst/V/vwmaccu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccus.vx.yaml b/arch/inst/V/vwmaccus.vx.yaml index 1704aace5..afa161fa1 100644 --- a/arch/inst/V/vwmaccus.vx.yaml +++ b/arch/inst/V/vwmaccus.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccus.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmul.vv.yaml b/arch/inst/V/vwmul.vv.yaml index 88ffd777c..4c33778e7 100644 --- a/arch/inst/V/vwmul.vv.yaml +++ b/arch/inst/V/vwmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmul.vx.yaml b/arch/inst/V/vwmul.vx.yaml index 56b2fdf90..e4f7060fb 100644 --- a/arch/inst/V/vwmul.vx.yaml +++ b/arch/inst/V/vwmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulsu.vv.yaml b/arch/inst/V/vwmulsu.vv.yaml index 32a53d3af..d6c385073 100644 --- a/arch/inst/V/vwmulsu.vv.yaml +++ b/arch/inst/V/vwmulsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulsu.vx.yaml b/arch/inst/V/vwmulsu.vx.yaml index 6d8b53e9b..86b26cc94 100644 --- a/arch/inst/V/vwmulsu.vx.yaml +++ b/arch/inst/V/vwmulsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulu.vv.yaml b/arch/inst/V/vwmulu.vv.yaml index 8686115d5..4ec2bdfdc 100644 --- a/arch/inst/V/vwmulu.vv.yaml +++ b/arch/inst/V/vwmulu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulu.vx.yaml b/arch/inst/V/vwmulu.vx.yaml index 8433bb622..5b71c1ed9 100644 --- a/arch/inst/V/vwmulu.vx.yaml +++ b/arch/inst/V/vwmulu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwredsum.vs.yaml b/arch/inst/V/vwredsum.vs.yaml index 0032bcfd6..492d0e7a6 100644 --- a/arch/inst/V/vwredsum.vs.yaml +++ b/arch/inst/V/vwredsum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwredsum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwredsumu.vs.yaml b/arch/inst/V/vwredsumu.vs.yaml index 700f88b76..6b9bc995c 100644 --- a/arch/inst/V/vwredsumu.vs.yaml +++ b/arch/inst/V/vwredsumu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwredsumu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.vv.yaml b/arch/inst/V/vwsub.vv.yaml index 14530949a..ebeb4d80d 100644 --- a/arch/inst/V/vwsub.vv.yaml +++ b/arch/inst/V/vwsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.vx.yaml b/arch/inst/V/vwsub.vx.yaml index 66a3c69f0..0998ef195 100644 --- a/arch/inst/V/vwsub.vx.yaml +++ b/arch/inst/V/vwsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.wv.yaml b/arch/inst/V/vwsub.wv.yaml index 8af49ee0a..644ea2292 100644 --- a/arch/inst/V/vwsub.wv.yaml +++ b/arch/inst/V/vwsub.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.wx.yaml b/arch/inst/V/vwsub.wx.yaml index a91894f1b..e7a6707cd 100644 --- a/arch/inst/V/vwsub.wx.yaml +++ b/arch/inst/V/vwsub.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.vv.yaml b/arch/inst/V/vwsubu.vv.yaml index 2b05bf512..1fec77e82 100644 --- a/arch/inst/V/vwsubu.vv.yaml +++ b/arch/inst/V/vwsubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.vx.yaml b/arch/inst/V/vwsubu.vx.yaml index 0838d847b..dbdb5dd94 100644 --- a/arch/inst/V/vwsubu.vx.yaml +++ b/arch/inst/V/vwsubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.wv.yaml b/arch/inst/V/vwsubu.wv.yaml index dec2d0698..a5f210c2c 100644 --- a/arch/inst/V/vwsubu.wv.yaml +++ b/arch/inst/V/vwsubu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.wx.yaml b/arch/inst/V/vwsubu.wx.yaml index 84243dc45..d881e60a6 100644 --- a/arch/inst/V/vwsubu.wx.yaml +++ b/arch/inst/V/vwsubu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vxor.vi.yaml b/arch/inst/V/vxor.vi.yaml index 40c557070..4c9ba6b85 100644 --- a/arch/inst/V/vxor.vi.yaml +++ b/arch/inst/V/vxor.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vxor.vv.yaml b/arch/inst/V/vxor.vv.yaml index 9e3067f6b..dfab9e367 100644 --- a/arch/inst/V/vxor.vv.yaml +++ b/arch/inst/V/vxor.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vxor.vx.yaml b/arch/inst/V/vxor.vx.yaml index 8ed77e0db..cc3f84366 100644 --- a/arch/inst/V/vxor.vx.yaml +++ b/arch/inst/V/vxor.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf2.yaml b/arch/inst/V/vzext.vf2.yaml index c978587ca..0f0409f7a 100644 --- a/arch/inst/V/vzext.vf2.yaml +++ b/arch/inst/V/vzext.vf2.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00110010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf4.yaml b/arch/inst/V/vzext.vf4.yaml index a39b7b881..8bb5470ea 100644 --- a/arch/inst/V/vzext.vf4.yaml +++ b/arch/inst/V/vzext.vf4.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00100010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf8.yaml b/arch/inst/V/vzext.vf8.yaml index 4fce98f03..9afef2eed 100644 --- a/arch/inst/V/vzext.vf8.yaml +++ b/arch/inst/V/vzext.vf8.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/Zabha/amoadd.b.yaml b/arch/inst/Zabha/amoadd.b.yaml index a88fe6b2c..f427053e8 100644 --- a/arch/inst/Zabha/amoadd.b.yaml +++ b/arch/inst/Zabha/amoadd.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoadd.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoadd.h.yaml b/arch/inst/Zabha/amoadd.h.yaml index 5b96e7779..72b6f0a07 100644 --- a/arch/inst/Zabha/amoadd.h.yaml +++ b/arch/inst/Zabha/amoadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoand.b.yaml b/arch/inst/Zabha/amoand.b.yaml index a8f3e6fc2..52509d451 100644 --- a/arch/inst/Zabha/amoand.b.yaml +++ b/arch/inst/Zabha/amoand.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoand.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoand.h.yaml b/arch/inst/Zabha/amoand.h.yaml index 9be12f711..21e7fa04b 100644 --- a/arch/inst/Zabha/amoand.h.yaml +++ b/arch/inst/Zabha/amoand.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoand.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amocas.b.yaml b/arch/inst/Zabha/amocas.b.yaml index 58be77749..b7b4ef004 100644 --- a/arch/inst/Zabha/amocas.b.yaml +++ b/arch/inst/Zabha/amocas.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zabha/amocas.h.yaml b/arch/inst/Zabha/amocas.h.yaml index 5ea2e2b72..0a17bfb89 100644 --- a/arch/inst/Zabha/amocas.h.yaml +++ b/arch/inst/Zabha/amocas.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zabha/amomax.b.yaml b/arch/inst/Zabha/amomax.b.yaml index 2ca5f2859..00c77cf2c 100644 --- a/arch/inst/Zabha/amomax.b.yaml +++ b/arch/inst/Zabha/amomax.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomax.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomax.h.yaml b/arch/inst/Zabha/amomax.h.yaml index b8ae26f1a..f3f02354e 100644 --- a/arch/inst/Zabha/amomax.h.yaml +++ b/arch/inst/Zabha/amomax.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomax.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomaxu.b.yaml b/arch/inst/Zabha/amomaxu.b.yaml index 8fad8f562..cb675e92e 100644 --- a/arch/inst/Zabha/amomaxu.b.yaml +++ b/arch/inst/Zabha/amomaxu.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomaxu.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomaxu.h.yaml b/arch/inst/Zabha/amomaxu.h.yaml index 9952ef356..f65f69222 100644 --- a/arch/inst/Zabha/amomaxu.h.yaml +++ b/arch/inst/Zabha/amomaxu.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomaxu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomin.b.yaml b/arch/inst/Zabha/amomin.b.yaml index 58f898f01..5d54cf154 100644 --- a/arch/inst/Zabha/amomin.b.yaml +++ b/arch/inst/Zabha/amomin.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomin.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomin.h.yaml b/arch/inst/Zabha/amomin.h.yaml index 7cb010ba0..d00310630 100644 --- a/arch/inst/Zabha/amomin.h.yaml +++ b/arch/inst/Zabha/amomin.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomin.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amominu.b.yaml b/arch/inst/Zabha/amominu.b.yaml index aaf8204d5..f781b73cf 100644 --- a/arch/inst/Zabha/amominu.b.yaml +++ b/arch/inst/Zabha/amominu.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amominu.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amominu.h.yaml b/arch/inst/Zabha/amominu.h.yaml index b805456a5..75437ea18 100644 --- a/arch/inst/Zabha/amominu.h.yaml +++ b/arch/inst/Zabha/amominu.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amominu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoor.b.yaml b/arch/inst/Zabha/amoor.b.yaml index c339a8c1e..32a155296 100644 --- a/arch/inst/Zabha/amoor.b.yaml +++ b/arch/inst/Zabha/amoor.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoor.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoor.h.yaml b/arch/inst/Zabha/amoor.h.yaml index 5c637e671..4ef72909e 100644 --- a/arch/inst/Zabha/amoor.h.yaml +++ b/arch/inst/Zabha/amoor.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoor.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoswap.b.yaml b/arch/inst/Zabha/amoswap.b.yaml index e3370fa27..a17173f58 100644 --- a/arch/inst/Zabha/amoswap.b.yaml +++ b/arch/inst/Zabha/amoswap.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoswap.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00001------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoswap.h.yaml b/arch/inst/Zabha/amoswap.h.yaml index 81ad25a56..47f74a8b8 100644 --- a/arch/inst/Zabha/amoswap.h.yaml +++ b/arch/inst/Zabha/amoswap.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoswap.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00001------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoxor.b.yaml b/arch/inst/Zabha/amoxor.b.yaml index 6cc6b9408..45ec3ff34 100644 --- a/arch/inst/Zabha/amoxor.b.yaml +++ b/arch/inst/Zabha/amoxor.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoxor.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoxor.h.yaml b/arch/inst/Zabha/amoxor.h.yaml index a03c9def1..e3d8799a7 100644 --- a/arch/inst/Zabha/amoxor.h.yaml +++ b/arch/inst/Zabha/amoxor.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoxor.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zacas/amocas.d.yaml b/arch/inst/Zacas/amocas.d.yaml index d7adbc8fd..3a73672d2 100644 --- a/arch/inst/Zacas/amocas.d.yaml +++ b/arch/inst/Zacas/amocas.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------011-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zacas/amocas.q.yaml b/arch/inst/Zacas/amocas.q.yaml index 7c375ab20..1e5a3b8fc 100644 --- a/arch/inst/Zacas/amocas.q.yaml +++ b/arch/inst/Zacas/amocas.q.yaml @@ -5,23 +5,23 @@ kind: instruction name: amocas.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas base: 64 assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------100-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zacas/amocas.w.yaml b/arch/inst/Zacas/amocas.w.yaml index 5cb79b0d6..0f4d9fd2a 100644 --- a/arch/inst/Zacas/amocas.w.yaml +++ b/arch/inst/Zacas/amocas.w.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------010-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zalasr/lb.aq.yaml b/arch/inst/Zalasr/lb.aq.yaml index c77cff6d4..8c9ce4603 100644 --- a/arch/inst/Zalasr/lb.aq.yaml +++ b/arch/inst/Zalasr/lb.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lb.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----000-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/ld.aq.yaml b/arch/inst/Zalasr/ld.aq.yaml index 227d21844..ea3e33537 100644 --- a/arch/inst/Zalasr/ld.aq.yaml +++ b/arch/inst/Zalasr/ld.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: ld.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----011-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/lh.aq.yaml b/arch/inst/Zalasr/lh.aq.yaml index 34542cece..3811cc306 100644 --- a/arch/inst/Zalasr/lh.aq.yaml +++ b/arch/inst/Zalasr/lh.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lh.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----001-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/lw.aq.yaml b/arch/inst/Zalasr/lw.aq.yaml index b0acbfb8d..706065daf 100644 --- a/arch/inst/Zalasr/lw.aq.yaml +++ b/arch/inst/Zalasr/lw.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lw.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----010-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sb.rl.yaml b/arch/inst/Zalasr/sb.rl.yaml index 4f2a76c0b..038a192d1 100644 --- a/arch/inst/Zalasr/sb.rl.yaml +++ b/arch/inst/Zalasr/sb.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sb.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------000000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sd.rl.yaml b/arch/inst/Zalasr/sd.rl.yaml index ea8d44954..e7ba1369e 100644 --- a/arch/inst/Zalasr/sd.rl.yaml +++ b/arch/inst/Zalasr/sd.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sd.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------011000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sh.rl.yaml b/arch/inst/Zalasr/sh.rl.yaml index 626501309..a45c0f328 100644 --- a/arch/inst/Zalasr/sh.rl.yaml +++ b/arch/inst/Zalasr/sh.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sh.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------001000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sw.rl.yaml b/arch/inst/Zalasr/sw.rl.yaml index f93fa6709..a1f2176f6 100644 --- a/arch/inst/Zalasr/sw.rl.yaml +++ b/arch/inst/Zalasr/sw.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sw.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------010000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zawrs/wrs.nto.yaml b/arch/inst/Zawrs/wrs.nto.yaml index 8ca9e6479..e171e412e 100644 --- a/arch/inst/Zawrs/wrs.nto.yaml +++ b/arch/inst/Zawrs/wrs.nto.yaml @@ -5,11 +5,11 @@ kind: instruction name: wrs.nto long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zawrs assembly: wrs_nto encoding: - match: '00000000110100000000000001110011' + match: "00000000110100000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Zawrs/wrs.sto.yaml b/arch/inst/Zawrs/wrs.sto.yaml index 7052d117c..835dd8f3c 100644 --- a/arch/inst/Zawrs/wrs.sto.yaml +++ b/arch/inst/Zawrs/wrs.sto.yaml @@ -5,11 +5,11 @@ kind: instruction name: wrs.sto long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zawrs assembly: wrs_sto encoding: - match: '00000001110100000000000001110011' + match: "00000001110100000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Zbkb/brev8.yaml b/arch/inst/Zbkb/brev8.yaml index 4993648fc..2f3cea1df 100644 --- a/arch/inst/Zbkb/brev8.yaml +++ b/arch/inst/Zbkb/brev8.yaml @@ -5,17 +5,17 @@ kind: instruction name: brev8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 011010000111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkb/unzip.yaml b/arch/inst/Zbkb/unzip.yaml index 64bff932a..ee1346c11 100644 --- a/arch/inst/Zbkb/unzip.yaml +++ b/arch/inst/Zbkb/unzip.yaml @@ -5,17 +5,17 @@ kind: instruction name: unzip long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 000010001111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkb/zip.yaml b/arch/inst/Zbkb/zip.yaml index b5a3b2733..17f309379 100644 --- a/arch/inst/Zbkb/zip.yaml +++ b/arch/inst/Zbkb/zip.yaml @@ -5,17 +5,17 @@ kind: instruction name: zip long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 000010001111-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkx/xperm4.yaml b/arch/inst/Zbkx/xperm4.yaml index 0e1c05fb7..1ff88af98 100644 --- a/arch/inst/Zbkx/xperm4.yaml +++ b/arch/inst/Zbkx/xperm4.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkx, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0010100----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkx/xperm8.yaml b/arch/inst/Zbkx/xperm8.yaml index a0afff2de..3968dc5f9 100644 --- a/arch/inst/Zbkx/xperm8.yaml +++ b/arch/inst/Zbkx/xperm8.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkx, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0010100----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/gorci.yaml b/arch/inst/Zbp/gorci.yaml index 1b7037d2c..c74ab2a88 100644 --- a/arch/inst/Zbp/gorci.yaml +++ b/arch/inst/Zbp/gorci.yaml @@ -5,19 +5,19 @@ kind: instruction name: gorci long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 001010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/grevi.yaml b/arch/inst/Zbp/grevi.yaml index 1fa748351..2fb9fbac8 100644 --- a/arch/inst/Zbp/grevi.yaml +++ b/arch/inst/Zbp/grevi.yaml @@ -5,19 +5,19 @@ kind: instruction name: grevi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 011010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/shfli.yaml b/arch/inst/Zbp/shfli.yaml index c903c6ae8..ec21d0f74 100644 --- a/arch/inst/Zbp/shfli.yaml +++ b/arch/inst/Zbp/shfli.yaml @@ -5,19 +5,19 @@ kind: instruction name: shfli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 0000100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/unshfli.yaml b/arch/inst/Zbp/unshfli.yaml index 0f49c5324..7eab8ae10 100644 --- a/arch/inst/Zbp/unshfli.yaml +++ b/arch/inst/Zbp/unshfli.yaml @@ -5,19 +5,19 @@ kind: instruction name: unshfli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 0000100----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/xperm16.yaml b/arch/inst/Zbp/xperm16.yaml index ad079aadb..2efc25548 100644 --- a/arch/inst/Zbp/xperm16.yaml +++ b/arch/inst/Zbp/xperm16.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm16 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, xs2 encoding: match: 0010100----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/xperm32.yaml b/arch/inst/Zbp/xperm32.yaml index 796b19071..9832c3aa0 100644 --- a/arch/inst/Zbp/xperm32.yaml +++ b/arch/inst/Zbp/xperm32.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm32 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, xs2 encoding: match: 0010100----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lbu.yaml b/arch/inst/Zcb/c.lbu.yaml index 0c0a4a0a9..e02c32857 100644 --- a/arch/inst/Zcb/c.lbu.yaml +++ b/arch/inst/Zcb/c.lbu.yaml @@ -10,18 +10,18 @@ description: | It expands to `lbu` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100000--------00 variables: - - name: imm - location: 5|6 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|6 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lh.yaml b/arch/inst/Zcb/c.lh.yaml index 2c29ba108..a96c92ef8 100644 --- a/arch/inst/Zcb/c.lh.yaml +++ b/arch/inst/Zcb/c.lh.yaml @@ -10,19 +10,19 @@ description: | It expands to `lh` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100001---1----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lhu.yaml b/arch/inst/Zcb/c.lhu.yaml index 1d71ead41..6d6e7d819 100644 --- a/arch/inst/Zcb/c.lhu.yaml +++ b/arch/inst/Zcb/c.lhu.yaml @@ -10,19 +10,19 @@ description: | It expands to `lhu` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100001---0----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.mul.yaml b/arch/inst/Zcb/c.mul.yaml index f27561dbb..f70a88712 100644 --- a/arch/inst/Zcb/c.mul.yaml +++ b/arch/inst/Zcb/c.mul.yaml @@ -9,16 +9,16 @@ description: | definedBy: allOf: - - Zcb - - Zmmul + - Zcb + - Zmmul assembly: xd, xs2 encoding: match: 100111---10---01 variables: - - name: rd - location: 9-7 - - name: rs2 - location: 4-2 + - name: rd + location: 9-7 + - name: rs2 + location: 4-2 access: s: always u: always diff --git a/arch/inst/Zcb/c.not.yaml b/arch/inst/Zcb/c.not.yaml index 8612ca93e..8841c116a 100644 --- a/arch/inst/Zcb/c.not.yaml +++ b/arch/inst/Zcb/c.not.yaml @@ -10,14 +10,14 @@ description: | definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd encoding: match: 100111---1110101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sb.yaml b/arch/inst/Zcb/c.sb.yaml index f4dcfa76c..18ef85732 100644 --- a/arch/inst/Zcb/c.sb.yaml +++ b/arch/inst/Zcb/c.sb.yaml @@ -10,18 +10,18 @@ description: | It expands to `sb` `rs2, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xs2, imm(xs1) encoding: match: 100010--------00 variables: - - name: imm - location: 5|6 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|6 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sext.b.yaml b/arch/inst/Zcb/c.sext.b.yaml index 0bd3c24de..9dd0dae51 100644 --- a/arch/inst/Zcb/c.sext.b.yaml +++ b/arch/inst/Zcb/c.sext.b.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1100101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sext.h.yaml b/arch/inst/Zcb/c.sext.h.yaml index 8f8061605..734cb8bd3 100644 --- a/arch/inst/Zcb/c.sext.h.yaml +++ b/arch/inst/Zcb/c.sext.h.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1101101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sh.yaml b/arch/inst/Zcb/c.sh.yaml index 39d357048..f4e34aef8 100644 --- a/arch/inst/Zcb/c.sh.yaml +++ b/arch/inst/Zcb/c.sh.yaml @@ -10,19 +10,19 @@ description: | It expands to `sh` `rs2, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xs2, imm(xs1) encoding: match: 100011---0----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.b.yaml b/arch/inst/Zcb/c.zext.b.yaml index 0049b6229..f048a52c5 100644 --- a/arch/inst/Zcb/c.zext.b.yaml +++ b/arch/inst/Zcb/c.zext.b.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1100001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.h.yaml b/arch/inst/Zcb/c.zext.h.yaml index aeff66ef0..57fb520e6 100644 --- a/arch/inst/Zcb/c.zext.h.yaml +++ b/arch/inst/Zcb/c.zext.h.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1101001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.w.yaml b/arch/inst/Zcb/c.zext.w.yaml index ea226cd04..cd6e4526e 100644 --- a/arch/inst/Zcb/c.zext.w.yaml +++ b/arch/inst/Zcb/c.zext.w.yaml @@ -10,15 +10,15 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd base: 64 encoding: match: 100111---1110001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml index 50e616b59..1b738d2eb 100644 --- a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml +++ b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.bf16.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfbfmin assembly: xd, xs1, rm encoding: match: 010001001000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml index c6d2dcb9c..147e56587 100644 --- a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml +++ b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.bf16 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfbfmin assembly: xd, xs1, rm encoding: match: 010000000110-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fadd.h.yaml b/arch/inst/Zfh/fadd.h.yaml index 8ff9819fe..41aee2f97 100644 --- a/arch/inst/Zfh/fadd.h.yaml +++ b/arch/inst/Zfh/fadd.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0000010------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fclass.h.yaml b/arch/inst/Zfh/fclass.h.yaml index dff44fbda..2d14f02fb 100644 --- a/arch/inst/Zfh/fclass.h.yaml +++ b/arch/inst/Zfh/fclass.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1 encoding: match: 111001000000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.d.h.yaml b/arch/inst/Zfh/fcvt.d.h.yaml index 5f309dcb2..dc02cc5a6 100644 --- a/arch/inst/Zfh/fcvt.d.h.yaml +++ b/arch/inst/Zfh/fcvt.d.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.d.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfh] assembly: xd, xs1, rm encoding: match: 010000100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.d.yaml b/arch/inst/Zfh/fcvt.h.d.yaml index 83d8d53ef..82db22c0e 100644 --- a/arch/inst/Zfh/fcvt.h.d.yaml +++ b/arch/inst/Zfh/fcvt.h.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.h.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfh] assembly: xd, xs1, rm encoding: match: 010001000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.l.yaml b/arch/inst/Zfh/fcvt.h.l.yaml index a91e39fe6..30321a088 100644 --- a/arch/inst/Zfh/fcvt.h.l.yaml +++ b/arch/inst/Zfh/fcvt.h.l.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.lu.yaml b/arch/inst/Zfh/fcvt.h.lu.yaml index 8bca31838..62169c912 100644 --- a/arch/inst/Zfh/fcvt.h.lu.yaml +++ b/arch/inst/Zfh/fcvt.h.lu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.s.yaml b/arch/inst/Zfh/fcvt.h.s.yaml index 65f87f4e9..8526b9e4a 100644 --- a/arch/inst/Zfh/fcvt.h.s.yaml +++ b/arch/inst/Zfh/fcvt.h.s.yaml @@ -19,12 +19,12 @@ description: | encoding: match: 010001000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -65,8 +65,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/Zfh/fcvt.h.w.yaml b/arch/inst/Zfh/fcvt.h.w.yaml index 435226b96..599021ca2 100644 --- a/arch/inst/Zfh/fcvt.h.w.yaml +++ b/arch/inst/Zfh/fcvt.h.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.wu.yaml b/arch/inst/Zfh/fcvt.h.wu.yaml index d1e3e0793..d4b3c68ff 100644 --- a/arch/inst/Zfh/fcvt.h.wu.yaml +++ b/arch/inst/Zfh/fcvt.h.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.l.h.yaml b/arch/inst/Zfh/fcvt.l.h.yaml index f024f191d..835ee0b19 100644 --- a/arch/inst/Zfh/fcvt.l.h.yaml +++ b/arch/inst/Zfh/fcvt.l.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.l.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.lu.h.yaml b/arch/inst/Zfh/fcvt.lu.h.yaml index 24adfb47a..ca97bf3ec 100644 --- a/arch/inst/Zfh/fcvt.lu.h.yaml +++ b/arch/inst/Zfh/fcvt.lu.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.lu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.s.h.yaml b/arch/inst/Zfh/fcvt.s.h.yaml index dc69ea9fb..eac044ed3 100644 --- a/arch/inst/Zfh/fcvt.s.h.yaml +++ b/arch/inst/Zfh/fcvt.s.h.yaml @@ -16,12 +16,12 @@ description: | encoding: match: 010000000010-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -62,8 +62,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/Zfh/fcvt.w.h.yaml b/arch/inst/Zfh/fcvt.w.h.yaml index 03c31e5e9..489ccaaf4 100644 --- a/arch/inst/Zfh/fcvt.w.h.yaml +++ b/arch/inst/Zfh/fcvt.w.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.wu.h.yaml b/arch/inst/Zfh/fcvt.wu.h.yaml index 2020304a6..17358a6de 100644 --- a/arch/inst/Zfh/fcvt.wu.h.yaml +++ b/arch/inst/Zfh/fcvt.wu.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fdiv.h.yaml b/arch/inst/Zfh/fdiv.h.yaml index ae879ef05..330c795df 100644 --- a/arch/inst/Zfh/fdiv.h.yaml +++ b/arch/inst/Zfh/fdiv.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0001110------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/feq.h.yaml b/arch/inst/Zfh/feq.h.yaml index a2ca9119e..a33e7bb19 100644 --- a/arch/inst/Zfh/feq.h.yaml +++ b/arch/inst/Zfh/feq.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fle.h.yaml b/arch/inst/Zfh/fle.h.yaml index 0328f9f52..5860f509f 100644 --- a/arch/inst/Zfh/fle.h.yaml +++ b/arch/inst/Zfh/fle.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fleq.h.yaml b/arch/inst/Zfh/fleq.h.yaml index 7a7a35eda..deb371268 100644 --- a/arch/inst/Zfh/fleq.h.yaml +++ b/arch/inst/Zfh/fleq.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 1010010----------100-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/flh.yaml b/arch/inst/Zfh/flh.yaml index 76b99366e..7810342f0 100644 --- a/arch/inst/Zfh/flh.yaml +++ b/arch/inst/Zfh/flh.yaml @@ -17,12 +17,12 @@ assembly: fd, imm(xs1) encoding: match: -----------------001-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -39,8 +39,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zfh/fli.h.yaml b/arch/inst/Zfh/fli.h.yaml index fb22d8010..1a73648c9 100644 --- a/arch/inst/Zfh/fli.h.yaml +++ b/arch/inst/Zfh/fli.h.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1 encoding: match: 111101000001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/flt.h.yaml b/arch/inst/Zfh/flt.h.yaml index 6e90a95ca..aba1e1850 100644 --- a/arch/inst/Zfh/flt.h.yaml +++ b/arch/inst/Zfh/flt.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fltq.h.yaml b/arch/inst/Zfh/fltq.h.yaml index 7b3ce83cb..852f53de1 100644 --- a/arch/inst/Zfh/fltq.h.yaml +++ b/arch/inst/Zfh/fltq.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 1010010----------101-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmadd.h.yaml b/arch/inst/Zfh/fmadd.h.yaml index 71971aac5..b56287fed 100644 --- a/arch/inst/Zfh/fmadd.h.yaml +++ b/arch/inst/Zfh/fmadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1000011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmax.h.yaml b/arch/inst/Zfh/fmax.h.yaml index c4d132a5b..98a6d1058 100644 --- a/arch/inst/Zfh/fmax.h.yaml +++ b/arch/inst/Zfh/fmax.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010110----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmaxm.h.yaml b/arch/inst/Zfh/fmaxm.h.yaml index d75b0d325..c0939a70e 100644 --- a/arch/inst/Zfh/fmaxm.h.yaml +++ b/arch/inst/Zfh/fmaxm.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 0010110----------011-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmin.h.yaml b/arch/inst/Zfh/fmin.h.yaml index 84699940c..ef25d24a6 100644 --- a/arch/inst/Zfh/fmin.h.yaml +++ b/arch/inst/Zfh/fmin.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010110----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fminm.h.yaml b/arch/inst/Zfh/fminm.h.yaml index 17ed7b705..72a365d06 100644 --- a/arch/inst/Zfh/fminm.h.yaml +++ b/arch/inst/Zfh/fminm.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 0010110----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmsub.h.yaml b/arch/inst/Zfh/fmsub.h.yaml index 9b17b7d82..6df211e7b 100644 --- a/arch/inst/Zfh/fmsub.h.yaml +++ b/arch/inst/Zfh/fmsub.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1000111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmul.h.yaml b/arch/inst/Zfh/fmul.h.yaml index b6185aa0c..f2291a64d 100644 --- a/arch/inst/Zfh/fmul.h.yaml +++ b/arch/inst/Zfh/fmul.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0001010------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmv.h.x.yaml b/arch/inst/Zfh/fmv.h.x.yaml index e6c8e7648..b179c5df8 100644 --- a/arch/inst/Zfh/fmv.h.x.yaml +++ b/arch/inst/Zfh/fmv.h.x.yaml @@ -14,10 +14,10 @@ assembly: fd, xs1 encoding: match: 111101000000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -32,7 +32,6 @@ operation(): | mark_f_state_dirty(); - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/Zfh/fmv.x.h.yaml b/arch/inst/Zfh/fmv.x.h.yaml index ecd308564..e0afcbcaa 100644 --- a/arch/inst/Zfh/fmv.x.h.yaml +++ b/arch/inst/Zfh/fmv.x.h.yaml @@ -8,21 +8,21 @@ definedBy: anyOf: [Zfh, Zfhmin] assembly: rd, fs1 description: | - Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008 - encoding to the lower 16 bits of integer register rd. + Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008 + encoding to the lower 16 bits of integer register rd. - The bits are not modified in the transfer, and in particular, the payloads of non-canonical - NaNs are preserved. + The bits are not modified in the transfer, and in particular, the payloads of non-canonical + NaNs are preserved. - The highest XLEN-16 bits of the destination register are filled with copies of the - floating-point number's sign bit. + The highest XLEN-16 bits of the destination register are filled with copies of the + floating-point number's sign bit. encoding: match: 111001000000-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = sext(f[fs1][15:0], 16); - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/Zfh/fnmadd.h.yaml b/arch/inst/Zfh/fnmadd.h.yaml index 61b3efbcd..88bdb2feb 100644 --- a/arch/inst/Zfh/fnmadd.h.yaml +++ b/arch/inst/Zfh/fnmadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1001111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fnmsub.h.yaml b/arch/inst/Zfh/fnmsub.h.yaml index 1f59bda40..15be753b7 100644 --- a/arch/inst/Zfh/fnmsub.h.yaml +++ b/arch/inst/Zfh/fnmsub.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1001011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fround.h.yaml b/arch/inst/Zfh/fround.h.yaml index 027675715..0cea38f95 100644 --- a/arch/inst/Zfh/fround.h.yaml +++ b/arch/inst/Zfh/fround.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, rm encoding: match: 010001000100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/froundnx.h.yaml b/arch/inst/Zfh/froundnx.h.yaml index a2477a504..10babc702 100644 --- a/arch/inst/Zfh/froundnx.h.yaml +++ b/arch/inst/Zfh/froundnx.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, rm encoding: match: 010001000101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnj.h.yaml b/arch/inst/Zfh/fsgnj.h.yaml index a3a42471d..f43c6e6ee 100644 --- a/arch/inst/Zfh/fsgnj.h.yaml +++ b/arch/inst/Zfh/fsgnj.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnjn.h.yaml b/arch/inst/Zfh/fsgnjn.h.yaml index b6454c376..2a88a2731 100644 --- a/arch/inst/Zfh/fsgnjn.h.yaml +++ b/arch/inst/Zfh/fsgnjn.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnjx.h.yaml b/arch/inst/Zfh/fsgnjx.h.yaml index 8b30873bf..b16460eff 100644 --- a/arch/inst/Zfh/fsgnjx.h.yaml +++ b/arch/inst/Zfh/fsgnjx.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsh.yaml b/arch/inst/Zfh/fsh.yaml index 6edc5d18f..40cc00979 100644 --- a/arch/inst/Zfh/fsh.yaml +++ b/arch/inst/Zfh/fsh.yaml @@ -20,12 +20,12 @@ assembly: fs2, imm(xs1) encoding: match: -----------------001-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: rs1 - location: 19-15 - - name: fs2 - location: 24-20 + - name: imm + location: 31-25|11-7 + - name: rs1 + location: 19-15 + - name: fs2 + location: 24-20 access: s: always u: always @@ -40,8 +40,6 @@ operation(): | write_memory<16>(virtual_address, hp_value, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zfh/fsqrt.h.yaml b/arch/inst/Zfh/fsqrt.h.yaml index 61d70bfc8..d869de24b 100644 --- a/arch/inst/Zfh/fsqrt.h.yaml +++ b/arch/inst/Zfh/fsqrt.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 010111000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsub.h.yaml b/arch/inst/Zfh/fsub.h.yaml index a280c6fa5..185a4ba75 100644 --- a/arch/inst/Zfh/fsub.h.yaml +++ b/arch/inst/Zfh/fsub.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0000110------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicbom/cbo.clean.yaml b/arch/inst/Zicbom/cbo.clean.yaml index 04c8461d7..6cc03f317 100644 --- a/arch/inst/Zicbom/cbo.clean.yaml +++ b/arch/inst/Zicbom/cbo.clean.yaml @@ -40,8 +40,8 @@ assembly: "TODO" encoding: match: 000000000001-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -65,6 +65,7 @@ access_detail: | ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== + # operation(): | # let cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); diff --git a/arch/inst/Zicbom/cbo.flush.yaml b/arch/inst/Zicbom/cbo.flush.yaml index 068a2d238..d84c793c2 100644 --- a/arch/inst/Zicbom/cbo.flush.yaml +++ b/arch/inst/Zicbom/cbo.flush.yaml @@ -33,8 +33,8 @@ assembly: "TODO" encoding: match: 000000000010-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -58,6 +58,7 @@ access_detail: | ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== + # operation(): | # XReg cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); # Boolean has_fault?; diff --git a/arch/inst/Zicbom/cbo.inval.yaml b/arch/inst/Zicbom/cbo.inval.yaml index f0d1d9ac8..ee9ca695b 100644 --- a/arch/inst/Zicbom/cbo.inval.yaml +++ b/arch/inst/Zicbom/cbo.inval.yaml @@ -72,8 +72,8 @@ assembly: "TODO" encoding: match: 000000000000-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -101,6 +101,7 @@ access_detail: | ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 01/11 ! 01/11 ! 01/11 ! executes ! executes ! executes ! executes !=== + # operation(): | # let cache_block_address = X[RS1] & ~(CACHE_BLOCK_SIZE-1); diff --git a/arch/inst/Zicboz/cbo.zero.yaml b/arch/inst/Zicboz/cbo.zero.yaml index 8457260bd..828f51eef 100644 --- a/arch/inst/Zicboz/cbo.zero.yaml +++ b/arch/inst/Zicboz/cbo.zero.yaml @@ -35,8 +35,8 @@ assembly: "TODO" encoding: match: 000000000100-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes diff --git a/arch/inst/Zicfilp/lpad.yaml b/arch/inst/Zicfilp/lpad.yaml index d06692598..603edc4dc 100644 --- a/arch/inst/Zicfilp/lpad.yaml +++ b/arch/inst/Zicfilp/lpad.yaml @@ -5,15 +5,15 @@ kind: instruction name: lpad long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfilp assembly: imm encoding: match: --------------------000000010111 variables: - - name: imm - location: 31-12 - left_shift: 12 + - name: imm + location: 31-12 + left_shift: 12 access: s: always u: always diff --git a/arch/inst/Zicfiss/ssamoswap.d.yaml b/arch/inst/Zicfiss/ssamoswap.d.yaml index 6c6018c08..ddbaddcf1 100644 --- a/arch/inst/Zicfiss/ssamoswap.d.yaml +++ b/arch/inst/Zicfiss/ssamoswap.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: ssamoswap.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd, xs1, xs2, aq, rl encoding: match: 01001------------011-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicfiss/ssamoswap.w.yaml b/arch/inst/Zicfiss/ssamoswap.w.yaml index df5c208ce..0db69e3e2 100644 --- a/arch/inst/Zicfiss/ssamoswap.w.yaml +++ b/arch/inst/Zicfiss/ssamoswap.w.yaml @@ -5,22 +5,22 @@ kind: instruction name: ssamoswap.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd, xs1, xs2, aq, rl encoding: match: 01001------------010-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicfiss/sspopchk.x1.yaml b/arch/inst/Zicfiss/sspopchk.x1.yaml index f81089bca..c30f48583 100644 --- a/arch/inst/Zicfiss/sspopchk.x1.yaml +++ b/arch/inst/Zicfiss/sspopchk.x1.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspopchk.x1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspopchk_x1 encoding: - match: '11001101110000001100000001110011' + match: "11001101110000001100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspopchk.x5.yaml b/arch/inst/Zicfiss/sspopchk.x5.yaml index 9fc5f4bfe..710484716 100644 --- a/arch/inst/Zicfiss/sspopchk.x5.yaml +++ b/arch/inst/Zicfiss/sspopchk.x5.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspopchk.x5 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspopchk_x5 encoding: - match: '11001101110000101100000001110011' + match: "11001101110000101100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspush.x1.yaml b/arch/inst/Zicfiss/sspush.x1.yaml index bb4361007..c9f3f9515 100644 --- a/arch/inst/Zicfiss/sspush.x1.yaml +++ b/arch/inst/Zicfiss/sspush.x1.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspush.x1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspush_x1 encoding: - match: '11001110000100000100000001110011' + match: "11001110000100000100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspush.x5.yaml b/arch/inst/Zicfiss/sspush.x5.yaml index d2c6e13c0..41d6d52fc 100644 --- a/arch/inst/Zicfiss/sspush.x5.yaml +++ b/arch/inst/Zicfiss/sspush.x5.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspush.x5 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspush_x5 encoding: - match: '11001110010100000100000001110011' + match: "11001110010100000100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/ssrdp.yaml b/arch/inst/Zicfiss/ssrdp.yaml index 4204bbe1f..b8efb52ab 100644 --- a/arch/inst/Zicfiss/ssrdp.yaml +++ b/arch/inst/Zicfiss/ssrdp.yaml @@ -5,15 +5,15 @@ kind: instruction name: ssrdp long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd encoding: match: 11001101110000000100-----1110011 variables: - - name: rd - location: 11-7 - not: 0 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml index 539e7e422..63e65aa53 100644 --- a/arch/inst/Zicond/czero.eqz.yaml +++ b/arch/inst/Zicond/czero.eqz.yaml @@ -5,18 +5,18 @@ kind: instruction name: czero.eqz long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicond assembly: xd, xs1, xs2 encoding: match: 0000111----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let value = X(rs1); diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml index 5dc0a2102..f3824848a 100644 --- a/arch/inst/Zicond/czero.nez.yaml +++ b/arch/inst/Zicond/czero.nez.yaml @@ -5,18 +5,18 @@ kind: instruction name: czero.nez long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicond assembly: xd, xs1, xs2 encoding: match: 0000111----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let value = X(rs1); diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index 283cccab7..124688230 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrc long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, xs1, csr encoding: match: -----------------011-----1110011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index 95b2a1625..52f008dbe 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrci long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, csr, imm encoding: match: -----------------111-----1110011 variables: - - name: csr - location: 31-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 5a5ea9f9c..a578970d6 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -18,12 +18,12 @@ assembly: xd, xs1, csr encoding: match: -----------------010-----0010011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = initial_csr_value; - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 67f2cd171..54ca92ebd 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrsi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, csr, imm encoding: match: -----------------110-----1110011 variables: - - name: csr - location: 31-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 9625c3895..97a98b343 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -17,12 +17,12 @@ assembly: xd, xs1, csr encoding: match: -----------------001-----1110011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | # performing any WARL transformations first CSR[csr].sw_write(X[rs1]); - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index 1da44ef62..473236a8b 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -17,12 +17,12 @@ assembly: xd, zimm, csr encoding: match: -----------------101-----1110011 variables: - - name: csr - location: 31-20 - - name: imm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: imm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | # performing any WARL transformations first CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zifencei/fence.i.yaml b/arch/inst/Zifencei/fence.i.yaml index 63793c2f9..4d5de9c78 100644 --- a/arch/inst/Zifencei/fence.i.yaml +++ b/arch/inst/Zifencei/fence.i.yaml @@ -37,12 +37,12 @@ assembly: "" encoding: match: -----------------001-----0001111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zimop/mop.r.n.yaml b/arch/inst/Zimop/mop.r.n.yaml index dcce06e56..6b7ef6954 100644 --- a/arch/inst/Zimop/mop.r.n.yaml +++ b/arch/inst/Zimop/mop.r.n.yaml @@ -5,22 +5,22 @@ kind: instruction name: mop.r.n long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zimop assembly: mop_r_t_30, mop_r_t_27_26, mop_r_t_21_20, xd, xs1 encoding: match: 1-00--0111-------100-----1110011 variables: - - name: mop_r_t_30 - location: 30-30 - - name: mop_r_t_27_26 - location: 27-26 - - name: mop_r_t_21_20 - location: 21-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: mop_r_t_30 + location: 30-30 + - name: mop_r_t_27_26 + location: 27-26 + - name: mop_r_t_21_20 + location: 21-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,68 +28,68 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) - to: mop.r.0 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) - to: mop.r.1 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) - to: mop.r.2 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) - to: mop.r.3 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) - to: mop.r.4 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) - to: mop.r.5 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) - to: mop.r.6 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) - to: mop.r.7 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) - to: mop.r.8 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) - to: mop.r.9 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) - to: mop.r.10 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) - to: mop.r.11 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) - to: mop.r.12 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) - to: mop.r.13 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) - to: mop.r.14 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) - to: mop.r.15 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) - to: mop.r.16 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) - to: mop.r.17 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) - to: mop.r.18 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) - to: mop.r.19 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) - to: mop.r.20 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) - to: mop.r.21 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) - to: mop.r.22 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) - to: mop.r.23 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) - to: mop.r.24 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) - to: mop.r.25 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) - to: mop.r.26 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) - to: mop.r.27 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) - to: mop.r.28 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) - to: mop.r.29 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) - to: mop.r.30 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) - to: mop.r.31 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) + to: mop.r.0 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) + to: mop.r.1 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) + to: mop.r.2 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) + to: mop.r.3 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) + to: mop.r.4 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) + to: mop.r.5 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) + to: mop.r.6 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) + to: mop.r.7 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) + to: mop.r.8 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) + to: mop.r.9 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) + to: mop.r.10 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) + to: mop.r.11 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) + to: mop.r.12 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) + to: mop.r.13 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) + to: mop.r.14 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) + to: mop.r.15 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) + to: mop.r.16 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) + to: mop.r.17 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) + to: mop.r.18 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) + to: mop.r.19 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) + to: mop.r.20 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) + to: mop.r.21 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) + to: mop.r.22 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) + to: mop.r.23 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) + to: mop.r.24 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) + to: mop.r.25 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) + to: mop.r.26 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) + to: mop.r.27 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) + to: mop.r.28 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) + to: mop.r.29 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) + to: mop.r.30 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) + to: mop.r.31 operation(): | diff --git a/arch/inst/Zimop/mop.rr.n.yaml b/arch/inst/Zimop/mop.rr.n.yaml index 4681771f1..01aeab425 100644 --- a/arch/inst/Zimop/mop.rr.n.yaml +++ b/arch/inst/Zimop/mop.rr.n.yaml @@ -5,22 +5,22 @@ kind: instruction name: mop.rr.n long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zimop assembly: mop_rr_t_30, mop_rr_t_27_26, xd, xs1, xs2 encoding: match: 1-00--1----------100-----1110011 variables: - - name: mop_rr_t_30 - location: 30-30 - - name: mop_rr_t_27_26 - location: 27-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: mop_rr_t_30 + location: 30-30 + - name: mop_rr_t_27_26 + location: 27-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,20 +28,20 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x0) - to: mop.rr.0 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x1) - to: mop.rr.1 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x2) - to: mop.rr.2 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x3) - to: mop.rr.3 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x0) - to: mop.rr.4 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x1) - to: mop.rr.5 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x2) - to: mop.rr.6 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) - to: mop.rr.7 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x0) + to: mop.rr.0 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x1) + to: mop.rr.1 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x2) + to: mop.rr.2 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x3) + to: mop.rr.3 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x0) + to: mop.rr.4 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x1) + to: mop.rr.5 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x2) + to: mop.rr.6 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) + to: mop.rr.7 operation(): | diff --git a/arch/inst/Zk/aes32dsi.yaml b/arch/inst/Zk/aes32dsi.yaml index e192c720b..443c1afa0 100644 --- a/arch/inst/Zk/aes32dsi.yaml +++ b/arch/inst/Zk/aes32dsi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32dsi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10101----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32dsmi.yaml b/arch/inst/Zk/aes32dsmi.yaml index 760aa8056..1f83af541 100644 --- a/arch/inst/Zk/aes32dsmi.yaml +++ b/arch/inst/Zk/aes32dsmi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32dsmi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10111----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32esi.yaml b/arch/inst/Zk/aes32esi.yaml index dde581325..e0c571375 100644 --- a/arch/inst/Zk/aes32esi.yaml +++ b/arch/inst/Zk/aes32esi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32esi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10001----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32esmi.yaml b/arch/inst/Zk/aes32esmi.yaml index 39a54cf93..1b875fbe6 100644 --- a/arch/inst/Zk/aes32esmi.yaml +++ b/arch/inst/Zk/aes32esmi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32esmi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10011----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ds.yaml b/arch/inst/Zk/aes64ds.yaml index 61dfb89de..6248ebfd1 100644 --- a/arch/inst/Zk/aes64ds.yaml +++ b/arch/inst/Zk/aes64ds.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ds long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011101----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64dsm.yaml b/arch/inst/Zk/aes64dsm.yaml index eef0dbbcb..99c004352 100644 --- a/arch/inst/Zk/aes64dsm.yaml +++ b/arch/inst/Zk/aes64dsm.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64dsm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64es.yaml b/arch/inst/Zk/aes64es.yaml index 5963c7a06..7f3d1b259 100644 --- a/arch/inst/Zk/aes64es.yaml +++ b/arch/inst/Zk/aes64es.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64es long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64esm.yaml b/arch/inst/Zk/aes64esm.yaml index 3013b2a06..d46b1d9ca 100644 --- a/arch/inst/Zk/aes64esm.yaml +++ b/arch/inst/Zk/aes64esm.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64esm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011011----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64im.yaml b/arch/inst/Zk/aes64im.yaml index 3b5a5388b..ea3c8050b 100644 --- a/arch/inst/Zk/aes64im.yaml +++ b/arch/inst/Zk/aes64im.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64im long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 001100000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ks1i.yaml b/arch/inst/Zk/aes64ks1i.yaml index 48520c22d..d311a22b2 100644 --- a/arch/inst/Zk/aes64ks1i.yaml +++ b/arch/inst/Zk/aes64ks1i.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ks1i long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, rnum encoding: match: 00110001---------001-----0010011 variables: - - name: rnum - location: 23-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rnum + location: 23-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ks2.yaml b/arch/inst/Zk/aes64ks2.yaml index e2189ca92..686f53dfb 100644 --- a/arch/inst/Zk/aes64ks2.yaml +++ b/arch/inst/Zk/aes64ks2.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ks2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0111111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/pack.yaml b/arch/inst/Zk/pack.yaml index 1a4a5d048..a8b886764 100644 --- a/arch/inst/Zk/pack.yaml +++ b/arch/inst/Zk/pack.yaml @@ -5,19 +5,19 @@ kind: instruction name: pack long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0000100----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/packh.yaml b/arch/inst/Zk/packh.yaml index 6101e75fc..a2b058ffd 100644 --- a/arch/inst/Zk/packh.yaml +++ b/arch/inst/Zk/packh.yaml @@ -5,19 +5,19 @@ kind: instruction name: packh long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0000100----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/packw.yaml b/arch/inst/Zk/packw.yaml index b7a986491..2005a5f04 100644 --- a/arch/inst/Zk/packw.yaml +++ b/arch/inst/Zk/packw.yaml @@ -5,7 +5,7 @@ kind: instruction name: packw long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000100----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,6 +26,6 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == 0x0) - to: zext.h + - when: (rs2 == 0x0) + to: zext.h operation(): | diff --git a/arch/inst/Zk/sha256sig0.yaml b/arch/inst/Zk/sha256sig0.yaml index 2ec32995d..47d1b88db 100644 --- a/arch/inst/Zk/sha256sig0.yaml +++ b/arch/inst/Zk/sha256sig0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sig0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000010-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sig1.yaml b/arch/inst/Zk/sha256sig1.yaml index 5534e2678..84b3b8827 100644 --- a/arch/inst/Zk/sha256sig1.yaml +++ b/arch/inst/Zk/sha256sig1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sig1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000011-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sum0.yaml b/arch/inst/Zk/sha256sum0.yaml index c80507c04..d46b5b936 100644 --- a/arch/inst/Zk/sha256sum0.yaml +++ b/arch/inst/Zk/sha256sum0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sum0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sum1.yaml b/arch/inst/Zk/sha256sum1.yaml index 94849b65e..0fa39a82e 100644 --- a/arch/inst/Zk/sha256sum1.yaml +++ b/arch/inst/Zk/sha256sum1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sum1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0.yaml b/arch/inst/Zk/sha512sig0.yaml index 65e4fecda..231ed7343 100644 --- a/arch/inst/Zk/sha512sig0.yaml +++ b/arch/inst/Zk/sha512sig0.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000110-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0h.yaml b/arch/inst/Zk/sha512sig0h.yaml index 36e442d5e..87afa1655 100644 --- a/arch/inst/Zk/sha512sig0h.yaml +++ b/arch/inst/Zk/sha512sig0h.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101110----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0l.yaml b/arch/inst/Zk/sha512sig0l.yaml index b45759fe5..334ee2dd4 100644 --- a/arch/inst/Zk/sha512sig0l.yaml +++ b/arch/inst/Zk/sha512sig0l.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101010----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1.yaml b/arch/inst/Zk/sha512sig1.yaml index 83965f0fe..3718f078a 100644 --- a/arch/inst/Zk/sha512sig1.yaml +++ b/arch/inst/Zk/sha512sig1.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000111-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1h.yaml b/arch/inst/Zk/sha512sig1h.yaml index 6dacd3aad..24b35db5f 100644 --- a/arch/inst/Zk/sha512sig1h.yaml +++ b/arch/inst/Zk/sha512sig1h.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1l.yaml b/arch/inst/Zk/sha512sig1l.yaml index e9312f90e..bc4b7957c 100644 --- a/arch/inst/Zk/sha512sig1l.yaml +++ b/arch/inst/Zk/sha512sig1l.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101011----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum0.yaml b/arch/inst/Zk/sha512sum0.yaml index 86ab00438..991dd57c4 100644 --- a/arch/inst/Zk/sha512sum0.yaml +++ b/arch/inst/Zk/sha512sum0.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000100-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum0r.yaml b/arch/inst/Zk/sha512sum0r.yaml index c535ac091..b73a79036 100644 --- a/arch/inst/Zk/sha512sum0r.yaml +++ b/arch/inst/Zk/sha512sum0r.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum0r long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum1.yaml b/arch/inst/Zk/sha512sum1.yaml index ab6ab69de..320f1dab5 100644 --- a/arch/inst/Zk/sha512sum1.yaml +++ b/arch/inst/Zk/sha512sum1.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000101-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum1r.yaml b/arch/inst/Zk/sha512sum1r.yaml index e1d04a9ab..5ecc1074b 100644 --- a/arch/inst/Zk/sha512sum1r.yaml +++ b/arch/inst/Zk/sha512sum1r.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum1r long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm3p0.yaml b/arch/inst/Zks/sm3p0.yaml index b0fbadc4a..aa903aa05 100644 --- a/arch/inst/Zks/sm3p0.yaml +++ b/arch/inst/Zks/sm3p0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sm3p0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksh] assembly: xd, xs1 encoding: match: 000100001000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm3p1.yaml b/arch/inst/Zks/sm3p1.yaml index 993184605..8cd4ca416 100644 --- a/arch/inst/Zks/sm3p1.yaml +++ b/arch/inst/Zks/sm3p1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sm3p1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksh] assembly: xd, xs1 encoding: match: 000100001001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm4ed.yaml b/arch/inst/Zks/sm4ed.yaml index df729eb2f..991a043a7 100644 --- a/arch/inst/Zks/sm4ed.yaml +++ b/arch/inst/Zks/sm4ed.yaml @@ -5,21 +5,21 @@ kind: instruction name: sm4ed long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksed] assembly: xd, xs1, xs2, bs encoding: match: --11000----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm4ks.yaml b/arch/inst/Zks/sm4ks.yaml index 6ae18d806..8f130c1ea 100644 --- a/arch/inst/Zks/sm4ks.yaml +++ b/arch/inst/Zks/sm4ks.yaml @@ -5,21 +5,21 @@ kind: instruction name: sm4ks long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksed] assembly: xd, xs1, xs2, bs encoding: match: --11010----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vandn.vv.yaml b/arch/inst/Zvbb/vandn.vv.yaml index 4da0076e0..ecf6c738a 100644 --- a/arch/inst/Zvbb/vandn.vv.yaml +++ b/arch/inst/Zvbb/vandn.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vandn.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 000001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vandn.vx.yaml b/arch/inst/Zvbb/vandn.vx.yaml index 2ffe56347..d3f99128b 100644 --- a/arch/inst/Zvbb/vandn.vx.yaml +++ b/arch/inst/Zvbb/vandn.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vandn.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 000001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vbrev.v.yaml b/arch/inst/Zvbb/vbrev.v.yaml index 71cebe309..d6545977d 100644 --- a/arch/inst/Zvbb/vbrev.v.yaml +++ b/arch/inst/Zvbb/vbrev.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vbrev.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vbrev8.v.yaml b/arch/inst/Zvbb/vbrev8.v.yaml index 4a4007d42..e148793f4 100644 --- a/arch/inst/Zvbb/vbrev8.v.yaml +++ b/arch/inst/Zvbb/vbrev8.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vbrev8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vclz.v.yaml b/arch/inst/Zvbb/vclz.v.yaml index 4365156a7..b8f0efd51 100644 --- a/arch/inst/Zvbb/vclz.v.yaml +++ b/arch/inst/Zvbb/vclz.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vclz.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01100010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vcpop.v.yaml b/arch/inst/Zvbb/vcpop.v.yaml index fefb67c38..051a4ae1e 100644 --- a/arch/inst/Zvbb/vcpop.v.yaml +++ b/arch/inst/Zvbb/vcpop.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vcpop.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01110010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vctz.v.yaml b/arch/inst/Zvbb/vctz.v.yaml index d05953576..6890a24fa 100644 --- a/arch/inst/Zvbb/vctz.v.yaml +++ b/arch/inst/Zvbb/vctz.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vctz.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01101010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrev8.v.yaml b/arch/inst/Zvbb/vrev8.v.yaml index 6fad0de88..54620007e 100644 --- a/arch/inst/Zvbb/vrev8.v.yaml +++ b/arch/inst/Zvbb/vrev8.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vrev8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrol.vv.yaml b/arch/inst/Zvbb/vrol.vv.yaml index cd07d39b1..414334ac9 100644 --- a/arch/inst/Zvbb/vrol.vv.yaml +++ b/arch/inst/Zvbb/vrol.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vrol.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 010101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrol.vx.yaml b/arch/inst/Zvbb/vrol.vx.yaml index 1210af58e..0563a4ac4 100644 --- a/arch/inst/Zvbb/vrol.vx.yaml +++ b/arch/inst/Zvbb/vrol.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vrol.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 010101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vi.yaml b/arch/inst/Zvbb/vror.vi.yaml index 78eebbb5a..e3ee0a6f3 100644 --- a/arch/inst/Zvbb/vror.vi.yaml +++ b/arch/inst/Zvbb/vror.vi.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd, imm encoding: match: 01010------------011-----1010111 variables: - - name: imm - location: 26|19-15 - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: imm + location: 26|19-15 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vv.yaml b/arch/inst/Zvbb/vror.vv.yaml index f2f40fe91..ac2f5aa2e 100644 --- a/arch/inst/Zvbb/vror.vv.yaml +++ b/arch/inst/Zvbb/vror.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 010100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vx.yaml b/arch/inst/Zvbb/vror.vx.yaml index d2a77d6b7..44871c290 100644 --- a/arch/inst/Zvbb/vror.vx.yaml +++ b/arch/inst/Zvbb/vror.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 010100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vi.yaml b/arch/inst/Zvbb/vwsll.vi.yaml index 591c1bed5..00dbd0ba2 100644 --- a/arch/inst/Zvbb/vwsll.vi.yaml +++ b/arch/inst/Zvbb/vwsll.vi.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd, imm encoding: match: 110101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vv.yaml b/arch/inst/Zvbb/vwsll.vv.yaml index 2b3a21c37..0f2b4d1dd 100644 --- a/arch/inst/Zvbb/vwsll.vv.yaml +++ b/arch/inst/Zvbb/vwsll.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 110101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vx.yaml b/arch/inst/Zvbb/vwsll.vx.yaml index bee40592d..91c02eb5b 100644 --- a/arch/inst/Zvbb/vwsll.vx.yaml +++ b/arch/inst/Zvbb/vwsll.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 110101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmul.vv.yaml b/arch/inst/Zvbc/vclmul.vv.yaml index 5546905fe..261456a1a 100644 --- a/arch/inst/Zvbc/vclmul.vv.yaml +++ b/arch/inst/Zvbc/vclmul.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 001100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmul.vx.yaml b/arch/inst/Zvbc/vclmul.vx.yaml index 9e965b1be..e90c8b3f6 100644 --- a/arch/inst/Zvbc/vclmul.vx.yaml +++ b/arch/inst/Zvbc/vclmul.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 001100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmulh.vv.yaml b/arch/inst/Zvbc/vclmulh.vv.yaml index 4a077cfc0..7511606c5 100644 --- a/arch/inst/Zvbc/vclmulh.vv.yaml +++ b/arch/inst/Zvbc/vclmulh.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmulh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 001101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmulh.vx.yaml b/arch/inst/Zvbc/vclmulh.vx.yaml index ff4ed9467..21b7b865e 100644 --- a/arch/inst/Zvbc/vclmulh.vx.yaml +++ b/arch/inst/Zvbc/vclmulh.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmulh.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 001101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml index c6e7afbed..2c6a47f5f 100644 --- a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +++ b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvtbf16.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfmin assembly: vm, vs2, vd encoding: match: 010010------11101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml index c5300811c..421c80fc5 100644 --- a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +++ b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvtbf16.f.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfmin assembly: vm, vs2, vd encoding: match: 010010------01101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml index fa975d1b4..30054ef34 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmaccbf16.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfwma assembly: vm, vs2, xs1, vd encoding: match: 111011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml index dc775e29b..09189a2db 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmaccbf16.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfwma assembly: vm, vs2, vs1, vd encoding: match: 111011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkg/vghsh.vv.yaml b/arch/inst/Zvkg/vghsh.vv.yaml index 25cf67cf7..a4f20bd16 100644 --- a/arch/inst/Zvkg/vghsh.vv.yaml +++ b/arch/inst/Zvkg/vghsh.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vghsh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvkg assembly: vs2, vs1, vd encoding: match: 1011001----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkg/vgmul.vv.yaml b/arch/inst/Zvkg/vgmul.vv.yaml index c4e1a173f..713f4c957 100644 --- a/arch/inst/Zvkg/vgmul.vv.yaml +++ b/arch/inst/Zvkg/vgmul.vv.yaml @@ -5,16 +5,16 @@ kind: instruction name: vgmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvkg assembly: vs2, vd encoding: match: 1010001-----10001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdf.vs.yaml b/arch/inst/Zvkn/vaesdf.vs.yaml index 9a870b3d7..dfab3452f 100644 --- a/arch/inst/Zvkn/vaesdf.vs.yaml +++ b/arch/inst/Zvkn/vaesdf.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdf.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdf.vv.yaml b/arch/inst/Zvkn/vaesdf.vv.yaml index 7ecb3e260..943a7652c 100644 --- a/arch/inst/Zvkn/vaesdf.vv.yaml +++ b/arch/inst/Zvkn/vaesdf.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdf.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdm.vs.yaml b/arch/inst/Zvkn/vaesdm.vs.yaml index 4f6ba265c..986d97d46 100644 --- a/arch/inst/Zvkn/vaesdm.vs.yaml +++ b/arch/inst/Zvkn/vaesdm.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdm.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdm.vv.yaml b/arch/inst/Zvkn/vaesdm.vv.yaml index 3fc90fcec..2585b72b0 100644 --- a/arch/inst/Zvkn/vaesdm.vv.yaml +++ b/arch/inst/Zvkn/vaesdm.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdm.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesef.vs.yaml b/arch/inst/Zvkn/vaesef.vs.yaml index b3d18719d..490d8b6e1 100644 --- a/arch/inst/Zvkn/vaesef.vs.yaml +++ b/arch/inst/Zvkn/vaesef.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesef.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00011010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesef.vv.yaml b/arch/inst/Zvkn/vaesef.vv.yaml index 0e692cf83..3bf5f12c8 100644 --- a/arch/inst/Zvkn/vaesef.vv.yaml +++ b/arch/inst/Zvkn/vaesef.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesef.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00011010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesem.vs.yaml b/arch/inst/Zvkn/vaesem.vs.yaml index 7010af1bb..0a8ea43b3 100644 --- a/arch/inst/Zvkn/vaesem.vs.yaml +++ b/arch/inst/Zvkn/vaesem.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesem.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00010010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesem.vv.yaml b/arch/inst/Zvkn/vaesem.vv.yaml index ae5618f1d..e515036e4 100644 --- a/arch/inst/Zvkn/vaesem.vv.yaml +++ b/arch/inst/Zvkn/vaesem.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesem.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00010010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaeskf1.vi.yaml b/arch/inst/Zvkn/vaeskf1.vi.yaml index ea88d6459..e8554288b 100644 --- a/arch/inst/Zvkn/vaeskf1.vi.yaml +++ b/arch/inst/Zvkn/vaeskf1.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vaeskf1.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd, imm encoding: match: 1000101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaeskf2.vi.yaml b/arch/inst/Zvkn/vaeskf2.vi.yaml index c00b3621d..6c2a56603 100644 --- a/arch/inst/Zvkn/vaeskf2.vi.yaml +++ b/arch/inst/Zvkn/vaeskf2.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vaeskf2.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd, imm encoding: match: 1010101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesz.vs.yaml b/arch/inst/Zvkn/vaesz.vs.yaml index 970a9bae8..8d422dd7c 100644 --- a/arch/inst/Zvkn/vaesz.vs.yaml +++ b/arch/inst/Zvkn/vaesz.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesz.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00111010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2ch.vv.yaml b/arch/inst/Zvkn/vsha2ch.vv.yaml index d29bd4d82..47b3bdf00 100644 --- a/arch/inst/Zvkn/vsha2ch.vv.yaml +++ b/arch/inst/Zvkn/vsha2ch.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2ch.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2cl.vv.yaml b/arch/inst/Zvkn/vsha2cl.vv.yaml index 9aa0dd3c2..4d66f7692 100644 --- a/arch/inst/Zvkn/vsha2cl.vv.yaml +++ b/arch/inst/Zvkn/vsha2cl.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2cl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011111----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2ms.vv.yaml b/arch/inst/Zvkn/vsha2ms.vv.yaml index 57e5cea2c..d7e30cfd7 100644 --- a/arch/inst/Zvkn/vsha2ms.vv.yaml +++ b/arch/inst/Zvkn/vsha2ms.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2ms.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011011----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm3c.vi.yaml b/arch/inst/Zvks/vsm3c.vi.yaml index 03d5de481..a053310cd 100644 --- a/arch/inst/Zvks/vsm3c.vi.yaml +++ b/arch/inst/Zvks/vsm3c.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm3c.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksh] assembly: vs2, vd, imm encoding: match: 1010111----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm3me.vv.yaml b/arch/inst/Zvks/vsm3me.vv.yaml index 25b76850b..eb092b573 100644 --- a/arch/inst/Zvks/vsm3me.vv.yaml +++ b/arch/inst/Zvks/vsm3me.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm3me.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksh] assembly: vs2, vs1, vd encoding: match: 1000001----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4k.vi.yaml b/arch/inst/Zvks/vsm4k.vi.yaml index 14056756f..cb04d00b0 100644 --- a/arch/inst/Zvks/vsm4k.vi.yaml +++ b/arch/inst/Zvks/vsm4k.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm4k.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd, imm encoding: match: 1000011----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4r.vs.yaml b/arch/inst/Zvks/vsm4r.vs.yaml index e21b71637..968903254 100644 --- a/arch/inst/Zvks/vsm4r.vs.yaml +++ b/arch/inst/Zvks/vsm4r.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vsm4r.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd encoding: match: 1010011-----10000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4r.vv.yaml b/arch/inst/Zvks/vsm4r.vv.yaml index e1d60fd3d..ec2507b6b 100644 --- a/arch/inst/Zvks/vsm4r.vv.yaml +++ b/arch/inst/Zvks/vsm4r.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vsm4r.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd encoding: match: 1010001-----10000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/manual/isa/20240411/contents.yaml b/arch/manual/isa/20240411/contents.yaml index 3ade2dea1..b28f4ce72 100644 --- a/arch/manual/isa/20240411/contents.yaml +++ b/arch/manual/isa/20240411/contents.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../../../schemas/manual_version_schema.json - --- manual: isa version: "4.0.0-pre" @@ -10,212 +9,212 @@ url: https://github.com/riscv/riscv-isa-manual/releases/tag/20240411 uses_isa_manual: true isa_manual_tree: "tags/20240411" volumes: -- title: "RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" - description: "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" - authors: - - name: Andrew Waterman - email: awaterman@sifive.com - organization: - name: SiFive, Inc. - url: https://www.sifive.com/ - chapters: - - riscv-isa-manual/src/colophon.adoc - - riscv-isa-manual/src/intro.adoc - - riscv-isa-manual/src/rv32.adoc - - riscv-isa-manual/src/rv32e.adoc - - riscv-isa-manual/src/rv64.adoc - - riscv-isa-manual/src/rv128.adoc - - riscv-isa-manual/src/zifencei.adoc - - riscv-isa-manual/src/zicsr.adoc - - riscv-isa-manual/src/counters.adoc - - riscv-isa-manual/src/zihintntl.adoc - - riscv-isa-manual/src/zihintpause.adoc - - riscv-isa-manual/src/zimop.adoc - - riscv-isa-manual/src/zicond.adoc - - riscv-isa-manual/src/m-st-ext.adoc - - riscv-isa-manual/src/a-st-ext.adoc - - riscv-isa-manual/src/zawrs.adoc - - riscv-isa-manual/src/zacas.adoc - - riscv-isa-manual/src/rvwmo.adoc - - riscv-isa-manual/src/ztso-st-ext.adoc - - riscv-isa-manual/src/cmo.adoc - - riscv-isa-manual/src/f-st-ext.adoc - - riscv-isa-manual/src/d-st-ext.adoc - - riscv-isa-manual/src/q-st-ext.adoc - - riscv-isa-manual/src/zfh.adoc - - riscv-isa-manual/src/zfa.adoc - - riscv-isa-manual/src/zfinx.adoc - - riscv-isa-manual/src/c-st-ext.adoc - - riscv-isa-manual/src/zc.adoc - - riscv-isa-manual/src/b-st-ext.adoc - - riscv-isa-manual/src/j-st-ext.adoc - - riscv-isa-manual/src/p-st-ext.adoc - - riscv-isa-manual/src/v-st-ext.adoc - - riscv-isa-manual/src/scalar-crypto.adoc - - riscv-isa-manual/src/vector-crypto.adoc - - riscv-isa-manual/src/rv-32-64g.adoc - - riscv-isa-manual/src/extending.adoc - - riscv-isa-manual/src/naming.adoc - - riscv-isa-manual/src/history.adoc - - riscv-isa-manual/src/mm-eplan.adoc - - riscv-isa-manual/src/mm-formal.adoc - #Appendices for Vector - - riscv-isa-manual/src/vector-examples.adoc - - riscv-isa-manual/src/calling-convention.adoc - #/End of Vector appendices - - riscv-isa-manual/src/index.adoc - extensions: - - [I, "2.1.0"] - - [U, "1.12.0"] - # - [E, "2.0"] - # - [RVI64, "2.1"] - # - [RVI128, "1.7"] - - [Zifencei, "2.0.0"] - - [Zicsr, "2.0.0"] - - [Zicntr, "2.0.0"] - - [Zihpm, "2.0.0"] - - [Zihintntl, "1.0.0"] - - [Zihintpause, "2.0.0"] - - [Zimop, "2.0.0"] - - [Zicond, "1.0.0"] - - [M, "2.0.0"] - - [A, "2.1.0"] - - [Zawrs, "1.0.1"] - - [Zacas, "1.0.0"] - - [Zabha, "1.0.0"] - # - [RVWMO, "2.0"] - - [Ztso, "1.0.0"] - - [Zicbom, "1.0.0"] - - [Zicboz, "1.0.0"] - - [Zicbop, "1.0.0"] - - [F, "2.2.0"] - - [D, "2.2.0"] - # - [Q, "2.2"] - - [Zfh, "1.0.0"] - - [Zfhmin, "1.0.0"] - - [Zfbfmin, "1.0.0"] - - [Zvfbfmin, "1.0.0"] - - [Zvfbfwma, "1.0.0"] - - [Zfa, "1.0.0"] - - [Zfinx, "1.0.0"] - - [Zdinx, "1.0.0"] - - [Zhinx, "1.0.0"] - - [C, "2.0.0"] - - [Zca, "1.0.0"] - - [Zcf, "1.0.0"] - - [Zcd, "1.0.0"] - - [Zcb, "1.0.0"] - - [Zcmp, "1.0.0"] - - [Zcmt, "1.0.0"] - - [B, "1.0.0"] - - [Zba, "1.0.0"] - - [Zbb, "1.0.0"] - - [Zbc, "1.0.0"] - - [Zbs, "1.0.0"] - - [Zbkb, "1.0.0"] - - [Zbkc, "1.0.0"] - - [Zbkx, "1.0.0"] - # - [J, "0.0"] - # - [P, "0.2"] - - [V, "1.0.0"] - - [Zvl32b, "1.0.0"] - - [Zvl64b, "1.0.0"] - - [Zvl128b, "1.0.0"] - - [Zvl256b, "1.0.0"] - - [Zvl512b, "1.0.0"] - - [Zvl1024b, "1.0.0"] - - [Zve32x, "1.0.0"] - - [Zve32f, "1.0.0"] - - [Zve64x, "1.0.0"] - - [Zve64f, "1.0.0"] - - [Zve64d, "1.0.0"] - - [Zvfhmin, "1.0.0"] - - [Zvfh, "1.0.0"] - - [Zvknha, "1.0.0"] - - [Zvknhb, "1.0.0"] - - [Zbkb, "1.0.0"] - - [Zbkc, "1.0.0"] - - [Zbkx, "1.0.0"] - - [Zknd, "1.0.0"] - - [Zkne, "1.0.0"] - - [Zknh, "1.0.0"] - - [Zksed, "1.0.0"] - - [Zksh, "1.0.0"] - - [Zkr, "1.0.0"] - - [Zkn, "1.0.0"] - - [Zks, "1.0.0"] - - [Zk, "1.0.0"] - - [Zkt, "1.0.0"] - - [Zvbb, "1.0.0"] - - [Zvbc, "1.0.0"] - - [Zvkb, "1.0.0"] - - [Zvkg, "1.0.0"] - - [Zvkned, "1.0.0"] - - [Zvknha, "1.0.0"] - - [Zvknhb, "1.0.0"] - - [Zvksed, "1.0.0"] - - [Zvksh, "1.0.0"] - - [Zvkn, "1.0.0"] - - [Zvknc, "1.0.0"] - - [Zvkng, "1.0.0"] - - [Zvks, "1.0.0"] - - [Zvksc, "1.0.0"] - - [Zvksg, "1.0.0"] - - [Zvkt, "1.0.0"] - - [Zicfilp, "1.0.0"] - - [Zicfiss, "1.0.0"] - # - [Zam, "0.1"] - changes: - - The inclusion of all ratified extensions through March 2024. - - The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. - - The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. -- title: "RISC-V Instruction Set Manual, Volume II: Privileged ISA" - description: "The RISC-V Instruction Set Manual, Volume II: Privileged ISA" - authors: - - name: Andrew Waterman - email: awaterman@sifive.com - organization: - name: SiFive, Inc. - url: https://www.sifive.com/ - chapters: - - riscv-isa-manual/src/priv-preface.adoc - - riscv-isa-manual/src/priv-intro.adoc - - riscv-isa-manual/src/priv-csrs.adoc - - riscv-isa-manual/src/machine.adoc - - riscv-isa-manual/src/smstateen.adoc - - riscv-isa-manual/src/indirect-csr.adoc - - riscv-isa-manual/src/smepmp.adoc - - riscv-isa-manual/src/smcntrpmf.adoc - - riscv-isa-manual/src/rnmi.adoc - - riscv-isa-manual/src/smcdeleg.adoc - - riscv-isa-manual/src/supervisor.adoc - - riscv-isa-manual/src/sstc.adoc - - riscv-isa-manual/src/sscofpmf.adoc - - riscv-isa-manual/src/hypervisor.adoc - - riscv-isa-manual/src/priv-insns.adoc - - riscv-isa-manual/src/priv-history.adoc - - riscv-isa-manual/src/bibliography.adoc - extensions: - - [Smstateen, "1.0.0"] - - [Smcsrind, "1.0.0"] - - [Sscsrind, "1.0.0"] - - [Smepmp, "1.0.0"] - - [Smcntrpmf, "1.0.0"] - - [Smrnmi, "0.5.0"] - - [Smcdeleg, "1.0.0"] - - [S, "1.12.0"] - - [Sm, "1.12.0"] - - [Smhpm, "1.12.0"] - - [Smpmp, "1.12.0"] - - [Sv32, "1.12.0"] - - [Sv39, "1.12.0"] - - [Sv48, "1.12.0"] - - [Sv57, "1.12.0"] - - [Svnapot, "1.0.0"] - - [Svpbmt, "1.0.0"] - - [Svinval, "1.0.0"] - - [Svadu, "1.0.0"] - - [Svvptc, "1.0.0"] - - [Sstc, "1.0.0"] - - [Sscofpmf, "1.0.0"] - - [H, "1.0.0"] + - title: "RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" + description: "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" + authors: + - name: Andrew Waterman + email: awaterman@sifive.com + organization: + name: SiFive, Inc. + url: https://www.sifive.com/ + chapters: + - riscv-isa-manual/src/colophon.adoc + - riscv-isa-manual/src/intro.adoc + - riscv-isa-manual/src/rv32.adoc + - riscv-isa-manual/src/rv32e.adoc + - riscv-isa-manual/src/rv64.adoc + - riscv-isa-manual/src/rv128.adoc + - riscv-isa-manual/src/zifencei.adoc + - riscv-isa-manual/src/zicsr.adoc + - riscv-isa-manual/src/counters.adoc + - riscv-isa-manual/src/zihintntl.adoc + - riscv-isa-manual/src/zihintpause.adoc + - riscv-isa-manual/src/zimop.adoc + - riscv-isa-manual/src/zicond.adoc + - riscv-isa-manual/src/m-st-ext.adoc + - riscv-isa-manual/src/a-st-ext.adoc + - riscv-isa-manual/src/zawrs.adoc + - riscv-isa-manual/src/zacas.adoc + - riscv-isa-manual/src/rvwmo.adoc + - riscv-isa-manual/src/ztso-st-ext.adoc + - riscv-isa-manual/src/cmo.adoc + - riscv-isa-manual/src/f-st-ext.adoc + - riscv-isa-manual/src/d-st-ext.adoc + - riscv-isa-manual/src/q-st-ext.adoc + - riscv-isa-manual/src/zfh.adoc + - riscv-isa-manual/src/zfa.adoc + - riscv-isa-manual/src/zfinx.adoc + - riscv-isa-manual/src/c-st-ext.adoc + - riscv-isa-manual/src/zc.adoc + - riscv-isa-manual/src/b-st-ext.adoc + - riscv-isa-manual/src/j-st-ext.adoc + - riscv-isa-manual/src/p-st-ext.adoc + - riscv-isa-manual/src/v-st-ext.adoc + - riscv-isa-manual/src/scalar-crypto.adoc + - riscv-isa-manual/src/vector-crypto.adoc + - riscv-isa-manual/src/rv-32-64g.adoc + - riscv-isa-manual/src/extending.adoc + - riscv-isa-manual/src/naming.adoc + - riscv-isa-manual/src/history.adoc + - riscv-isa-manual/src/mm-eplan.adoc + - riscv-isa-manual/src/mm-formal.adoc + #Appendices for Vector + - riscv-isa-manual/src/vector-examples.adoc + - riscv-isa-manual/src/calling-convention.adoc + #/End of Vector appendices + - riscv-isa-manual/src/index.adoc + extensions: + - [I, "2.1.0"] + - [U, "1.12.0"] + # - [E, "2.0"] + # - [RVI64, "2.1"] + # - [RVI128, "1.7"] + - [Zifencei, "2.0.0"] + - [Zicsr, "2.0.0"] + - [Zicntr, "2.0.0"] + - [Zihpm, "2.0.0"] + - [Zihintntl, "1.0.0"] + - [Zihintpause, "2.0.0"] + - [Zimop, "2.0.0"] + - [Zicond, "1.0.0"] + - [M, "2.0.0"] + - [A, "2.1.0"] + - [Zawrs, "1.0.1"] + - [Zacas, "1.0.0"] + - [Zabha, "1.0.0"] + # - [RVWMO, "2.0"] + - [Ztso, "1.0.0"] + - [Zicbom, "1.0.0"] + - [Zicboz, "1.0.0"] + - [Zicbop, "1.0.0"] + - [F, "2.2.0"] + - [D, "2.2.0"] + # - [Q, "2.2"] + - [Zfh, "1.0.0"] + - [Zfhmin, "1.0.0"] + - [Zfbfmin, "1.0.0"] + - [Zvfbfmin, "1.0.0"] + - [Zvfbfwma, "1.0.0"] + - [Zfa, "1.0.0"] + - [Zfinx, "1.0.0"] + - [Zdinx, "1.0.0"] + - [Zhinx, "1.0.0"] + - [C, "2.0.0"] + - [Zca, "1.0.0"] + - [Zcf, "1.0.0"] + - [Zcd, "1.0.0"] + - [Zcb, "1.0.0"] + - [Zcmp, "1.0.0"] + - [Zcmt, "1.0.0"] + - [B, "1.0.0"] + - [Zba, "1.0.0"] + - [Zbb, "1.0.0"] + - [Zbc, "1.0.0"] + - [Zbs, "1.0.0"] + - [Zbkb, "1.0.0"] + - [Zbkc, "1.0.0"] + - [Zbkx, "1.0.0"] + # - [J, "0.0"] + # - [P, "0.2"] + - [V, "1.0.0"] + - [Zvl32b, "1.0.0"] + - [Zvl64b, "1.0.0"] + - [Zvl128b, "1.0.0"] + - [Zvl256b, "1.0.0"] + - [Zvl512b, "1.0.0"] + - [Zvl1024b, "1.0.0"] + - [Zve32x, "1.0.0"] + - [Zve32f, "1.0.0"] + - [Zve64x, "1.0.0"] + - [Zve64f, "1.0.0"] + - [Zve64d, "1.0.0"] + - [Zvfhmin, "1.0.0"] + - [Zvfh, "1.0.0"] + - [Zvknha, "1.0.0"] + - [Zvknhb, "1.0.0"] + - [Zbkb, "1.0.0"] + - [Zbkc, "1.0.0"] + - [Zbkx, "1.0.0"] + - [Zknd, "1.0.0"] + - [Zkne, "1.0.0"] + - [Zknh, "1.0.0"] + - [Zksed, "1.0.0"] + - [Zksh, "1.0.0"] + - [Zkr, "1.0.0"] + - [Zkn, "1.0.0"] + - [Zks, "1.0.0"] + - [Zk, "1.0.0"] + - [Zkt, "1.0.0"] + - [Zvbb, "1.0.0"] + - [Zvbc, "1.0.0"] + - [Zvkb, "1.0.0"] + - [Zvkg, "1.0.0"] + - [Zvkned, "1.0.0"] + - [Zvknha, "1.0.0"] + - [Zvknhb, "1.0.0"] + - [Zvksed, "1.0.0"] + - [Zvksh, "1.0.0"] + - [Zvkn, "1.0.0"] + - [Zvknc, "1.0.0"] + - [Zvkng, "1.0.0"] + - [Zvks, "1.0.0"] + - [Zvksc, "1.0.0"] + - [Zvksg, "1.0.0"] + - [Zvkt, "1.0.0"] + - [Zicfilp, "1.0.0"] + - [Zicfiss, "1.0.0"] + # - [Zam, "0.1"] + changes: + - The inclusion of all ratified extensions through March 2024. + - The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. + - The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. + - title: "RISC-V Instruction Set Manual, Volume II: Privileged ISA" + description: "The RISC-V Instruction Set Manual, Volume II: Privileged ISA" + authors: + - name: Andrew Waterman + email: awaterman@sifive.com + organization: + name: SiFive, Inc. + url: https://www.sifive.com/ + chapters: + - riscv-isa-manual/src/priv-preface.adoc + - riscv-isa-manual/src/priv-intro.adoc + - riscv-isa-manual/src/priv-csrs.adoc + - riscv-isa-manual/src/machine.adoc + - riscv-isa-manual/src/smstateen.adoc + - riscv-isa-manual/src/indirect-csr.adoc + - riscv-isa-manual/src/smepmp.adoc + - riscv-isa-manual/src/smcntrpmf.adoc + - riscv-isa-manual/src/rnmi.adoc + - riscv-isa-manual/src/smcdeleg.adoc + - riscv-isa-manual/src/supervisor.adoc + - riscv-isa-manual/src/sstc.adoc + - riscv-isa-manual/src/sscofpmf.adoc + - riscv-isa-manual/src/hypervisor.adoc + - riscv-isa-manual/src/priv-insns.adoc + - riscv-isa-manual/src/priv-history.adoc + - riscv-isa-manual/src/bibliography.adoc + extensions: + - [Smstateen, "1.0.0"] + - [Smcsrind, "1.0.0"] + - [Sscsrind, "1.0.0"] + - [Smepmp, "1.0.0"] + - [Smcntrpmf, "1.0.0"] + - [Smrnmi, "0.5.0"] + - [Smcdeleg, "1.0.0"] + - [S, "1.12.0"] + - [Sm, "1.12.0"] + - [Smhpm, "1.12.0"] + - [Smpmp, "1.12.0"] + - [Sv32, "1.12.0"] + - [Sv39, "1.12.0"] + - [Sv48, "1.12.0"] + - [Sv57, "1.12.0"] + - [Svnapot, "1.0.0"] + - [Svpbmt, "1.0.0"] + - [Svinval, "1.0.0"] + - [Svadu, "1.0.0"] + - [Svvptc, "1.0.0"] + - [Sstc, "1.0.0"] + - [Sscofpmf, "1.0.0"] + - [H, "1.0.0"] diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 6b18b173d..9a40b5eeb 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -5,19 +5,19 @@ MockProfileRelease: release: 20 state: ratified # current status ["ratified", "development"] versions: - - version: "1.0" + - version: "1.0" ratification_date: "2024-01-01" introduction: Here's the Mock Profile Release introduction. description: | This is the Mock Profile Release description. It can be longer than the introduction since it gets its own sub-heading. contributors: - - name: Joe Blow - email: joe.blow@riscv.org - company: Acme Inc - - name: Jane Doe - email: jane.doe@gmail.com - company: Universal Imports + - name: Joe Blow + email: joe.blow@riscv.org + company: Acme Inc + - name: Jane Doe + email: jane.doe@gmail.com + company: Universal Imports profiles: MP-U-64: marketing_name: MockProfile 64-bit Unpriv @@ -41,9 +41,9 @@ MockProfileRelease: base: 64 release: MockProfileRelease contributors: - - name: Micky Mouse - email: micky@disney.com - company: Disney + - name: Micky Mouse + email: micky@disney.com + company: Disney extensions: $inherits: "#/MockProfileRelease/profiles/MP-U-64/extensions" A: @@ -56,7 +56,7 @@ MockProfileRelease: Zifencei: presence: optional: development - version: "~> 2.0" + version: "= 2.0" note: Zihpm: presence: @@ -69,32 +69,32 @@ MockProfileRelease: version: "~> 1.11" note: Made this a transitory option extra_notes: - - presence: mandatory - text: | - Here's the first extra note for the mandatory extensions section. - This note is multiple lines. - - presence: optional - text: | - Here's the first extra note for the optional extensions section. - In this case, we don't differentiate between optional types. - This note is multiple lines. - - presence: - optional: localized - text: Here's the first extra note for the localized optional extensions section. - - presence: - optional: localized - text: Here's the second extra note for the localized optional extensions section. - - presence: - optional: development - text: Here's the first extra note for the development optional extensions section. - - presence: - optional: expansion - text: Here's the first extra note for the expansion optional extensions section. - - presence: - optional: transitory - text: Here's the first extra note for the transitory optional extensions section. + - presence: mandatory + text: | + Here's the first extra note for the mandatory extensions section. + This note is multiple lines. + - presence: optional + text: | + Here's the first extra note for the optional extensions section. + In this case, we don't differentiate between optional types. + This note is multiple lines. + - presence: + optional: localized + text: Here's the first extra note for the localized optional extensions section. + - presence: + optional: localized + text: Here's the second extra note for the localized optional extensions section. + - presence: + optional: development + text: Here's the first extra note for the development optional extensions section. + - presence: + optional: expansion + text: Here's the first extra note for the expansion optional extensions section. + - presence: + optional: transitory + text: Here's the first extra note for the transitory optional extensions section. recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. - - text: Micky should give Pluto an extra treat + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + - text: Micky should give Pluto an extra treat diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index b920ef717..162aba901 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -8,7 +8,7 @@ RVA20: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -28,9 +28,9 @@ RVA20: NOTE: Only XLEN=64 application processor profiles are currently defined. It would be possible to also define very similar XLEN=32 variants. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVA20U64: marketing_name: RVA20U64 @@ -44,7 +44,7 @@ RVA20: terms of the amount of software that targets this profile. extensions: $inherits: "profile_release/RVI20.yaml#/RVI20/profiles/RVI20U64/extensions" - $remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA). + $remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA). A: presence: mandatory C: @@ -98,36 +98,36 @@ RVA20: distributions should assume their existence only for correctness, not for performance. extra_notes: - - presence: optional - text: | - The rationale to not make Q an optional extension is that - quad-precision floating-point is unlikely to be implemented in - hardware, and so we do not require or expect A-profile software to - expend effort optimizing use of Q instructions in case they are - present. - - presence: optional - text: | - Zifencei is not classed as a supported option in the user-mode - profile because it is not sufficient by itself to produce the desired - effect in a multiprogrammed multiprocessor environment without OS - support, and so the instruction cache flush should always be performed - using an OS call rather than using the `fence.i` instruction. - `fence.i` semantics can be expensive to implement for some hardware - memory hierarchy designs, and so alternative non-standard - instruction-cache coherence mechanisms can be used behind the OS - abstraction. A separate extension is being developed for more general - and efficient instruction cache coherence. - - presence: optional - text: | - The execution environment must provide a means to synchronize writes to - instruction memory with instruction fetches, the implementation of which - likely relies on the Zifencei extension. - For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and - a corresponding vDSO call. + - presence: optional + text: | + The rationale to not make Q an optional extension is that + quad-precision floating-point is unlikely to be implemented in + hardware, and so we do not require or expect A-profile software to + expend effort optimizing use of Q instructions in case they are + present. + - presence: optional + text: | + Zifencei is not classed as a supported option in the user-mode + profile because it is not sufficient by itself to produce the desired + effect in a multiprogrammed multiprocessor environment without OS + support, and so the instruction cache flush should always be performed + using an OS call rather than using the `fence.i` instruction. + `fence.i` semantics can be expensive to implement for some hardware + memory hierarchy designs, and so alternative non-standard + instruction-cache coherence mechanisms can be used behind the OS + abstraction. A separate extension is being developed for more general + and efficient instruction cache coherence. + - presence: optional + text: | + The execution environment must provide a means to synchronize writes to + instruction memory with instruction fetches, the implementation of which + likely relies on the Zifencei extension. + For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and + a corresponding vDSO call. recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVA20S64: marketing_name: RVA20S64 mode: S diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 3df820062..816564a19 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -8,7 +8,7 @@ RVA22: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -28,9 +28,9 @@ RVA22: NOTE: Only XLEN=64 application processor profiles are currently defined. It would be possible to also define very similar XLEN=32 variants. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVA22U64: marketing_name: RVA22U64 @@ -133,33 +133,29 @@ RVA22: presence: optional version: "~> 1.0" extra_notes: - - presence: optional - text: | - The scalar crypto extensions are expected to be superseded by - vector crypto standards in future profiles, and the scalar extensions - may be removed as supported options once vector crypto is present. - - presence: optional - text: | - The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, - Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate - options in the profile. Profile implementers should provide all of - the instructions in a given algorithm suite as part of the Zkn or Zks - supported options. - - presence: optional - text: | - Access to the entropy source (Zkr) in a system is usually - carefully controlled. While the design supports unprivileged access - to the entropy source, this is unlikely to be commonly used in an - application processor, and so Zkr was not added as a profile option. - This also means the roll-up Zk was not added as a profile option. - - presence: optional - text: | - The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible - with the profile mandates to support the F and D extensions. - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - presence: optional + text: | + The scalar crypto extensions are expected to be superseded by + vector crypto standards in future profiles, and the scalar extensions + may be removed as supported options once vector crypto is present. + - presence: optional + text: | + The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, + Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate + options in the profile. Profile implementers should provide all of + the instructions in a given algorithm suite as part of the Zkn or Zks + supported options. + - presence: optional + text: | + Access to the entropy source (Zkr) in a system is usually + carefully controlled. While the design supports unprivileged access + to the entropy source, this is unlikely to be commonly used in an + application processor, and so Zkr was not added as a profile option. + This also means the roll-up Zk was not added as a profile option. + - presence: optional + text: | + The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible + with the profile mandates to support the F and D extensions. RVA22S64: marketing_name: RVA22S64 mode: S @@ -262,7 +258,3 @@ RVA22: * Shtvala * Shvstvecd * Shgatpa - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 3bd5b6750..3c3b1f63d 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -8,14 +8,14 @@ RVI20: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | The two profiles RVI20U32 and RVI20U64 correspond to the RV32I and RV64I base ISAs respectively. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVI20U32: marketing_name: RVI20U32 @@ -80,9 +80,9 @@ RVI20: presence: optional version: "~> 2.0" recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVI20U64: $inherits: "#/RVI20/profiles/RVI20U32" base: 64 diff --git a/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml b/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml index f0f01d376..81aabeed3 100644 --- a/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml +++ b/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../../../schemas/csr_schema.json - --- $schema: "csr_schema.json#" kind: csr diff --git a/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml b/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml index 80aa49d40..1579a46a6 100644 --- a/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml +++ b/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml @@ -5,8 +5,8 @@ name: Xcustom long_name: A new custom extension! type: unprivileged versions: -- version: "0.1.0" - ratification_date: null - state: development + - version: "0.1.0" + ratification_date: null + state: development description: | A new custom extension! diff --git a/cfgs/generic_rv64/params.yaml b/cfgs/generic_rv64/params.yaml index ace3ee74d..b7f97c19f 100644 --- a/cfgs/generic_rv64/params.yaml +++ b/cfgs/generic_rv64/params.yaml @@ -1,4 +1,3 @@ - --- params: XLEN: 64 @@ -32,43 +31,43 @@ params: MISALIGNED_AMO: false HPM_COUNTER_EN: - - false # CY - - false # empty - - false # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - false # CY + - false # empty + - false # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # list of defined HPM events HPM_EVENTS: - - 0 - - 3 + - 0 + - 3 # Indicates which counters can be disabled from mcountinhibit # @@ -77,38 +76,38 @@ params: # 11 in COUNTINHIBIT_EN since the highest implemented counter # would be at bit 10 COUNTINHIBIT_EN: - - true # CY - - false # empty - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # empty + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via mcounteren # @@ -117,38 +116,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 MCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via scounteren # @@ -157,38 +156,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 SCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via hcounteren # @@ -197,38 +196,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 HCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # when true, writing an illegal value to a WLRL CSR field raises an Illegal Instruction exception # when false, writing an illegal value to a WLRL CSR field is ignored @@ -291,7 +290,6 @@ params: # REPORT_CAUSE_IN_VSTVAL_ON_SOFTWARE_CHECK: true # VSTVAL_WIDTH not needed; "vstval is a WARL register that must be able to hold the same set of values that stval can hold" - # address of the unified discovery configuration data structure # this address is reported in the mconfigptr CSR CONFIG_PTR_ADDRESS: 0x1000 @@ -510,11 +508,11 @@ params: TINST_VALUE_ON_LOAD_PAGE_FAULT: "always zero" TINST_VALUE_ON_STORE_AMO_PAGE_FAULT: "always zero" MTVEC_MODES: [0, 1] - MSTATUS_FS_LEGAL_VALUES: [0,1,2,3] + MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3] MSTATUS_FS_WRITEABLE: true MSTATUS_TVM_IMPLEMENTED: true HW_MSTATUS_FS_DIRTY_UPDATE: precise MSTATUS_VS_WRITEABLE: true - MSTATUS_VS_LEGAL_VALUES: [0,1,2,3] + MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3] HW_MSTATUS_VS_DIRTY_UPDATE: precise FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: true diff --git a/schemas/arch_schema.json b/schemas/arch_schema.json index 385784650..52871d719 100644 --- a/schemas/arch_schema.json +++ b/schemas/arch_schema.json @@ -3,17 +3,12 @@ "type": "object", "title": "Unified Architecture Specification", - "required": [ - "type", - "extensions", - "csrs", - "instructions" - ], + "required": ["type", "extensions", "csrs", "instructions"], "allOf": [ { "if": { "properties": { - "type": { "enum": ["fully configured"]} + "type": { "enum": ["fully configured"] } } }, "then": { @@ -111,7 +106,7 @@ "profile_releases": { "type": "object", "items": { - "type": "string" + "type": "string" } }, "manuals": { diff --git a/schemas/config_schema.json b/schemas/config_schema.json index 493e5b157..179bd4d41 100644 --- a/schemas/config_schema.json +++ b/schemas/config_schema.json @@ -35,10 +35,7 @@ "properties": { "XLEN": { "type": "integer", - "enum": [ - 32, - 64 - ], + "enum": [32, 64], "description": "Base instruction set datapath width (e.g., RV32 or RV64)\n" }, "NAME": { @@ -52,7 +49,7 @@ }, "M_MODE_ENDIANESS": { "type": "integer", - "enum": [ 0, 1, 2], + "enum": [0, 1, 2], "description": "Endianess of data in M-mode. Can be one of:\n\n * 0: M-mode data is always little endian\n * 1: M-mode data is always big endian\n * 2: M-mode data can be either little or big endian, depending on the RW CSR field mstatus.MBE\n" }, "S_MODE_ENDIANESS": { @@ -390,8 +387,6 @@ "description": "When true, vstval is written with the casue when a SoftwareCheck exception occurs.\nWhen false, vstval is written with 0" }, - - "CONFIG_PTR_ADDRESS": { "type": "integer", "minimum": 0, @@ -510,10 +505,7 @@ } }, "type": "object", - "required": [ - "params", - "extensions" - ], + "required": ["params", "extensions"], "properties": { "params": { "$ref": "#/$defs/params" diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 78ee09fee..92b53160b 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -164,7 +164,16 @@ }, "csr_register": { "type": "object", - "required": ["$schema", "kind", "name", "long_name", "length", "description", "priv_mode", "definedBy"], + "required": [ + "$schema", + "kind", + "name", + "long_name", + "length", + "description", + "priv_mode", + "definedBy" + ], "properties": { "$schema": { @@ -202,11 +211,11 @@ "type": "object", "description": "A full Asciidoc description of the CSR, intended to be used as documentation.", "properties": { - "$copy" : { - "type": "string", - "format": "uri-reference" - } - }, + "$copy": { + "type": "string", + "format": "uri-reference" + } + }, "additionalProperties": false } ] @@ -230,7 +239,8 @@ "default": false, "description": "Whether or not the CSR is accessible via an indirect address" }, - "virtual_address": true, "$comment": "Conditionally required; see below", + "virtual_address": true, + "$comment": "Conditionally required; see below", "priv_mode": { "enum": ["M", "S", "U", "VS"] }, diff --git a/schemas/ext_schema.json b/schemas/ext_schema.json index 79c38d4b4..2a2694f60 100644 --- a/schemas/ext_schema.json +++ b/schemas/ext_schema.json @@ -39,7 +39,14 @@ }, "ext_data": { "type": "object", - "required": ["$schema", "kind", "name", "description", "long_name", "versions"], + "required": [ + "$schema", + "kind", + "name", + "description", + "long_name", + "versions" + ], "properties": { "$schema": { "type": "string", @@ -101,7 +108,12 @@ "description": "Extension(s) that conflict with this extension; both cannot be implemented at the same time", "oneOf": [ { "$ref": "schema_defs.json#/$defs/extension_requirement" }, - { "type": "array", "items": { "$ref": "schema_defs.json#/$defs/extension_requirement" }} + { + "type": "array", + "items": { + "$ref": "schema_defs.json#/$defs/extension_requirement" + } + } ] }, "versions": { @@ -109,16 +121,16 @@ "items": { "type": "object", "required": ["version", "state"], - "if": { - "properties": { - "state": { - "const": "ratified" - } + "if": { + "properties": { + "state": { + "const": "ratified" } - }, - "then": { - "required": ["ratification_date"] - }, + } + }, + "then": { + "required": ["ratification_date"] + }, "properties": { "version": { "$ref": "schema_defs.json#/$defs/extension_version" @@ -147,10 +159,17 @@ }, "ratification_date": { "oneOf": [ - {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", - "description": "A specific year and month in YYYY-MM format", "examples": ["2019-01", "2024-12"] }, - {"type": "string", "pattern": "^unknown$", "$comment": "When ratification date is unknown" }, - {"type": "null", "$comment": "When version isn't ratified" } + { + "type": "string", + "pattern": "^20[0-9][0-9]-[0-9][0-9]$", + "$comment": "When ratification date is known" + }, + { + "type": "string", + "pattern": "^unknown$", + "$comment": "When ratification date is unknown" + }, + { "type": "null", "$comment": "When version isn't ratified" } ] }, "changes": { @@ -160,12 +179,23 @@ }, "description": "Changes since last version" }, - "url": { "type": "string", "format": "uri", "description": "Link to ratified document" }, + "url": { + "type": "string", + "format": "uri", + "description": "Link to ratified document" + }, "implies": { "description": "Extension(s) implied by this extension (i.e., any subextensions)", "oneOf": [ - { "$ref": "schema_defs.json#/$defs/extension_name_and_version" }, - { "type": "array", "items": { "$ref": "schema_defs.json#/$defs/extension_name_and_version" }} + { + "$ref": "schema_defs.json#/$defs/extension_name_and_version" + }, + { + "type": "array", + "items": { + "$ref": "schema_defs.json#/$defs/extension_name_and_version" + } + } ] }, "requires": { diff --git a/schemas/inst_schema.json b/schemas/inst_schema.json index ac1c0082d..6a54ffd9b 100644 --- a/schemas/inst_schema.json +++ b/schemas/inst_schema.json @@ -50,7 +50,7 @@ "description": "Specific value(s) that are not permitted for this field." } }, - "required": [ "location" ], + "required": ["location"], "additionalProperties": false }, "field": { @@ -146,7 +146,16 @@ }, "inst_data": { "type": "object", - "required": ["$schema", "kind", "name", "long_name", "description", "definedBy", "access", "assembly"], + "required": [ + "$schema", + "kind", + "name", + "long_name", + "description", + "definedBy", + "access", + "assembly" + ], "additionalProperties": false, "properties": { "$schema": { @@ -278,5 +287,5 @@ } }, - "$ref": "#/$defs/inst_data" + "$ref": "#/$defs/inst_data" } diff --git a/schemas/json-schema-draft-07.json b/schemas/json-schema-draft-07.json index 3f39fddaf..252199ee5 100644 --- a/schemas/json-schema-draft-07.json +++ b/schemas/json-schema-draft-07.json @@ -3,243 +3,240 @@ "$id": "http://json-schema.org/draft-07/schema#", "title": "Core schema meta-schema", "definitions": { - "schemaArray": { - "type": "array", - "minItems": 1, - "items": { - "$ref": "#" - } - }, - "nonNegativeInteger": { - "type": "integer", - "minimum": 0 - }, - "nonNegativeIntegerDefault0": { - "allOf": [ - { - "$ref": "#/definitions/nonNegativeInteger" - }, - { - "default": 0 - } - ] - }, - "simpleTypes": { - "enum": [ - "array", - "boolean", - "integer", - "null", - "number", - "object", - "string" - ] - }, - "stringArray": { - "type": "array", - "items": { - "type": "string" - }, - "uniqueItems": true, - "default": [] + "schemaArray": { + "type": "array", + "minItems": 1, + "items": { + "$ref": "#" } - }, - "type": [ - "object", - "boolean" - ], - "properties": { - "$id": { - "type": "string", - "format": "uri-reference" - }, - "$schema": { - "type": "string", - "format": "uri" - }, - "$ref": { - "type": "string", - "format": "uri-reference" - }, - "$comment": { - "type": "string" - }, - "title": { - "type": "string" - }, - "description": { - "type": "string" - }, - "default": true, - "readOnly": { - "type": "boolean", - "default": false - }, - "writeOnly": { - "type": "boolean", - "default": false - }, - "examples": { - "type": "array", - "items": true - }, - "multipleOf": { - "type": "number", - "exclusiveMinimum": 0 - }, - "maximum": { - "type": "number" - }, - "exclusiveMaximum": { - "type": "number" - }, - "minimum": { - "type": "number" - }, - "exclusiveMinimum": { - "type": "number" - }, - "maxLength": { + }, + "nonNegativeInteger": { + "type": "integer", + "minimum": 0 + }, + "nonNegativeIntegerDefault0": { + "allOf": [ + { "$ref": "#/definitions/nonNegativeInteger" - }, - "minLength": { - "$ref": "#/definitions/nonNegativeIntegerDefault0" - }, - "pattern": { - "type": "string", - "format": "regex" - }, - "additionalItems": { - "$ref": "#" - }, + }, + { + "default": 0 + } + ] + }, + "simpleTypes": { + "enum": [ + "array", + "boolean", + "integer", + "null", + "number", + "object", + "string" + ] + }, + "stringArray": { + "type": "array", "items": { - "anyOf": [ - { - "$ref": "#" - }, - { - "$ref": "#/definitions/schemaArray" - } - ], - "default": true - }, - "maxItems": { - "$ref": "#/definitions/nonNegativeInteger" - }, - "minItems": { - "$ref": "#/definitions/nonNegativeIntegerDefault0" - }, - "uniqueItems": { - "type": "boolean", - "default": false + "type": "string" }, - "contains": { + "uniqueItems": true, + "default": [] + } + }, + "type": ["object", "boolean"], + "properties": { + "$id": { + "type": "string", + "format": "uri-reference" + }, + "$schema": { + "type": "string", + "format": "uri" + }, + "$ref": { + "type": "string", + "format": "uri-reference" + }, + "$comment": { + "type": "string" + }, + "title": { + "type": "string" + }, + "description": { + "type": "string" + }, + "default": true, + "readOnly": { + "type": "boolean", + "default": false + }, + "writeOnly": { + "type": "boolean", + "default": false + }, + "examples": { + "type": "array", + "items": true + }, + "multipleOf": { + "type": "number", + "exclusiveMinimum": 0 + }, + "maximum": { + "type": "number" + }, + "exclusiveMaximum": { + "type": "number" + }, + "minimum": { + "type": "number" + }, + "exclusiveMinimum": { + "type": "number" + }, + "maxLength": { + "$ref": "#/definitions/nonNegativeInteger" + }, + "minLength": { + "$ref": "#/definitions/nonNegativeIntegerDefault0" + }, + "pattern": { + "type": "string", + "format": "regex" + }, + "additionalItems": { + "$ref": "#" + }, + "items": { + "anyOf": [ + { "$ref": "#" + }, + { + "$ref": "#/definitions/schemaArray" + } + ], + "default": true + }, + "maxItems": { + "$ref": "#/definitions/nonNegativeInteger" + }, + "minItems": { + "$ref": "#/definitions/nonNegativeIntegerDefault0" + }, + "uniqueItems": { + "type": "boolean", + "default": false + }, + "contains": { + "$ref": "#" + }, + "maxProperties": { + "$ref": "#/definitions/nonNegativeInteger" + }, + "minProperties": { + "$ref": "#/definitions/nonNegativeIntegerDefault0" + }, + "required": { + "$ref": "#/definitions/stringArray" + }, + "additionalProperties": { + "$ref": "#" + }, + "definitions": { + "type": "object", + "additionalProperties": { + "$ref": "#" }, - "maxProperties": { - "$ref": "#/definitions/nonNegativeInteger" - }, - "minProperties": { - "$ref": "#/definitions/nonNegativeIntegerDefault0" - }, - "required": { - "$ref": "#/definitions/stringArray" - }, + "default": {} + }, + "properties": { + "type": "object", "additionalProperties": { - "$ref": "#" + "$ref": "#" }, - "definitions": { - "type": "object", - "additionalProperties": { - "$ref": "#" - }, - "default": {} + "default": {} + }, + "patternProperties": { + "type": "object", + "additionalProperties": { + "$ref": "#" }, - "properties": { - "type": "object", - "additionalProperties": { - "$ref": "#" - }, - "default": {} + "propertyNames": { + "format": "regex" }, - "patternProperties": { - "type": "object", - "additionalProperties": { - "$ref": "#" - }, - "propertyNames": { - "format": "regex" + "default": {} + }, + "dependencies": { + "type": "object", + "additionalProperties": { + "anyOf": [ + { + "$ref": "#" }, - "default": {} - }, - "dependencies": { - "type": "object", - "additionalProperties": { - "anyOf": [ - { - "$ref": "#" - }, - { - "$ref": "#/definitions/stringArray" - } - ] + { + "$ref": "#/definitions/stringArray" } - }, - "propertyNames": { - "$ref": "#" - }, - "const": true, - "enum": { + ] + } + }, + "propertyNames": { + "$ref": "#" + }, + "const": true, + "enum": { + "type": "array", + "items": true, + "minItems": 1, + "uniqueItems": true + }, + "type": { + "anyOf": [ + { + "$ref": "#/definitions/simpleTypes" + }, + { "type": "array", - "items": true, + "items": { + "$ref": "#/definitions/simpleTypes" + }, "minItems": 1, "uniqueItems": true - }, - "type": { - "anyOf": [ - { - "$ref": "#/definitions/simpleTypes" - }, - { - "type": "array", - "items": { - "$ref": "#/definitions/simpleTypes" - }, - "minItems": 1, - "uniqueItems": true - } - ] - }, - "format": { - "type": "string" - }, - "contentMediaType": { - "type": "string" - }, - "contentEncoding": { - "type": "string" - }, - "if": { - "$ref": "#" - }, - "then": { - "$ref": "#" - }, - "else": { - "$ref": "#" - }, - "allOf": { - "$ref": "#/definitions/schemaArray" - }, - "anyOf": { - "$ref": "#/definitions/schemaArray" - }, - "oneOf": { - "$ref": "#/definitions/schemaArray" - }, - "not": { - "$ref": "#" - } + } + ] + }, + "format": { + "type": "string" + }, + "contentMediaType": { + "type": "string" + }, + "contentEncoding": { + "type": "string" + }, + "if": { + "$ref": "#" + }, + "then": { + "$ref": "#" + }, + "else": { + "$ref": "#" + }, + "allOf": { + "$ref": "#/definitions/schemaArray" + }, + "anyOf": { + "$ref": "#/definitions/schemaArray" + }, + "oneOf": { + "$ref": "#/definitions/schemaArray" + }, + "not": { + "$ref": "#" + } }, "default": true } diff --git a/schemas/manual_version_schema.json b/schemas/manual_version_schema.json index e6b6320d5..e9de71045 100644 --- a/schemas/manual_version_schema.json +++ b/schemas/manual_version_schema.json @@ -50,7 +50,14 @@ }, "type": "object", - "required": ["manual", "version", "name", "marketing_version", "state", "volumes"], + "required": [ + "manual", + "version", + "name", + "marketing_version", + "state", + "volumes" + ], "properties": { "name": { "type": "string", diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 86d57b404..df5f06eab 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -15,8 +15,12 @@ }, "field_location": { "oneOf": [ - {"type": "number", "description": "Location of a single bit"}, - {"type": "string", "pattern": "^[0-9]+-[0-9]+$", "description": "Location range of a multi-bit field"} + { "type": "number", "description": "Location of a single bit" }, + { + "type": "string", + "pattern": "^[0-9]+-[0-9]+$", + "description": "Location range of a multi-bit field" + } ], "description": "Location of a field in a register" }, @@ -58,11 +62,7 @@ "oneOf": [ { "type": "string", - "enum": [ - "mandatory", - "optional", - "prohibited" - ] + "enum": ["mandatory", "optional", "prohibited"] }, { "type": "object", @@ -138,7 +138,6 @@ "additionalProperties": false } ] - }, "requires_entry": { "oneOf": [