diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 019117fb8..7886344e5 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -100,6 +100,7 @@ description: | with both bits clear, but may result in lower performance. definedBy: anyOf: [A, Zalrsc] +base: 64 assembly: xd, xs2, xs1 encoding: match: 00011------------011-----0101111 diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index d5e22cd25..aea69c211 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -11,6 +11,7 @@ description: | If the value in rs2 is zero, rd is written with all 1s. definedBy: M +base: 64 assembly: xd, xs1, xs2 encoding: match: 0000001----------101-----0111011 diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 13031feb0..1f180a746 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -15,6 +15,7 @@ description: | Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd; definedBy: M +base: 64 assembly: xd, xs1, xs2 encoding: match: 0000001----------100-----0111011 diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index d2a24afee..a839db862 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -17,6 +17,7 @@ description: | an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U]. definedBy: anyOf: [M, Zmmul] +base: 64 assembly: xd, xs1, xs2 encoding: match: 0000001----------000-----0111011 diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index c765fa4a6..d6eac0d02 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -10,6 +10,7 @@ description: | If the value in rs2 is zero, rd gets the sign-extended value in rs1. definedBy: M +base: 64 assembly: xd, xs1, xs2 encoding: match: 0000001----------111-----0111011 diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index f03753412..1418819ec 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -12,6 +12,7 @@ description: | If the result of the division overflows, write zero into rd; definedBy: M +base: 64 assembly: xd, xs1, xs2 encoding: match: 0000001----------110-----0111011