Merge pull request #266 from kbroch-rivosinc/dev/kbroch/pre-commit-in…

…itial-cfg

initial pre-commit config

.devcontainer/onCreateCommand.sh

@@ -1,4 +1,4 @@
 #!/bin/bash
 
-npm i 
+npm i
 bundle install

.pre-commit-config.yaml

@@ -0,0 +1,14 @@
+---
+exclude: ^docs/ruby/ # All generated code
+
+repos:
+  - repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v5.0.0
+    hooks:
+      - id: check-symlinks
+      - id: end-of-file-fixer
+      - id: trailing-whitespace
+        args: [--markdown-linebreak-ext=md]
+      - id: check-merge-conflict
+        args: ["--assume-in-merge"]
+        exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise

LICENSE

@@ -18,7 +18,7 @@ met:
 NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS
 SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS 
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
 BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

Rakefile

@@ -98,7 +98,7 @@ namespace :test do
       validator.validate(f)
     end
     Rake::Task["test:insts"].invoke
-    puts "All files validate against their schema"  
+    puts "All files validate against their schema"
   end
   task idl_model: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"]  do
     print "Parsing IDL code for RV32..."
@@ -298,7 +298,7 @@ namespace :test do
     ENV["MANUAL_NAME"] = "isa"
     ENV["VERSIONS"] = "all"
     Rake::Task["gen:html_manual"].invoke
-    
+
     ENV["EXT"] = "B"
     ENV["VERSION"] = "latest"
     Rake::Task["gen:ext_pdf"].invoke
@@ -371,4 +371,4 @@ namespace :gen do
     puts "==================================="
     Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke
   end
-end
+end

arch/README.adoc

@@ -21,7 +21,7 @@ To tame this challenge, this specification generator takes the following approac
 
 The architecture is specified in a series of https://en.wikipedia.org/wiki/YAML[YAML]
 files for _Extensions_, _Instructions_, and _Control and Status Registers (CSRs)_.
-Each extension/instruction/CSR has its own file. 
+Each extension/instruction/CSR has its own file.
 
 == Flow
 

arch/certificate_class/MC.yaml

@@ -21,12 +21,12 @@ naming_scheme: |
 
   Where:
 
-  * Left & right square braces denote optional. 
+  * Left & right square braces denote optional.
   * \<model> is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD.
   ** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond)
   ** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP)
   ** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H)
-  * \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions. 
+  * \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions.
   ** A <major> release indicates support for a new optional extension.
   ** A <minor> release indicates one or more of the following changes to the certification tests associated with the CRD.
   *** Fix test bug or increase test coverage
@@ -35,4 +35,4 @@ naming_scheme: |
   ** A <patch> release indicates just CRD specification changes without any difference in functional behavior
 
 mandatory_priv_modes:
-- M
+- M

arch/certificate_model/MC100.yaml

@@ -8,7 +8,7 @@ class:
   $ref: certificate_class/MC.yaml#
 
 # Semantic versions within the model
-versions: 
+versions:
 - version: "1.0.0"
 
 # XLEN used by rakefile
@@ -139,4 +139,4 @@ extensions:
             const: little
         XLEN:
           schema:
-            const: 32
+            const: 32

arch/certificate_model/MockCertificateModel.yaml

@@ -13,7 +13,7 @@ base: 64
 # Semantic versions within the model
 versions:
   - version: "1.0.0"
-  - version: "1.1.0"  
+  - version: "1.1.0"
 
 revision_history:
 - revision: "0.1.0"
@@ -223,4 +223,4 @@ recommendations:
 - text: |
     Implementations are strongly recommended to raise illegal-instruction
     exceptions on attempts to execute unimplemented opcodes.
-- text: Micky should give Pluto an extra treat
+- text: Micky should give Pluto an extra treat

arch/csr/F/fcsr.yaml

@@ -42,7 +42,7 @@ description: |
   modes are encoded as shown in <<rm>>. A value of 111 in the
   instruction's _rm_ field selects the dynamic rounding mode held in
   `frm`. The behavior of floating-point instructions that depend on
-  rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to 
+  rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to
   RNE (000) but implementations must treat the _rm_ field as usual (in
   particular, with regard to decoding legal vs. reserved encodings).
 
@@ -122,7 +122,7 @@ fields:
       including both static reserved rounding modes (101-110) and dynamic reserved
       rounding modes (101-111). Some instructions, including widening conversions,
       have the _rm_ field but are nevertheless mathematically unaffected by the
-      rounding mode; software should set their _rm_ field to 
+      rounding mode; software should set their _rm_ field to
       RNE (000) but implementations must treat the _rm_ field as usual (in
       particular, with regard to decoding legal vs. reserved encodings).
     type: RW-H
@@ -181,4 +181,4 @@ fields:
       Set by hardware when a floating point operation is inexact and stays set until explicitly
       cleared by software.
     type: RW-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value: UNDEFINED_LEGAL

arch/csr/H/henvcfg.yaml

@@ -12,7 +12,7 @@ description: |
   If bit `henvcfg.FIOM` (Fence of I/O implies Memory) is set to one in henvcfg, `fence`
   instructions executed when V=1 are modified so the requirement to order accesses to device I/O
   implies also the requirement to order main memory accesses.
-  
+
   <<henvcfg-FIOM>> details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when
   FIOM=1 and V=1.
 
@@ -71,7 +71,7 @@ description: |
   The Zicfiss extension adds the `SSE` field in `henvcfg`. If the `SSE` field is
   set to 1, the Zicfiss extension is activated in VS-mode. When the `SSE` field is
   0, the Zicfiss extension remains inactive in VS-mode, and the following rules
-  apply when `V=1`: 
+  apply when `V=1`:
 
   * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
   * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
@@ -127,12 +127,12 @@ fields:
 
       The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage
       address translation.
-      
+
       When PBMTE=1, Svpbmt is available for VS-stage address translation.
-      
+
       When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for
       VS-stage address translation.
-      
+
       If `Svpbmt` is not implemented, PBMTE is read-only zero.
 
       `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero.
@@ -141,7 +141,7 @@ fields:
       _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation
       of G-stage and VS-stage PTEs' PBMT fields.
 
-      By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with 
+      By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with
       _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation
       of VS-stage PTEs' PBMT fields for the currently active VMID.
 
@@ -165,14 +165,14 @@ fields:
     description: |
       If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of
       PTE A/D bits is enabled for VS-stage address translation.
-      
+
       When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address
       translation, and the implementation behaves as though the Svade extension were not
       implemented for VS-mode address translation.
-      
+
       When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage
       address translation.
-      
+
       If Svadu is not implemented, ADUE is read-only zero.
 
       Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only
@@ -287,4 +287,4 @@ sw_read(): |
     # henvcfg.ADUE must read-as-zero
     value = value & ~(1 << 61);
   }
-  return value;
+  return value;

arch/csr/H/henvcfgh.yaml

@@ -47,12 +47,12 @@ fields:
 
       The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage
       address translation.
-      
+
       When PBMTE=1, Svpbmt is available for VS-stage address translation.
-      
+
       When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for
       VS-stage address translation.
-      
+
       If `Svpbmt` is not implemented, PBMTE is read-only zero.
 
       `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero.
@@ -61,7 +61,7 @@ fields:
       _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation
       of G-stage and VS-stage PTEs' PBMT fields.
 
-      By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with 
+      By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with
       _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation
       of VS-stage PTEs' PBMT fields for the currently active VMID.
 
@@ -86,14 +86,14 @@ fields:
     description: |
       If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of
       PTE A/D bits is enabled for VS-stage address translation.
-      
+
       When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address
       translation, and the implementation behaves as though the Svade extension were not
       implemented for VS-mode address translation.
-      
+
       When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage
       address translation.
-      
+
       If Svadu is not implemented, ADUE is read-only zero.
 
       Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only
@@ -104,4 +104,4 @@ fields:
     reset_value(): |
       return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;
 sw_read(): |
-  return CSR[henvcfg].sw_read()[63:32];
+  return CSR[henvcfg].sw_read()[63:32];

arch/csr/H/hgatp.yaml

@@ -225,12 +225,12 @@ fields:
       return csr_value.PPN;
 
 sw_read(): |
-  if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4)) 
+  if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4))
       || (CSR[hgatp].MODE == $bits(HgatpMode::Sv39x4))
       || (CSR[hgatp].MODE == $bits(HgatpMode::Sv48x4))
       || (CSR[hgatp].MODE == $bits(HgatpMode::Sv57x4))) {
     # bits 1:0 of PPN read as zero
     return $bits(CSR[hgatp]) & ~64'h3;
   } else {
     return $bits(CSR[hgatp]);
-  }
+  }

arch/csr/H/vsatp.yaml

@@ -127,7 +127,7 @@ fields:
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       if (csr_value.MODE == 0) {
-        if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) {          
+        if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) {
           # when MODE == Bare, PPN and ASID must be zero
           if (csr_value.ASID == 0 && csr_value.PPN == 0) {
             return csr_value.PPN;

arch/csr/I/pmpaddrN.layout

@@ -1,6 +1,6 @@
 # yaml-language-server: $schema=../../../schemas/csr_schema.json
 
-<%- 
+<%-
   raise "'pmpaddr_num' must be defined" if pmpaddr_num.nil?
   pmpcfg_num_32 = (pmpaddr_num / 4)
   pmpcfg_num_64 = (pmpaddr_num / 8)*2