[Question] Implicit sfence.vma when satp.MODE is changed from/to Bare

[atsushi-shinbo-esoltrinity]

Current value and location

riscv-unified-db/arch/csr/satp.yaml

Lines 46 to 47 in c7a9658

	# changes *to* Bare mode take effect immediately without needing sfence.vma
	# thus, an implicit sfence.vma occurs now

riscv-unified-db/arch/csr/satp.yaml

Lines 64 to 65 in c7a9658

	# changes *from* Bare mode take effect immediately without needing sfence.vma
	# thus, an implicit sfence.vma occurs now

Expected value

I would like to ask for clarification of the above statement.

The privilege spec version 20240411 makes the following two statements regarding changes to satp:

11.1.11. Supervisor Address Translation and Protection (satp) Register

Note that writing satp does not imply any ordering constraints between page-table updates and
subsequent address translations, nor does it imply any invalidation of address-translation caches. If
the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to
execute an SFENCE.VMA instruction (see Section 10.2.1) after, or in some cases before, writing satp.

11.2.1. Supervisor Memory-Management Fence Instruction

Changing satp.MODE from Bare to other modes and vice versa also takes
effect immediately, without the need to execute an SFENCE.VMA instruction. Likewise, changes to
satp.ASID take effect immediately.

• I think "Note that writing satp does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches" is conflicted with the statements in riscv-unified-db above.

• I interpret this to mean that turning mapping off by switching to bare mode takes effect immediately, i.e. it disables the mapping without a fence, but then switching back to a non-bare mode enables mapping while retaining the state that existed before it was switched to bare.

In general, the software has to execute SFENCE.VMA explicitly when changing satp CSR, i.e. no implicit TLB flush is performed when changing satp.ASID and satp.PPN. However, the RISC-V privilege spec does not describe the implicit SFENCE.VMA when changing satp.MODE from/to Bare.

So, I want to clarify this.

[ThinkOpenly]

This probably isn't the best place for this question, which seeks clarification of ISA content. This project is really about quantifying that content into a machine-readable database.

I suggest posted to the "ISA-dev" mailing list: https://groups.google.com/u/0/a/groups.riscv.org/g/isa-dev.

[atsushi-shinbo-esoltrinity]

@dhower-qc

I understood that this repository is about quantifying into a machine-readable database and is not the right place to discuss about RISC-V ISA.

If you know I'd like to ask.
The following description is committed by you, but where do this description come from ?
https://github.com/riscv-software-src/riscv-unified-db/blame/c7a9658554dbb2c627387902a44b8bb0ed605aef/arch/csr/satp.yaml#L64-L65

[dhower-qc]

Priv Section 10.2.1 "Supervisor Memory-Management Fence Instruction":

Changing satp.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction.