xcause CSRs are listing exception and interrupt codes not available in their privilege level

[james-ball-qualcomm]

The scause CSR shouldn't be showing M-mode only exception and interrupt codes. I assume the same is true for the vscause CSR showing HS-mode. This is because all the xcause CSRs are using the same adoc code (that doesn't specify the privilege level) when calling arch_def.interrupt_codes() and arch_def.exception_codes().

     `scause.CODE` is writeable.

      [when,"TRAP_ON_ILLEGAL_WLRL == true"]
      If `scause` is written with an undefined cause (combination of `scause.INT` and `scause.CODE`), an `Illegal Instruction` exception occurs.

      [when,"TRAP_ON_ILLEGAL_WLRL == false"]
      If `scause` is written with an undefined cause (combination of `scause.INT` and `scause.CODE`), neither `scause.INT` nor `scause.CODE` are modified.

      Valid interrupt codes are:
      [separator="!"]
      !===
      <%- interrupt_codes.sort_by { |code| code.num }.each do |code| -%>
      ! <%= code.num %> ! <%= code.name %>
      <%- end -%>
      !===

      Valid exception codes are:
      [separator="!"]
      !===
      <%- exception_codes.sort_by { |code| code.num }.each do |code| -%>
      ! <%= code.num %> ! <%= code.name %>
      <%- end -%>
      !===