diff --git a/arch/inst/C/c.lui.yaml b/arch/inst/C/c.lui.yaml
index ffba4e470..ccdca54c5 100644
--- a/arch/inst/C/c.lui.yaml
+++ b/arch/inst/C/c.lui.yaml
@@ -3,9 +3,9 @@
 c.lui:
   long_name: Load the non-zero 6-bit immediate field into bits 17–12 of the destination register
   description: |
-    C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. 
-    C.LUI expands into `lui rd, imm`. 
-    C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero. 
+    C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination.
+    C.LUI expands into `lui rd, imm`.
+    C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero.
     The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction
   definedBy:
     anyOf:
@@ -20,8 +20,7 @@ c.lui:
       left_shift: 12
     - name: rd
       location: 11-7
-      not: 0
-      not: 2
+      not: [0, 2]
   access:
     s: always
     u: always
@@ -33,4 +32,3 @@ c.lui:
     }
 
     X[rd] = imm;
-
diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb
index 92c9a7640..8daaa54be 100644
--- a/lib/arch_obj_models/instruction.rb
+++ b/lib/arch_obj_models/instruction.rb
@@ -289,7 +289,7 @@ def pretty_name
       elsif excludes.size == 1
         "#{name} != #{excludes[0]}"
       else
-        "#{name} != {#{excludes[0].join(',')}}"
+        "#{name} != {#{excludes.join(',')}}"
       end
     end