From 208b99f5ba47fb811b8a45b35d1859d46dd53c3f Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Tue, 15 Oct 2024 12:15:40 +0200 Subject: [PATCH] sort out extensions xrefs --- src/cap-description.adoc | 2 +- src/cheri-pte-ext.adoc | 1 + src/debug-integration.adoc | 2 +- src/insns/acperm_32bit.adoc | 2 +- src/introduction.adoc | 30 +++++++++++++++--------------- src/level-ext.adoc | 2 +- src/tables.adoc | 6 +++++- src/tid-ext.adoc | 1 + 8 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/cap-description.adoc b/src/cap-description.adoc index dd700c45..7085a897 100644 --- a/src/cap-description.adoc +++ b/src/cap-description.adoc @@ -248,7 +248,7 @@ permission. | 6 | <>^1^ | 7 | <>^1^ |============================================================================== -^1^ This permission is only supported if the implementation supports <>. +^1^ This permission is only supported if the implementation supports <>. The <> is only assigned meaning when the implementation supports {cheri_default_ext_name} _and_ <> is set. diff --git a/src/cheri-pte-ext.adoc b/src/cheri-pte-ext.adoc index ebe937bd..cc0d8314 100644 --- a/src/cheri-pte-ext.adoc +++ b/src/cheri-pte-ext.adoc @@ -1,4 +1,5 @@ [#section_sv_cheri] +[#cheri_pte_ext] == "{cheri_pte_ext_name}" Extension for CHERI Page-Based Virtual-Memory Systems CHERI is a security mechanism that is generally orthogonal to page-based diff --git a/src/debug-integration.adoc b/src/debug-integration.adoc index 6a2f653a..98923633 100644 --- a/src/debug-integration.adoc +++ b/src/debug-integration.adoc @@ -181,7 +181,7 @@ If {cheri_default_ext_name} is implemented: * The <> is reset to {cheri_int_mode_name} ({INT_MODE_VALUE}). * The debugger can set the <> to {cheri_cap_mode_name} ({CAP_MODE_VALUE}) by executing <> from the program buffer. -** Executing <> causes subsequent instruction execution from the program buffer, starting from the next instruction, to be executed in {cheri_cap_mode_name}. It also sets the CHERI execution mode to {cheri_cap_mode_name} on future entry into debug mode. +** Executing <> causes subsequent instructions execution from the program buffer, starting from the next instruction, to be executed in {cheri_cap_mode_name}. It also sets the CHERI execution mode to {cheri_cap_mode_name} on future entry into debug mode. ** Therefore to enable use of a CHERI debugger, a single <> only needs to be executed once from the program buffer after resetting the core. ** The debugger can also execute <> to change the mode back to {cheri_int_mode_name}, which also affects the execution of the next instruction in the program buffer, updates the <> of <> and controls which CHERI execution mode to enter on the next entry into debug mode. diff --git a/src/insns/acperm_32bit.adoc b/src/insns/acperm_32bit.adoc index 346cbd4c..100646a4 100644 --- a/src/insns/acperm_32bit.adoc +++ b/src/insns/acperm_32bit.adoc @@ -68,7 +68,7 @@ The MXLEN=32 additional rules are: [#acperm_bit_field] include::../img/acperm_bit_field.edn[] -NOTE: The <>, <> and <> fields are only defined if the implementation supports <>. +NOTE: The <>, <> and <> fields are only defined if the implementation supports <>. NOTE: Even though being included here <> is not considered an architectural permission. diff --git a/src/introduction.adoc b/src/introduction.adoc index 53192c3b..b51dc3d9 100644 --- a/src/introduction.adoc +++ b/src/introduction.adoc @@ -81,20 +81,20 @@ This specification is based on publicly available documentation including cite:[cheri-v9-spec] and cite:[woodruff2019cheri]. It defines the following extensions to support CHERI alongside RISC-V: -{cheri_base_ext_name}:: Introduces key, minimal CHERI concepts and features to +<>:: Introduces key, minimal CHERI concepts and features to the RISC-V ISA. The resulting extended ISA is not backwards-compatible with RISC-V. -{cheri_default_ext_name}:: Extends {cheri_base_ext_name} with features to ensure +<>:: Extends {cheri_base_ext_name} with features to ensure that the ISA extended with CHERI allows backwards binary compatibility with RISC-V. -{sh4add_ext_name}:: Addition of <> and <> for RV64 only, as CHERI capabilities are 16 bytes when XLEN=64 -{lr_sc_bh_ext_name}:: Addition of <>, <>, <>, <> for more accurate atomic locking as the memory ranges are restricted by using bounds, therefore precise locking is needed. -{cheri_pte_ext_name}:: CHERI extension for RISC-V harts supporting page-based +<>:: Addition of <> and <> for RV64 only, as CHERI capabilities are 16 bytes when XLEN=64 +<>:: Addition of <>, <>, <>, <> for more accurate atomic locking as the memory ranges are restricted by using bounds, therefore precise locking is needed. +<>:: CHERI extension for RISC-V harts supporting page-based virtual-memory. -{cheri_levels_ext_name}:: Extension for supporting capability flow control. -This extension allows limiting storing of capabilities to specific regions and can be used e.g. for safer data sharing between compartments. -{tid_ext_name}:: Extension for supporting thread identifiers. This extension +<>:: Extension for supporting thread identifiers. This extension improves software compartmentalization on CHERI systems. +<>:: Extension for supporting capability flow control. +This extension allows limiting storing of capabilities to specific regions and can be used e.g. for safer data sharing between compartments. CAUTION: The extension names are provisional and subject to change. @@ -103,13 +103,13 @@ CAUTION: The extension names are provisional and subject to change. [options=header,align=center,width="90%",cols="25,23,52"] |============================================================================== | Extension | Status | Comment -|{cheri_base_ext_name} | Stable | This extension is a candidate for freezing -|{cheri_default_ext_name} | Stable | This extension is a candidate for freezing -|{sh4add_ext_name} | Stable | This extension is a candidate for freezing -|{lr_sc_bh_ext_name} | Stable | This extension is a candidate for freezing -|{cheri_pte_ext_name} | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level -|{tid_ext_name} | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level -|{cheri_levels_ext_name} | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level +|<> | Stable | This extension is a candidate for freezing +|<> | Stable | This extension is a candidate for freezing +|<> | Stable | This extension is a candidate for freezing +|<> | Stable | This extension is a candidate for freezing +|<> | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level +|<> | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level +|<> | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level |============================================================================== {cheri_base_ext_name} is defined as the base extension which all CHERI RISC-V diff --git a/src/level-ext.adoc b/src/level-ext.adoc index 365dfed3..522c0fce 100644 --- a/src/level-ext.adoc +++ b/src/level-ext.adoc @@ -1,4 +1,4 @@ -[#section_ext_cheri_levels] +[#cheri_levels_ext] == "{cheri_levels_ext_name}" Extension for Capability Levels {cheri_levels_ext_name} is an extension to {cheri_base_ext_name} that adds support for associating a level with capabilities and limiting the flow of capabilities to specific memory region subsets. diff --git a/src/tables.adoc b/src/tables.adoc index 98715634..9a8970e2 100644 --- a/src/tables.adoc +++ b/src/tables.adoc @@ -1,6 +1,7 @@ [appendix] == Extension summary +[#lr_sc_bh_ext] === {lr_sc_bh_ext_name} {lr_sc_bh_ext_name} is a separate extension independent of CHERI, but is required for CHERI software. @@ -14,6 +15,7 @@ These instructions are not controlled by the CRE bits in <>, < include::generated/Zabhlrsc_insns_table_body.adoc[] |============================================================================== +[#sh4add_ext] === {sh4add_ext_name} {sh4add_ext_name} is a separate extension independent of CHERI, but improves performance for CHERI code @@ -28,11 +30,12 @@ These instructions are not controlled by the CRE bits in <>, < include::generated/Zish4add_insns_table_body.adoc[] |============================================================================== +[#cheri_base_ext] === {cheri_base_ext_name} {cheri_base_ext_name} defines the set of instructions supported by a core when in {cheri_cap_mode_name}. -Some instructions depend on the presence of other extensions, as listed in xref:Zcheri_purecap_instruction_extension[xrefstyle=short] +Some instructions depend on the presence of other extensions, as listed in xref:Zcheri_purecap_instruction_extension[xrefstyle=short]. .{cheri_base_ext_name} instruction extension - Pure {cheri_cap_mode_name} instructions [#Zcheri_purecap_instruction_extension] @@ -41,6 +44,7 @@ Some instructions depend on the presence of other extensions, as listed in xref: include::generated/Zcheri_purecap_insns_table_body.adoc[] |============================================================================== +[#cheri_default_ext] === {cheri_default_ext_name} {cheri_default_ext_name} defines the set of instructions added by the {cheri_int_mode_name}, in addition to {cheri_base_ext_name}. diff --git a/src/tid-ext.adoc b/src/tid-ext.adoc index 26ed39a6..c9eec355 100644 --- a/src/tid-ext.adoc +++ b/src/tid-ext.adoc @@ -1,3 +1,4 @@ +[#tid_ext] == "{tid_ext_name}" Extension for Thread Identification {tid_ext_name} is an optional extension to the RISC-V base ISA.