Update src/riscv-integration.adoc

Signed-off-by: Alexander Richardson <[email protected]>

src/riscv-integration.adoc

@@ -330,8 +330,7 @@ two tag bits in memory.
 
 {cheri_base_ext_name} requires that RISC-V CSRs intended to hold addresses,
 are now able to hold capabilities. Therefore, such registers are
-extended to CLEN+1 bits in {cheri_base_ext_name} and a `c` suffix is added such
-as <<mtvec>> is extended to <<mtvecc>>.
+extended to CLEN+1 bits in {cheri_base_ext_name} and a `c` suffix is added (e.g. <<mtvec>> is extended to <<mtvecc>>).
 
 Reading or writing any part of a CLEN-bit CSR may cause
 side effects. For example, the CSR's tag bit may be cleared if a new address