From 5565cd7cf6b4e5c77bdc14d8472a1c91f893bab9 Mon Sep 17 00:00:00 2001 From: Nathaniel Wesley Filardo Date: Wed, 2 Oct 2024 21:33:40 +0100 Subject: [PATCH 1/4] Mark c0-authorized loads and stores as extensible --- src/insns/amo_32bit.adoc | 2 ++ src/insns/amoswap_32bit_cap.adoc | 2 ++ src/insns/hypv-virt-load-cap.adoc | 2 ++ src/insns/hypv-virt-load.adoc | 2 ++ src/insns/hypv-virt-loadx.adoc | 2 ++ src/insns/hypv-virt-store-cap.adoc | 2 ++ src/insns/hypv-virt-store.adoc | 2 ++ src/insns/load_32bit.adoc | 2 ++ src/insns/load_32bit_cap.adoc | 2 ++ src/insns/load_32bit_fp.adoc | 2 ++ src/insns/load_res_32bit.adoc | 2 ++ src/insns/load_res_cap_32bit.adoc | 2 ++ src/insns/load_store_c0.adoc | 2 ++ src/insns/store_32bit.adoc | 2 ++ src/insns/store_32bit_cap.adoc | 2 ++ src/insns/store_32bit_fp.adoc | 2 ++ src/insns/store_cond_32bit.adoc | 2 ++ src/insns/store_cond_cap_32bit.adoc | 2 ++ 18 files changed, 36 insertions(+) create mode 100644 src/insns/load_store_c0.adoc diff --git a/src/insns/amo_32bit.adoc b/src/insns/amo_32bit.adoc index 595031d9..f89e3fe1 100644 --- a/src/insns/amo_32bit.adoc +++ b/src/insns/amo_32bit.adoc @@ -30,6 +30,8 @@ include::wavedrom/amo.adoc[] {cheri_cap_mode_name} Description:: Standard atomic instructions, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Standard atomic instructions, authorised by the capability in <>. diff --git a/src/insns/amoswap_32bit_cap.adoc b/src/insns/amoswap_32bit_cap.adoc index 75940818..0bf170c2 100644 --- a/src/insns/amoswap_32bit_cap.adoc +++ b/src/insns/amoswap_32bit_cap.adoc @@ -17,6 +17,8 @@ include::wavedrom/amoswap_cap.adoc[] {cheri_cap_mode_name} Description:: Atomic swap of capability type, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Atomic swap of capability type, authorised by the capability in <>. diff --git a/src/insns/hypv-virt-load-cap.adoc b/src/insns/hypv-virt-load-cap.adoc index 8dd464af..e6f6497d 100644 --- a/src/insns/hypv-virt-load-cap.adoc +++ b/src/insns/hypv-virt-load-cap.adoc @@ -21,6 +21,8 @@ translation and protection, and endianness, that apply to memory accesses in either VS-mode or VU-mode. The effective address is the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of the loaded value is written to `cd`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Load a CLEN+1 bit value from memory as though V=1; i.e., with the address diff --git a/src/insns/hypv-virt-load.adoc b/src/insns/hypv-virt-load.adoc index a73c5106..336b8102 100644 --- a/src/insns/hypv-virt-load.adoc +++ b/src/insns/hypv-virt-load.adoc @@ -69,6 +69,8 @@ protection, and endianness, that apply to memory accesses in either VS-mode or VU-mode. The effective address is the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of the loaded value is written to `rd`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Performs a load as though V=1; i.e., with the address translation and diff --git a/src/insns/hypv-virt-loadx.adoc b/src/insns/hypv-virt-loadx.adoc index f9216529..aaea5fc3 100644 --- a/src/insns/hypv-virt-loadx.adoc +++ b/src/insns/hypv-virt-loadx.adoc @@ -31,6 +31,8 @@ translation and protection, and endianness, that apply to memory access in either VS-mode or VU-mode. The effective address is the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of the loaded value is written to `rd`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Performs a load with the *execute* permission taking the place of *read* diff --git a/src/insns/hypv-virt-store-cap.adoc b/src/insns/hypv-virt-store-cap.adoc index 2197ee89..ad892b68 100644 --- a/src/insns/hypv-virt-store-cap.adoc +++ b/src/insns/hypv-virt-store-cap.adoc @@ -22,6 +22,8 @@ accesses in either VS-mode or VU-mode. The effective address is the address of `cs1`. The authorising capability for the operation is `cs1`. The capability written to memory has the tag set to 0 if the tag of `cs2` is 0 or `cs1` does not grant <>. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the diff --git a/src/insns/hypv-virt-store.adoc b/src/insns/hypv-virt-store.adoc index c8748858..db71d367 100644 --- a/src/insns/hypv-virt-store.adoc +++ b/src/insns/hypv-virt-store.adoc @@ -55,6 +55,8 @@ VU-mode. The effective address is the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of `rs2` is written to memory at the location indicated by the effective address and the tag bit of each block of memory naturally aligned to CLEN/8 is cleared. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Performs a store as though V=1; i.e., with address translation and protection, diff --git a/src/insns/load_32bit.adoc b/src/insns/load_32bit.adoc index 7a4c2982..a58a6c42 100644 --- a/src/insns/load_32bit.adoc +++ b/src/insns/load_32bit.adoc @@ -68,6 +68,8 @@ Load integer data of the indicated size (byte, halfword, word, double-word) from memory. The effective address of the load is obtained by adding the sign-extended 12-bit offset to the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of the loaded value is written to `rd`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Load integer data of the indicated size (byte, halfword, word, double-word) diff --git a/src/insns/load_32bit_cap.adoc b/src/insns/load_32bit_cap.adoc index 7f822aa8..f1827a1c 100644 --- a/src/insns/load_32bit_cap.adoc +++ b/src/insns/load_32bit_cap.adoc @@ -21,6 +21,8 @@ include::wavedrom/loadcap.adoc[] {cheri_cap_mode_name} Description:: Load a CLEN+1 bit value from memory and writes it to `cd`. The capability in `cs1` authorizes the operation. The effective address of the memory access is obtained by adding the address of `cs1` to the sign-extended 12-bit offset. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Loads a CLEN+1 bit value from memory and writes it to `cd`. The capability diff --git a/src/insns/load_32bit_fp.adoc b/src/insns/load_32bit_fp.adoc index 5cc78ffa..334dc890 100644 --- a/src/insns/load_32bit_fp.adoc +++ b/src/insns/load_32bit_fp.adoc @@ -31,6 +31,8 @@ include::wavedrom/fpload.adoc[] {cheri_cap_mode_name} Description:: Standard floating point load instructions, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Standard floating point load instructions, authorised by the capability in <>. diff --git a/src/insns/load_res_32bit.adoc b/src/insns/load_res_32bit.adoc index 60cfb807..0fbe05c3 100644 --- a/src/insns/load_res_32bit.adoc +++ b/src/insns/load_res_32bit.adoc @@ -37,6 +37,8 @@ include::wavedrom/load_res.adoc[] {cheri_cap_mode_name} Description:: Load reserved instructions, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Load reserved instructions, authorised by the capability in <>. diff --git a/src/insns/load_res_cap_32bit.adoc b/src/insns/load_res_cap_32bit.adoc index 44996197..e9a2ebf7 100644 --- a/src/insns/load_res_cap_32bit.adoc +++ b/src/insns/load_res_cap_32bit.adoc @@ -18,6 +18,8 @@ include::wavedrom/load_res_cap.adoc[] {cheri_cap_mode_name} Description:: Load reserved instructions, authorised by the capability in `cs1`. All misaligned load reservations cause a load address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]). ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Load reserved instructions, authorised by the capability in <>. diff --git a/src/insns/load_store_c0.adoc b/src/insns/load_store_c0.adoc new file mode 100644 index 00000000..5bed46a8 --- /dev/null +++ b/src/insns/load_store_c0.adoc @@ -0,0 +1,2 @@ +Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <>. +As such, these forms should be considered available for use by future extensions. diff --git a/src/insns/store_32bit.adoc b/src/insns/store_32bit.adoc index 998cd217..49f02245 100644 --- a/src/insns/store_32bit.adoc +++ b/src/insns/store_32bit.adoc @@ -55,6 +55,8 @@ sign-extended 12-bit offset to the address of `cs1`. The authorising capability for the operation is `cs1`. A copy of `rs2` is written to memory at the location indicated by the effective address and the tag bit of each block of memory naturally aligned to CLEN/8 is cleared. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Store integer data of the indicated size (byte, halfword, word, double-word) to diff --git a/src/insns/store_32bit_cap.adoc b/src/insns/store_32bit_cap.adoc index d5a9e695..a41aeb3a 100644 --- a/src/insns/store_32bit_cap.adoc +++ b/src/insns/store_32bit_cap.adoc @@ -23,6 +23,8 @@ authorizes the operation. The effective address of the memory access is obtained by adding the address of `cs1` to the sign-extended 12-bit offset. The capability written to memory has the tag set to 0 if the tag of `cs2` is 0 or `cs1` does not grant <>. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Store the CLEN+1 bit value in `cs2` to memory. The capability diff --git a/src/insns/store_32bit_fp.adoc b/src/insns/store_32bit_fp.adoc index 502f6666..2ab24c3a 100644 --- a/src/insns/store_32bit_fp.adoc +++ b/src/insns/store_32bit_fp.adoc @@ -31,6 +31,8 @@ include::wavedrom/fpstore.adoc[] {cheri_cap_mode_name} Description:: Standard floating point store instructions, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Standard floating point store instructions, authorised by the capability in <>. diff --git a/src/insns/store_cond_32bit.adoc b/src/insns/store_cond_32bit.adoc index d8743c21..92d85dce 100644 --- a/src/insns/store_cond_32bit.adoc +++ b/src/insns/store_cond_32bit.adoc @@ -37,6 +37,8 @@ include::wavedrom/store_cond.adoc[] {cheri_cap_mode_name} Description:: Store conditional instructions, authorised by the capability in `cs1`. ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Store conditional instructions, authorised by the capability in <>. diff --git a/src/insns/store_cond_cap_32bit.adoc b/src/insns/store_cond_cap_32bit.adoc index 54e9c8fc..8beddb27 100644 --- a/src/insns/store_cond_cap_32bit.adoc +++ b/src/insns/store_cond_cap_32bit.adoc @@ -18,6 +18,8 @@ include::wavedrom/store_cond_cap.adoc[] {cheri_cap_mode_name} Description:: Store conditional instructions, authorised by the capability in `cs1`. All misaligned store conditionals cause a store/AMO address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]). ++ +include::load_store_c0.adoc[] {cheri_int_mode_name} Description:: Store conditional instructions, authorised by the capability in <>. From ad412ca1646b5da6e4d24a03c4823a5cab6155e9 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Fri, 11 Oct 2024 13:23:27 +0100 Subject: [PATCH 2/4] Update src/insns/load_store_c0.adoc Co-authored-by: Alexander Richardson Signed-off-by: Tariq Kurd --- src/insns/load_store_c0.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/insns/load_store_c0.adoc b/src/insns/load_store_c0.adoc index 5bed46a8..9f16e89a 100644 --- a/src/insns/load_store_c0.adoc +++ b/src/insns/load_store_c0.adoc @@ -1,2 +1,2 @@ Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <>. -As such, these forms should be considered available for use by future extensions. +As such, the encodings with a `cs1` of `c0` are RESERVED for use by future extensions. From c15361146c4490fd4e078d69744b67eccd35cb1f Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Fri, 11 Oct 2024 14:37:56 +0200 Subject: [PATCH 3/4] udpate encodings diagrams to forbid cs1==0 --- src/insns/load_store_c0.adoc | 2 +- src/insns/wavedrom/amo.adoc | 2 +- src/insns/wavedrom/amoswap_cap.adoc | 2 +- src/insns/wavedrom/fpload.adoc | 2 +- src/insns/wavedrom/fpstore.adoc | 2 +- src/insns/wavedrom/hypv-virt-load-cap.adoc | 2 +- src/insns/wavedrom/hypv-virt-load.adoc | 2 +- src/insns/wavedrom/hypv-virt-loadx.adoc | 2 +- src/insns/wavedrom/hypv-virt-store-cap.adoc | 2 +- src/insns/wavedrom/hypv-virt-store.adoc | 2 +- src/insns/wavedrom/load.adoc | 2 +- src/insns/wavedrom/load_res.adoc | 2 +- src/insns/wavedrom/load_res_cap.adoc | 2 +- src/insns/wavedrom/loadcap.adoc | 2 +- src/insns/wavedrom/store.adoc | 2 +- src/insns/wavedrom/store_cond.adoc | 2 +- src/insns/wavedrom/store_cond_cap.adoc | 2 +- src/insns/wavedrom/storecap.adoc | 2 +- 18 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/insns/load_store_c0.adoc b/src/insns/load_store_c0.adoc index 9f16e89a..80508405 100644 --- a/src/insns/load_store_c0.adoc +++ b/src/insns/load_store_c0.adoc @@ -1,2 +1,2 @@ -Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <>. +NOTE: Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <> capability. As such, the encodings with a `cs1` of `c0` are RESERVED for use by future extensions. diff --git a/src/insns/wavedrom/amo.adoc b/src/insns/wavedrom/amo.adoc index 37deb81c..85af9429 100644 --- a/src/insns/wavedrom/amo.adoc +++ b/src/insns/wavedrom/amo.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', '.W=010', 'rv64: .D=011'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/amoswap_cap.adoc b/src/insns/wavedrom/amoswap_cap.adoc index 6f36077e..b0dc0fdc 100644 --- a/src/insns/wavedrom/amoswap_cap.adoc +++ b/src/insns/wavedrom/amoswap_cap.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'cd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', 'width', '.C=100'], type: 8}, - {bits: 5, name: 'cs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'cs1!=0', attr: ['5', 'base'], type: 4}, {bits: 5, name: 'cs2', attr: ['5', 'src'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/fpload.adoc b/src/insns/wavedrom/fpload.adoc index 28487510..1b0dcff4 100644 --- a/src/insns/wavedrom/fpload.adoc +++ b/src/insns/wavedrom/fpload.adoc @@ -5,7 +5,7 @@ {bits: 7, name: 'opcode', attr: ['7','LOAD-FP=0000111'], type: 8}, {bits: 5, name: 'frd', attr: ['5','dest'], type: 2}, {bits: 3, name: 'width', attr: ['3','FLD=011','FLW=010', 'FLH=001'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5','base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5','base'], type: 4}, {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, ]} .... diff --git a/src/insns/wavedrom/fpstore.adoc b/src/insns/wavedrom/fpstore.adoc index 8de3d257..66895f4c 100644 --- a/src/insns/wavedrom/fpstore.adoc +++ b/src/insns/wavedrom/fpstore.adoc @@ -5,7 +5,7 @@ {bits: 7, name: 'opcode', attr: ['7','STORE-FP=0100111'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]'], type: 3}, {bits: 3, name: 'width', attr: ['3','FSD=011','FSW=010', 'FSH=001'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5','base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5','base'], type: 4}, {bits: 5, name: 'fs2', attr: ['5','src'], type: 4}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} diff --git a/src/insns/wavedrom/hypv-virt-load-cap.adoc b/src/insns/wavedrom/hypv-virt-load-cap.adoc index bdb1b71b..92954323 100644 --- a/src/insns/wavedrom/hypv-virt-load-cap.adoc +++ b/src/insns/wavedrom/hypv-virt-load-cap.adoc @@ -4,7 +4,7 @@ {bits: 7, name: 0x73, attr: ['7'], type: 8}, {bits: 5, name: 'cd', attr: ['5'], type: 2}, {bits: 3, name: 0x4, attr: ['3'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'src1'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4}, {bits: 5, name: 'type', attr: ['5', 'HLV.C=00000'], type: 3}, {bits: 7, name: 'funct7', attr: ['7', 'HLV.C=0111000'], type: 3}, ]} diff --git a/src/insns/wavedrom/hypv-virt-load.adoc b/src/insns/wavedrom/hypv-virt-load.adoc index adbc40a2..f3f45021 100644 --- a/src/insns/wavedrom/hypv-virt-load.adoc +++ b/src/insns/wavedrom/hypv-virt-load.adoc @@ -4,7 +4,7 @@ {bits: 7, name: 0x73, attr: ['7'], type: 8}, {bits: 5, name: 'rd', attr: ['5'], type: 2}, {bits: 3, name: 0x4, attr: ['3'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'src1'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4}, {bits: 5, name: 'type', attr: ['5', 'HLV.B=00000', 'HLV.BU=00001', 'HLV.H=00000', 'HLV.HU=00001', 'HLV.W=00000', 'HLV.WU=00001', 'HLV.D=00000'], type: 3}, {bits: 7, name: 'funct7', attr: ['7', 'HLV.B=0110000', 'HLV.BU=0110000', 'HLV.H=0110010', 'HLV.HU=0110010', 'HLV.W=0110100', 'HLV.WU=0110100', 'HLV.D=0110110'], type: 3}, ]} diff --git a/src/insns/wavedrom/hypv-virt-loadx.adoc b/src/insns/wavedrom/hypv-virt-loadx.adoc index b8da048c..0a86f006 100644 --- a/src/insns/wavedrom/hypv-virt-loadx.adoc +++ b/src/insns/wavedrom/hypv-virt-loadx.adoc @@ -4,7 +4,7 @@ {bits: 7, name: 0x73, attr: ['7'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, {bits: 3, name: 0x4, attr: ['3'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'src1'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4}, {bits: 5, name: 0x3, attr: ['5'], type: 3}, {bits: 7, name: 'funct7', attr: ['7', 'HLVX.HU=0110010', 'HLVX.WU=0110100'], type: 3}, ]} diff --git a/src/insns/wavedrom/hypv-virt-store-cap.adoc b/src/insns/wavedrom/hypv-virt-store-cap.adoc index 66a24029..a034c36f 100644 --- a/src/insns/wavedrom/hypv-virt-store-cap.adoc +++ b/src/insns/wavedrom/hypv-virt-store-cap.adoc @@ -4,7 +4,7 @@ {bits: 7, name: 0x73, attr: ['7'], type: 8}, {bits: 5, name: 0x0, attr: ['5'], type: 2}, {bits: 3, name: 0x4, attr: ['3'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'src1'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4}, {bits: 5, name: 'cs2', attr: ['5', 'src2'], type: 3}, {bits: 7, name: 'funct7', attr: ['7', 'HSV.C=0111001'], type: 3}, ]} diff --git a/src/insns/wavedrom/hypv-virt-store.adoc b/src/insns/wavedrom/hypv-virt-store.adoc index 55fa37ff..7463cb44 100644 --- a/src/insns/wavedrom/hypv-virt-store.adoc +++ b/src/insns/wavedrom/hypv-virt-store.adoc @@ -4,7 +4,7 @@ {bits: 7, name: 0x73, attr: ['7'], type: 8}, {bits: 5, name: 0x0, attr: ['5'], type: 2}, {bits: 3, name: 0x4, attr: ['3'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'src1'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'src1'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'src2'], type: 3}, {bits: 7, name: 'funct7', attr: ['7', 'HSV.B=0110001', 'HSV.H=0110011', 'HSV.W=0110101', 'HSV.D=0110111'], type: 3}, ]} diff --git a/src/insns/wavedrom/load.adoc b/src/insns/wavedrom/load.adoc index bda442cc..d1af4025 100644 --- a/src/insns/wavedrom/load.adoc +++ b/src/insns/wavedrom/load.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'LOAD=0000011'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', 'width', 'LB=000', 'LH=001', 'LW=010', 'LBU=100', 'LHU=101', 'rv64: LWU=110', 'rv64: LD=011'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, ]} .... diff --git a/src/insns/wavedrom/load_res.adoc b/src/insns/wavedrom/load_res.adoc index f57ba054..c2c1a234 100644 --- a/src/insns/wavedrom/load_res.adoc +++ b/src/insns/wavedrom/load_res.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', '.B=000', '.H=001', '.W=010', 'rv64: .D=011'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'LR.*=00000'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/load_res_cap.adoc b/src/insns/wavedrom/load_res_cap.adoc index 867a98b8..27ec8d2c 100644 --- a/src/insns/wavedrom/load_res_cap.adoc +++ b/src/insns/wavedrom/load_res_cap.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'cd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', '.C=100'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'funct5', attr: ['5', 'LR.*=00000'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/loadcap.adoc b/src/insns/wavedrom/loadcap.adoc index 38876ec5..3c145935 100644 --- a/src/insns/wavedrom/loadcap.adoc +++ b/src/insns/wavedrom/loadcap.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'MISCMEM=0001111','LOAD=0000011',], type: 8}, {bits: 5, name: 'cd', attr: ['5', 'dest'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', 'LC=100'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, ]} .... diff --git a/src/insns/wavedrom/store.adoc b/src/insns/wavedrom/store.adoc index 70cc4313..65d998cb 100644 --- a/src/insns/wavedrom/store.adoc +++ b/src/insns/wavedrom/store.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'STORE=0100011'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', 'SB=000','SH=001','SW=010','rv64: SD=011'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0', attr: ['5', 'base'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, ]} diff --git a/src/insns/wavedrom/store_cond.adoc b/src/insns/wavedrom/store_cond.adoc index c339832a..5f30e4fe 100644 --- a/src/insns/wavedrom/store_cond.adoc +++ b/src/insns/wavedrom/store_cond.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', 'width', '.B=000','.H=001','.W=010', 'rv64: .D=011'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/store_cond_cap.adoc b/src/insns/wavedrom/store_cond_cap.adoc index 222a71b3..907285a7 100644 --- a/src/insns/wavedrom/store_cond_cap.adoc +++ b/src/insns/wavedrom/store_cond_cap.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'AMO=0101111'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'rdest[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', 'width', '.C=100'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'cs2', attr: ['5', 'src'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'rl'], type: 4}, {bits: 1, name: 'aq', attr: ['1', 'aq'], type: 4}, diff --git a/src/insns/wavedrom/storecap.adoc b/src/insns/wavedrom/storecap.adoc index 6611c379..7bd8a716 100644 --- a/src/insns/wavedrom/storecap.adoc +++ b/src/insns/wavedrom/storecap.adoc @@ -6,7 +6,7 @@ {bits: 7, name: 'opcode', attr: ['7', 'STORE=0100011'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, {bits: 3, name: 'funct3', attr: ['3', 'SC=100'], type: 8}, - {bits: 5, name: 'rs1/cs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4}, {bits: 5, name: 'cs2', attr: ['5', 'src'], type: 4}, {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, ]} From 779b887367cd14fada6aab707d5857b91c71d16b Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Tue, 15 Oct 2024 10:28:41 +0100 Subject: [PATCH 4/4] Update src/insns/load_store_c0.adoc Co-authored-by: Nathaniel Wesley Filardo Signed-off-by: Tariq Kurd --- src/insns/load_store_c0.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/insns/load_store_c0.adoc b/src/insns/load_store_c0.adoc index 80508405..d99f58f1 100644 --- a/src/insns/load_store_c0.adoc +++ b/src/insns/load_store_c0.adoc @@ -1,2 +1,2 @@ -NOTE: Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <> capability. +NOTE: Any instance of this instruction with a `cs1` of `c0` would certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <> capability. As such, the encodings with a `cs1` of `c0` are RESERVED for use by future extensions.