Mark c0-authorized loads and stores as extensible

src/insns/amo_32bit.adoc

@@ -30,6 +30,8 @@ include::wavedrom/amo.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard atomic instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard atomic instructions, authorised by the capability in <<ddc>>.

src/insns/amoswap_32bit_cap.adoc

@@ -17,6 +17,8 @@ include::wavedrom/amoswap_cap.adoc[]
 
 {cheri_cap_mode_name} Description::
 Atomic swap of capability type, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Atomic swap of capability type, authorised by the capability in <<ddc>>.

src/insns/hypv-virt-load-cap.adoc

@@ -21,6 +21,8 @@ translation and protection, and endianness, that apply to memory accesses in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
 authorising capability for the operation is `cs1`. A copy of the loaded value
 is written to `cd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address

src/insns/hypv-virt-load.adoc

@@ -69,6 +69,8 @@ protection, and endianness, that apply to memory accesses in either VS-mode or
 VU-mode. The effective address is the address of `cs1`. The authorising
 capability for the operation is `cs1`. A copy of the loaded value is written to
 `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and

src/insns/hypv-virt-loadx.adoc

@@ -31,6 +31,8 @@ translation and protection, and endianness, that apply to memory access in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
 authorising capability for the operation is `cs1`. A copy of the loaded value
 is written to `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a load with the *execute* permission taking the place of *read*

src/insns/hypv-virt-store-cap.adoc

@@ -22,6 +22,8 @@ accesses in either VS-mode or VU-mode. The effective address is the address of
 `cs1`. The authorising capability for the operation is `cs1`. The capability
 written to memory has the tag set to 0 if the tag of `cs2` is 0 or `cs1` does
 not grant <<c_perm>>.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the

src/insns/hypv-virt-store.adoc

@@ -55,6 +55,8 @@ VU-mode. The effective address is the address of `cs1`. The authorising
 capability for the operation is `cs1`. A copy of `rs2` is written to memory at
 the location indicated by the effective address and the tag bit of each block
 of memory naturally aligned to CLEN/8 is cleared.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Performs a store as though V=1; i.e., with address translation and protection,

src/insns/load_32bit.adoc

@@ -68,6 +68,8 @@ Load integer data of the indicated size (byte, halfword, word, double-word)
 from memory. The effective address of the load is obtained by adding the
 sign-extended 12-bit offset to the address of `cs1`. The authorising capability
 for the operation is `cs1`. A copy of the loaded value is written to `rd`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load integer data of the indicated size (byte, halfword, word, double-word)

src/insns/load_32bit_cap.adoc

@@ -21,6 +21,8 @@ include::wavedrom/loadcap.adoc[]
 
 {cheri_cap_mode_name} Description::
 Load a CLEN+1 bit value from memory and writes it to `cd`. The capability in `cs1` authorizes the operation. The effective address of the memory access is obtained by adding the address of `cs1` to the sign-extended 12-bit offset.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Loads a CLEN+1 bit value from memory and writes it to `cd`. The capability

src/insns/load_32bit_fp.adoc

@@ -31,6 +31,8 @@ include::wavedrom/fpload.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard floating point load instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard floating point load instructions, authorised by the capability in <<ddc>>.

src/insns/load_res_32bit.adoc

@@ -37,6 +37,8 @@ include::wavedrom/load_res.adoc[]
 
 {cheri_cap_mode_name} Description::
 Load reserved instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load reserved instructions, authorised by the capability in <<ddc>>.

src/insns/load_res_cap_32bit.adoc

@@ -18,6 +18,8 @@ include::wavedrom/load_res_cap.adoc[]
 {cheri_cap_mode_name} Description::
 Load reserved instructions, authorised by the capability in `cs1`.
  All misaligned load reservations cause a load address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load reserved instructions, authorised by the capability in <<ddc>>.

src/insns/load_store_c0.adoc

@@ -0,0 +1,2 @@
+Any instance of this instruction with a `cs1` of `c0` will certainly trap (with a CHERI tag violation), as `c0` is defined to always hold a <<null-cap>>.
+As such, these forms should be considered available for use by future extensions.

src/insns/store_32bit.adoc

@@ -55,6 +55,8 @@ sign-extended 12-bit offset to the address of `cs1`. The authorising capability
 for the operation is `cs1`. A copy of `rs2` is written to memory at the
 location indicated by the effective address and the tag bit of each block of
 memory naturally aligned to CLEN/8 is cleared.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store integer data of the indicated size (byte, halfword, word, double-word) to

src/insns/store_32bit_cap.adoc

@@ -23,6 +23,8 @@ authorizes the operation. The effective address of the memory access is
 obtained by adding the address of `cs1` to the sign-extended 12-bit offset. The
 capability written to memory has the tag set to 0 if the tag of `cs2` is 0 or
 `cs1` does not grant <<c_perm>>.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store the CLEN+1 bit value in `cs2` to memory. The capability

src/insns/store_32bit_fp.adoc

@@ -31,6 +31,8 @@ include::wavedrom/fpstore.adoc[]
 
 {cheri_cap_mode_name} Description::
 Standard floating point store instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Standard floating point store instructions, authorised by the capability in <<ddc>>.

src/insns/store_cond_32bit.adoc

@@ -37,6 +37,8 @@ include::wavedrom/store_cond.adoc[]
 
 {cheri_cap_mode_name} Description::
 Store conditional instructions, authorised by the capability in `cs1`.
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store conditional instructions, authorised by the capability in <<ddc>>.

src/insns/store_cond_cap_32bit.adoc

@@ -18,6 +18,8 @@ include::wavedrom/store_cond_cap.adoc[]
 {cheri_cap_mode_name} Description::
 Store conditional instructions, authorised by the capability in `cs1`.
  All misaligned store conditionals cause a store/AMO address misaligned exception to allow software emulation (Zam extension, see cite:[riscv-unpriv-spec]).
++
+include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store conditional instructions, authorised by the capability in <<ddc>>.