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There is a watchpoint enable bit in dbgwcr[0] to control watchpoint work in arm, but RV doesn't exist a similar bit to start trigger fire.
How does debugger enable a trigger? 1.use type in tdata1?but tinfo is read only,if we just implement type=6 for this trigger,type in data1 can't be 0; 2. Use m/s/u state enable,and load/store enable etc. in tdata1?
The text was updated successfully, but these errors were encountered:
A trigger will only match if the appropriate mode bit is set and if the appropriate load/store/execute bit is set. There's no need for a top-level enable bit because there are multiple other ways to disable the trigger (and the value of m, s, u, vs, vu, load, store, and execute are all 0 on reset so triggers are disabled by default).
A trigger will only match if the appropriate mode bit is set and if the appropriate load/store/execute bit is set. There's no need for a top-level enable bit because there are multiple other ways to disable the trigger (and the value of m, s, u, vs, vu, load, store, and execute are all 0 on reset so triggers are disabled by default).
There is a watchpoint enable bit in dbgwcr[0] to control watchpoint work in arm, but RV doesn't exist a similar bit to start trigger fire.
How does debugger enable a trigger? 1.use type in tdata1?but tinfo is read only,if we just implement type=6 for this trigger,type in data1 can't be 0; 2. Use m/s/u state enable,and load/store enable etc. in tdata1?
The text was updated successfully, but these errors were encountered: