create a new PR for https://github.com/riscv/riscv-fast-interrupt/pull/395

[jb-brelot-nxp]

#395

it is confusing when doing csrr (rs1 == x0) whether clic.level should be compared against mcause.mpil or whether it should be compared to 0 (rs1[23:16]). I think the intent is that csr reads are compared to mcause.mpil.

[hirooih]

@jb-brelot-nxp

Let me confirm the intent of this issue ticket.

The title of #395 is "mnxti pseudo code clarification when rs1 == x0". And as you quoted, it commented as follows;

it is confusing when doing csrr (rs1 == x0) whether clic.level should be compared against mcause.mpil or whether it should be compared to 0 (rs1[23:16]). I think the intent is that csr reads are compared to mcause.mpil.

On the other hand, the content of the PR is to delete the "mnxti pseudo code when rs1 == x0", as follows

- // Pseudo-code for csrrs rd, mnxti, rs1 in M mode.
+ // Pseudo-code for csrrs rd, mnxti, rs1, rs1 != x0 in M mode.

---

Is the intent of this issue ticket to define csrr rd, mnxti as follows?

Pseudo-code for csrr rd, mnxti (csrrs rd, mnxti, x0) in M mode:

 // clic.priv, clic.level, clic.id represent the highest-ranked interrupt currently present in the CLIC
   if (clic.priv==M && clic.level > mcause.mpil && clic.level > mintthresh.th) {
     // There is an available interrupt.
     rd = VTBASE + XLEN/8 * clic.id; // Return pointer to trap handler entry.
   } else {
     // No interrupt or in non-CLIC mode.
     rd = 0;
   }

This definition is consistent with the text of this specification and makes sense to me.