Per section 3.1.1 of the Privileged Spec (Machine ISA Register misa):…

… F/D both should be disabled if F=0
riscv · Sep 26, 2023 · dbea780 · dbea780
1 parent 24e3e68
commit dbea780
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -164,10 +164,10 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
   else {
     /* Suppress enabling C if C was disabled at boot (i.e. not supported) */
     let m = if not(sys_enable_rvc()) then m else update_C(m, v.C());
-    /* Handle updates for F/D. */
-    if   not(sys_enable_fdext()) | (v.D() == 0b1 & v.F() == 0b0)
+    /* Suppress updates to misa.{f,d} if disabled at boot */
+    if   not(sys_enable_fdext())
     then m
-    else update_D(update_F(m, v.F()), v.D())
+    else update_D(update_F(m, v.F()), v.D() & v.F())
   }
 }