Clarify EMUL constraint for indexed segment ops (#868)

Signed-off-by: Nick Knight <[email protected]>
riscvarchive · Mar 14, 2023 · 5799887 · 5799887
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commit 5799887
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diff --git a/v-spec.adoc b/v-spec.adoc
@@ -1947,6 +1947,7 @@ with respect to each other.
 The data vector register group has EEW=SEW, EMUL=LMUL, while the index
 vector register group has EEW encoded in the instruction with
 EMUL=(EEW/SEW)*LMUL.
+The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group.
 
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     # Format