Skip to content
This repository has been archived by the owner on Mar 20, 2024. It is now read-only.

Update toolchain link #927

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 1 addition & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,7 @@ International License. See the LICENSE file for details.
- The [Spike simulator](https://github.com/riscv/riscv-isa-sim) supports v1.0.
- The [RISC-V Proxy Kernel](https://github.com/riscv/riscv-pk)
(to be used with e.g. Spike) supports v1.0 binaries.
- The [Binutils port for v0.8](https://github.com/riscv/riscv-binutils-gdb/tree/rvv-0.8.x)
- The [GNU toolchain port for v0.8](https://github.com/riscv/riscv-gnu-toolchain/tree/rvv-0.8.x)
- The stable release GCC 13 and LLVM 17 toolchains ([pre-built](https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable)) support v1.0.
- [riscvOVPsim](https://github.com/riscv/riscv-ovpsim) is a free
RISC-V reference simulator that has support for v0.9, v0.8 and
v0.7.1 (simulator is under a proprietary license, models are
Expand Down