diff --git a/configure b/configure
index eb49bb6680c1..c06fee23c170 100755
--- a/configure
+++ b/configure
@@ -7879,7 +7879,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml riscv-64bit-vector-512b.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
index da1bf19e2f4b..3d2031da7dcf 100644
--- a/gdb-xml/riscv-32bit-csr.xml
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -110,6 +110,8 @@
+
+
@@ -232,12 +234,11 @@
-
-
-
-
-
+
+
+
+
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
index 6aa4bed9f50f..45279edbdab8 100644
--- a/gdb-xml/riscv-64bit-csr.xml
+++ b/gdb-xml/riscv-64bit-csr.xml
@@ -110,6 +110,8 @@
+
+
@@ -232,12 +234,11 @@
-
-
-
-
-
+
+
+
+
@@ -247,4 +248,10 @@
+
+
+
+
+
+
diff --git a/gdb-xml/riscv-64bit-vector-128b.xml b/gdb-xml/riscv-64bit-vector-128b.xml
new file mode 100644
index 000000000000..f6150968b384
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-128b.xml
@@ -0,0 +1,59 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
diff --git a/gdb-xml/riscv-64bit-vector-256b.xml b/gdb-xml/riscv-64bit-vector-256b.xml
new file mode 100644
index 000000000000..6183846a35f9
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-256b.xml
@@ -0,0 +1,59 @@
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/gdb-xml/riscv-64bit-vector-512b.xml b/gdb-xml/riscv-64bit-vector-512b.xml
new file mode 100644
index 000000000000..78bb147cdf9e
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-512b.xml
@@ -0,0 +1,59 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 2f32750f2fb6..d871cc3daf28 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -268,6 +268,12 @@ static int csr_register_map[] = {
CSR_MUCOUNTEREN,
CSR_MSCOUNTEREN,
CSR_MHCOUNTEREN,
+ CSR_VSTART,
+ CSR_VXSAT,
+ CSR_VXRM,
+ CSR_VL,
+ CSR_VTYPE,
+ CSR_VLENB,
};
int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
@@ -351,6 +357,32 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
+static int riscv_gdb_get_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ int i;
+ int cnt = 0;
+ for (i = 0; i < env->vlenb; i += 8) {
+ cnt += gdb_get_reg64(mem_buf + i,
+ env->vreg[n * RV_VLEN_MAX / 64 + i / 8]);
+ }
+ return cnt;
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ int i;
+ for (i = 0; i < env->vlenb; i += 8) {
+ env->vreg[n * RV_VLEN_MAX / 64 + i / 8] = ldq_p(mem_buf + i);
+ }
+ return env->vlenb;
+ }
+ return 0;
+}
+
static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < ARRAY_SIZE(csr_register_map)) {
@@ -416,15 +448,36 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
+ if (env->misa & RVV) {
+ /* FIXME: It only supports vlen = 128, 256, 512 currently. */
+ const char *vector_xml_name = NULL;
+ switch (cpu->cfg.vlen) {
+ case 128:
+ vector_xml_name = "riscv-64bit-vector-128b.xml";
+ break;
+ case 256:
+ vector_xml_name = "riscv-64bit-vector-256b.xml";
+ break;
+ case 512:
+ vector_xml_name = "riscv-64bit-vector-512b.xml";
+ break;
+ default:
+ vector_xml_name = NULL;
+ break;
+ }
+ if (vector_xml_name)
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
+ 32, vector_xml_name, 0);
+ }
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- 240, "riscv-32bit-csr.xml", 0);
+ 247, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- 240, "riscv-64bit-csr.xml", 0);
+ 247, "riscv-64bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);