From 6770538c803fa0b0e9c59c0177130c2644bb38fb Mon Sep 17 00:00:00 2001 From: Yuichi Sugiyama Date: Wed, 7 Apr 2021 17:13:26 +0900 Subject: [PATCH] fix: fix the value written to mepc so that the low bit of mepc is always zero #39 --- Processor/Src/Privileged/CSR_Unit.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Processor/Src/Privileged/CSR_Unit.sv b/Processor/Src/Privileged/CSR_Unit.sv index bddff5bf..3fab8d5b 100644 --- a/Processor/Src/Privileged/CSR_Unit.sv +++ b/Processor/Src/Privileged/CSR_Unit.sv @@ -140,7 +140,9 @@ module CSR_Unit( CSR_NUM_MCAUSE: csrNext.mcause = wv; CSR_NUM_MTVEC: csrNext.mtvec = wv; CSR_NUM_MTVAL: csrNext.mtval = wv; - CSR_NUM_MEPC: csrNext.mepc = wv; + // The low bit of mepc is always zero, + // as described in Chapter 3.1.19 of RISC-V Privileged Architectures. + CSR_NUM_MEPC: csrNext.mepc = {wv[31:1], 1'b0}; CSR_NUM_MSCRATCH: csrNext.mscratch = wv; CSR_NUM_MCYCLE: csrNext.mcycle = wv;