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I have found a bug that causes memory deadlock on RSD 7b65f6b when executing the FENCE.I and its following instructions. Moreover, the expected behaviors of the instruction should only synchronize the instruction cache with memory. However, we suspect that the FENCE.I in RSD also affects the behaviors of data cache because we observe more than 1000 D cache misses.
I have attached the C code, hex code, and the printout from RSD when using modelsim for simulation.
Hi,
I have found a bug that causes memory deadlock on RSD
7b65f6b
when executing theFENCE.I
and its following instructions. Moreover, the expected behaviors of the instruction should only synchronize the instruction cache with memory. However, we suspect that theFENCE.I
in RSD also affects the behaviors of data cache because we observe more than 1000 D cache misses.I have attached the C code, hex code, and the printout from RSD when using modelsim for simulation.
fence_i.zip
Thank you.
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