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In general, the definitions for a lot of the registers defined in SCB, SAU, etc., are rather deficient, but my current complaint is the Fault Status registers.
The ones defined in SCB are just defined as RW<u32>, so if you want to check individual bits, you have to define your own bitfield (or do the bit twiddling manually). Disappointing, but usable.
In SAU, the situation seems a little better: there are bitfield macros for Sfsr and Sfar! That sounds great, until you try to use them:
so you end up having to do the same thing (define your own bitfield or do the bit twiddling manually), only now you have to pull the value out of the existing bitfield with sfsr.0.
The sau crate doesn't do anything with this register, yet this bitfield definition makes it useless outside of the crate.
Fix
The register definitions could use a lot of love 🙁, but the obvious fix here is to make the fields in the bitfield pub, e.g.:
In general, the definitions for a lot of the registers defined in
SCB
,SAU
, etc., are rather deficient, but my current complaint is the Fault Status registers.The ones defined in
SCB
are just defined asRW<u32>
, so if you want to check individual bits, you have to define your ownbitfield
(or do the bit twiddling manually). Disappointing, but usable.In
SAU
, the situation seems a little better: there arebitfield
macros forSfsr
andSfar
! That sounds great, until you try to use them:which gets you
so you end up having to do the same thing (define your own
bitfield
or do the bit twiddling manually), only now you have to pull the value out of the existingbitfield
withsfsr.0
.The
sau
crate doesn't do anything with this register, yet thisbitfield
definition makes it useless outside of the crate.Fix
The register definitions could use a lot of love 🙁, but the obvious fix here is to make the fields in the bitfield
pub
, e.g.:The text was updated successfully, but these errors were encountered: