diff --git a/ci/script.sh b/ci/script.sh index fcb1199e..43651a68 100755 --- a/ci/script.sh +++ b/ci/script.sh @@ -43,6 +43,7 @@ main() { echo 'cortex-m = "0.7.7"' >> $td/Cargo.toml echo 'cortex-m-rt = "0.7.3"' >> $td/Cargo.toml echo 'vcell = "0.1.3"' >> $td/Cargo.toml + echo 'const-default = "1.0"' >> $td/Cargo.toml if [[ "$options" == *"--atomics"* ]]; then echo 'portable-atomic = { version = "1.4", default-features = false }' >> $td/Cargo.toml fi diff --git a/ci/svd2rust-regress/src/svd_test.rs b/ci/svd2rust-regress/src/svd_test.rs index 1ea01f2e..e321035c 100644 --- a/ci/svd2rust-regress/src/svd_test.rs +++ b/ci/svd2rust-regress/src/svd_test.rs @@ -11,7 +11,11 @@ use std::{ path::Path, }; -const CRATES_ALL: &[&str] = &["critical-section = \"1.0\"", "vcell = \"0.1.2\""]; +const CRATES_ALL: &[&str] = &[ + "critical-section = \"1.0\"", + "vcell = \"0.1.2\"", + "const-default = \"1.0\"", +]; const CRATES_MSP430: &[&str] = &["msp430 = \"0.4.0\"", "msp430-rt = \"0.4.0\""]; const CRATES_ATOMICS: &[&str] = &["portable-atomic = { version = \"0.3.16\", default-features = false }"]; diff --git a/src/generate/generic.rs b/src/generate/generic.rs index d1b0ca0c..58c6d5ce1 100644 --- a/src/generate/generic.rs +++ b/src/generate/generic.rs @@ -1,9 +1,10 @@ use core::marker; +use const_default::ConstDefault; /// Raw register type (`u8`, `u16`, `u32`, ...) pub trait RawReg: Copy - + Default + + ConstDefault + From + core::ops::BitOr + core::ops::BitAnd @@ -74,10 +75,10 @@ pub trait Writable: RegisterSpec { type Safety; /// Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0` - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::DEFAULT; /// Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1` - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::DEFAULT; } /// Reset value of the register. @@ -86,7 +87,7 @@ pub trait Writable: RegisterSpec { /// register by using the `reset` method. pub trait Resettable: RegisterSpec { /// Reset value of the register. - const RESET_VALUE: Self::Ux; + const RESET_VALUE: Self::Ux = Self::Ux::DEFAULT; /// Reset value of the register. #[inline(always)] @@ -201,7 +202,7 @@ impl Reg { { self.register.set( f(&mut W { - bits: REG::Ux::default(), + bits: REG::Ux::DEFAULT, _reg: marker::PhantomData, }) .bits, diff --git a/src/generate/generic_atomic.rs b/src/generate/generic_atomic.rs index f0c436f6..d40d686c 100644 --- a/src/generate/generic_atomic.rs +++ b/src/generate/generic_atomic.rs @@ -39,7 +39,7 @@ mod atomic { impl Reg where - REG::Ux: AtomicOperations + Default + core::ops::Not, + REG::Ux: AtomicOperations, { /// Set high every bit in the register that was set in the write proxy. Leave other bits /// untouched. The write is done in a single atomic instruction. @@ -53,7 +53,7 @@ mod atomic { F: FnOnce(&mut W) -> &mut W, { let bits = f(&mut W { - bits: Default::default(), + bits: REG::Ux::DEFAULT, _reg: marker::PhantomData, }) .bits; @@ -72,7 +72,7 @@ mod atomic { F: FnOnce(&mut W) -> &mut W, { let bits = f(&mut W { - bits: !REG::Ux::default(), + bits: !REG::Ux::DEFAULT, _reg: marker::PhantomData, }) .bits; @@ -91,7 +91,7 @@ mod atomic { F: FnOnce(&mut W) -> &mut W, { let bits = f(&mut W { - bits: Default::default(), + bits: REG::Ux::DEFAULT, _reg: marker::PhantomData, }) .bits; diff --git a/src/generate/register.rs b/src/generate/register.rs index b40d8a60..391871e0 100644 --- a/src/generate/register.rs +++ b/src/generate/register.rs @@ -413,24 +413,31 @@ pub fn render_register_mod( let doc = format!("`write(|w| ..)` method takes [`{mod_ty}::W`](W) writer structure",); - let zero_to_modify_fields_bitmap = util::hex(zero_to_modify_fields_bitmap); - let one_to_modify_fields_bitmap = util::hex(one_to_modify_fields_bitmap); + let zero_to_modify_fields_bitmap = util::hex_nonzero(zero_to_modify_fields_bitmap) + .map(|bm| quote!(const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;)); + let one_to_modify_fields_bitmap = util::hex_nonzero(one_to_modify_fields_bitmap) + .map(|bm| quote!(const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;)); mod_items.extend(quote! { #[doc = #doc] impl crate::Writable for #regspec_ty { type Safety = crate::#safe_ty; - const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #zero_to_modify_fields_bitmap; - const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #one_to_modify_fields_bitmap; + #zero_to_modify_fields_bitmap + #one_to_modify_fields_bitmap } }); } - if let Some(rv) = properties.reset_value.map(util::hex) { - let doc = format!("`reset()` method sets {} to value {rv}", register.name); + if let Some(rv) = properties.reset_value.map(util::hex_nonzero) { + let doc = if let Some(rv) = &rv { + format!("`reset()` method sets {} to value {rv}", register.name) + } else { + format!("`reset()` method sets {} to value 0", register.name) + }; + let rv = rv.map(|rv| quote!(const RESET_VALUE: #rty = #rv;)); mod_items.extend(quote! { #[doc = #doc] impl crate::Resettable for #regspec_ty { - const RESET_VALUE: #rty = #rv; + #rv } }); } diff --git a/src/lib.rs b/src/lib.rs index 6a0b754f..908772ea 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -62,6 +62,7 @@ //! - [`cortex-m`](https://crates.io/crates/cortex-m) >=v0.7.6 //! - [`cortex-m-rt`](https://crates.io/crates/cortex-m-rt) >=v0.6.13 //! - [`vcell`](https://crates.io/crates/vcell) >=v0.1.2 +//! - [`const-default`](https://crates.io/crates/const-default) >=v1.0 //! //! Furthermore, the "device" feature of `cortex-m-rt` must be enabled when the `rt` feature //! is enabled. The `Cargo.toml` of the device crate will look like this: @@ -126,6 +127,7 @@ //! - [`msp430`](https://crates.io/crates/msp430) v0.4.x //! - [`msp430-rt`](https://crates.io/crates/msp430-rt) v0.4.x //! - [`vcell`](https://crates.io/crates/vcell) v0.1.x +//! - [`const-default`](https://crates.io/crates/const-default) v1.x.x //! //! The "device" feature of `msp430-rt` must be enabled when the `rt` feature is //! enabled. The `Cargo.toml` of the device crate will look like this: @@ -152,6 +154,7 @@ //! - [`riscv`](https://crates.io/crates/riscv) v0.9.x (if target is RISC-V) //! - [`riscv-rt`](https://crates.io/crates/riscv-rt) v0.9.x (if target is RISC-V) //! - [`vcell`](https://crates.io/crates/vcell) v0.1.x +//! - [`const-default`](https://crates.io/crates/const-default) v1.x.x //! //! The `*-rt` dependencies must be optional only enabled when the `rt` feature is enabled. The //! `Cargo.toml` of the device crate will look like this for a RISC-V target: @@ -162,6 +165,7 @@ //! riscv = "0.9.0" //! riscv-rt = { version = "0.9.0", optional = true } //! vcell = "0.1.0" +//! const-default = "1.0" //! //! [features] //! rt = ["riscv-rt"] diff --git a/src/util.rs b/src/util.rs index 4910e6a7..25102c3e 100644 --- a/src/util.rs +++ b/src/util.rs @@ -253,6 +253,11 @@ pub fn hex(n: u64) -> LitInt { ) } +/// Turns non-zero `n` into an unsuffixed separated hex token +pub fn hex_nonzero(n: u64) -> Option { + (n != 0).then(|| hex(n)) +} + /// Turns `n` into an unsuffixed token pub fn unsuffixed(n: impl Into) -> LitInt { LitInt::new(&n.into().to_string(), Span::call_site())