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The RISC-V standard states that, in vector mode, the value in mtvec must be at least 4-byte aligned. However, targets may impose more strict alignment constraints (e.g., 256-byte aligned in Ibex).
The linked PR adds a RISCV_MTVEC_ALIGN environment variable that PACs should set in their build script to the desired value. I propose using svd2rust's config file to allow PACs to use this feature.
The text was updated successfully, but these errors were encountered:
Motivated by rust-embedded/riscv#259
The RISC-V standard states that, in vector mode, the value in
mtvec
must be at least 4-byte aligned. However, targets may impose more strict alignment constraints (e.g., 256-byte aligned in Ibex).The linked PR adds a
RISCV_MTVEC_ALIGN
environment variable that PACs should set in their build script to the desired value. I propose usingsvd2rust
's config file to allow PACs to use this feature.The text was updated successfully, but these errors were encountered: