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32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

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LICENSE		LICENSE
README.md		README.md
Report.pdf		Report.pdf
adder_pipeline.v		adder_pipeline.v
adder_tb.v		adder_tb.v
fa.v		fa.v
ha.v		ha.v

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Floating-Point-Adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

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32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

pipeline-framework verilog ieee754 digital-design

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Verilog 100.0%