From b01fb227e76364d554477e82d5e04f266a1e76c7 Mon Sep 17 00:00:00 2001 From: AlwenXXD <58737673+AlwenXXD@users.noreply.github.com> Date: Sat, 22 Oct 2022 11:51:59 +0800 Subject: [PATCH] refactor decode logic, add file decoder.scala (#47) * refactor decode logic, add decoder file * Change the code style, remove out of use files. * Change object name uOP to UOp, remove deprecated code. --- src/main/scala/ALU.scala | 36 ++-- src/main/scala/BranchCondition.scala | 24 +-- src/main/scala/CPU.scala | 122 +++++-------- src/main/scala/Decoder.scala | 248 +++++++++++++++++++++++++++ src/main/scala/Imm.scala | 41 ----- src/test/scala/ALUTest.scala | 2 +- src/test/scala/ImmTest.scala | 29 ---- 7 files changed, 310 insertions(+), 192 deletions(-) create mode 100644 src/main/scala/Decoder.scala delete mode 100644 src/main/scala/Imm.scala delete mode 100644 src/test/scala/ImmTest.scala diff --git a/src/main/scala/ALU.scala b/src/main/scala/ALU.scala index 8ae4154..4d29315 100644 --- a/src/main/scala/ALU.scala +++ b/src/main/scala/ALU.scala @@ -3,58 +3,44 @@ import chisel3.util._ class ALU extends Module { - import ALUOperation._ - val io = IO(new Bundle { val A = Input(Bits(32.W)) val B = Input(Bits(32.W)) - val op = Input(Bits(4.W)) + val op = Input(UOp()) val result = Output(Bits(32.W)) }) io.result := 0xdead.U switch(io.op) { - is(ADD) { + is(UOp.ADD) { io.result := io.A.asUInt + io.B.asUInt } - is(SUB) { + is(UOp.SUB) { io.result := io.A.asUInt - io.B.asUInt } - is(SLL) { + is(UOp.SLL) { io.result := io.A << io.B(4, 0).asUInt } - is(SLT) { + is(UOp.SLT) { io.result := io.A.asSInt < io.B.asSInt } - is(SLTU) { + is(UOp.SLTU) { io.result := io.A.asUInt < io.B.asUInt } - is(XOR) { + is(UOp.XOR) { io.result := io.A ^ io.B } - is(SRL) { + is(UOp.SRL) { io.result := io.A >> io.B(4, 0).asUInt } - is(SRA) { + is(UOp.SRA) { io.result := (io.A.asSInt >> io.B(4, 0)).asUInt() } - is(OR) { + is(UOp.OR) { io.result := io.A | io.B } - is(AND) { + is(UOp.AND) { io.result := io.A & io.B } } } -object ALUOperation extends Enumeration { - val ADD = "b0000".U - val SUB = "b1000".U - val SLL = "b0001".U - val SLT = "b0010".U - val SLTU = "b0011".U - val XOR = "b0100".U - val SRL = "b0101".U - val SRA = "b1101".U - val OR = "b0110".U - val AND = "b0111".U -} diff --git a/src/main/scala/BranchCondition.scala b/src/main/scala/BranchCondition.scala index 601008d..2601db1 100644 --- a/src/main/scala/BranchCondition.scala +++ b/src/main/scala/BranchCondition.scala @@ -3,42 +3,32 @@ import chisel3.util._ class BranchCondition extends Module { - import BranchType._ - val io = IO(new Bundle { val A = Input(Bits(32.W)) val B = Input(Bits(32.W)) - val op = Input(Bits(3.W)) + val op = Input(UOp()) val take = Output(Bool()) }) io.take := false.B switch(io.op) { - is(EQ) { + is(UOp.BEQ) { io.take := io.A.asSInt() === io.B.asSInt() } - is(NE) { + is(UOp.BNE) { io.take := io.A.asSInt() =/= io.B.asSInt() } - is(LT) { + is(UOp.BLT) { io.take := io.A.asSInt() < io.B.asSInt() } - is(GE) { + is(UOp.BGE) { io.take := io.A.asSInt() >= io.B.asSInt() } - is(LTU) { + is(UOp.BLTU) { io.take := io.A.asUInt() < io.B.asUInt() } - is(GEU) { + is(UOp.BGEU) { io.take := io.A.asUInt() >= io.B.asUInt() } } } -object BranchType extends Enumeration { - val EQ = "b000".U - val NE = "b001".U - val LT = "b100".U - val GE = "b101".U - val LTU = "b110".U - val GEU = "b111".U -} diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala index 1b8a190..894569c 100644 --- a/src/main/scala/CPU.scala +++ b/src/main/scala/CPU.scala @@ -9,7 +9,6 @@ class CPUBundle extends Bundle { class CPU extends Module { - import CommandType._ val io = IO(new CPUBundle) @@ -21,6 +20,9 @@ class CPU extends Module { val instruction = Wire(UInt(32.W)) instruction := io.programROMBundle.value + val decoder = Wire(new Decoder()) + decoder.decode(instruction) + io.dataBusBundle.readMode := true.B io.dataBusBundle.maskLevel := Mask.WORD io.dataBusBundle.address := 0.U @@ -34,52 +36,44 @@ class CPU extends Module { csr.io.timerInterruptPending := io.timerInterruptPending val regFile = Module(new RegFile) - regFile.io.addressInput := instruction(11, 7) - regFile.io.addressA := instruction(19, 15) - regFile.io.addressB := instruction(24, 20) + regFile.io.addressInput := decoder.rdAddr + regFile.io.addressA := decoder.rs1Addr + regFile.io.addressB := decoder.rs2Addr regFile.io.input := 0xdead.U regFile.io.writeEnable := false.B - val immGen = Module(new Imm) - immGen.io.instruction := instruction - val branchCondition = Module(new BranchCondition) branchCondition.io.A := regFile.io.outputA branchCondition.io.B := regFile.io.outputB - branchCondition.io.op := instruction(14, 12) + branchCondition.io.op := decoder.uOp val alu = Module(new ALU) alu.io.A := 0xdead.U alu.io.B := 0xdead.U - alu.io.op := 0xdead.U + alu.io.op := UOp.NOP val stall = RegInit(false.B) when(stall) { stall := false.B regFile.io.writeEnable := true.B - io.dataBusBundle.address := (regFile.io.outputA.asSInt() + immGen.io.result).asUInt() - io.dataBusBundle.maskLevel := instruction(13, 12) + io.dataBusBundle.address := (regFile.io.outputA.asSInt() + decoder.immData.asSInt()).asUInt() + io.dataBusBundle.maskLevel := decoder.maskLevel // second part of load - switch(instruction(14, 12)) { - // LB - is("b000".U) { + switch(decoder.uOp) { + is(UOp.LB) { regFile.io.input := io.dataBusBundle.dataOut(7, 0) } - // LH - is("b001".U) { + is(UOp.LH) { regFile.io.input := io.dataBusBundle.dataOut(15, 0) } - // LW - is("b010".U) { + is(UOp.LW) { regFile.io.input := io.dataBusBundle.dataOut } - // LBU - is("b100".U) { + is(UOp.LBU) { regFile.io.input := io.dataBusBundle.dataOut(7, 0).asUInt() } - // LHU - is("b101".U) { + is(UOp.LHU) { regFile.io.input := io.dataBusBundle.dataOut(15, 0).asUInt() } } @@ -90,80 +84,69 @@ class CPU extends Module { csr.io.inputValue := pc + 4.U pc := csr.io.pcOnInterrupt }.otherwise { - switch(instruction(6, 2)) { - is(LUI) { - regFile.io.input := immGen.io.result.asUInt() + switch(decoder.instType) { + is(InstType.LUI) { + regFile.io.input := decoder.immData regFile.io.writeEnable := true.B } - is(AUIPC) { - alu.io.A := immGen.io.result.asUInt() + is(InstType.AUIPC) { + alu.io.A := decoder.immData alu.io.B := pc - alu.io.op := ALUOperation.ADD + alu.io.op := UOp.ADD regFile.io.input := alu.io.result regFile.io.writeEnable := true.B } - is(JAL) { + is(InstType.JAL) { alu.io.A := 4.U alu.io.B := pc - alu.io.op := ALUOperation.ADD + alu.io.op := UOp.ADD regFile.io.input := alu.io.result regFile.io.writeEnable := true.B - pc := (pc.asSInt() + immGen.io.result).asUInt() + pc := (pc.asSInt() + decoder.immData.asSInt()).asUInt() } - is(JALR) { + is(InstType.JALR) { alu.io.A := regFile.io.outputA - alu.io.B := immGen.io.result.asUInt() - alu.io.op := ALUOperation.ADD + alu.io.B := decoder.immData + alu.io.op := UOp.ADD regFile.io.input := pc + 4.U regFile.io.writeEnable := true.B pc := alu.io.result & "hfffffffe".U } - is(BRANCH) { + is(InstType.BRANCH) { when(branchCondition.io.take) { - pc := (pc.asSInt() + immGen.io.result).asUInt() + pc := (pc.asSInt() + decoder.immData.asSInt()).asUInt() } } - is(LOAD) { + is(InstType.LOAD) { // first part of load: send a load command to addressSpace - io.dataBusBundle.address := (regFile.io.outputA.asSInt() + immGen.io.result).asUInt() - io.dataBusBundle.maskLevel := instruction(13, 12) + io.dataBusBundle.address := (regFile.io.outputA.asSInt() + decoder.immData.asSInt()).asUInt() + io.dataBusBundle.maskLevel := decoder.maskLevel // stall once for waiting for the load result come out pc := pc stall := true.B } - is(STORE) { - io.dataBusBundle.address := (regFile.io.outputA.asSInt() + immGen.io.result).asUInt() + is(InstType.STORE) { + io.dataBusBundle.address := (regFile.io.outputA.asSInt() + decoder.immData.asSInt()).asUInt() io.dataBusBundle.readMode := false.B - io.dataBusBundle.maskLevel := instruction(13, 12) + io.dataBusBundle.maskLevel := decoder.maskLevel io.dataBusBundle.dataIn := regFile.io.outputB } - is(CALCULATE_IMM) { - regFile.io.writeEnable := true.B - alu.io.A := regFile.io.outputA - alu.io.B := immGen.io.result.asUInt() - when(instruction(14, 12) === "b001".U || instruction(14, 12) === "b101".U) { - alu.io.op := Cat(instruction(30), instruction(14, 12)) - }.otherwise { - alu.io.op := Cat(0.U(1.W), instruction(14, 12)) - } - regFile.io.input := alu.io.result - } - is(CALCULATE_REG) { + is(InstType.CALCULATE) { regFile.io.writeEnable := true.B alu.io.A := regFile.io.outputA - alu.io.B := regFile.io.outputB - alu.io.op := Cat(instruction(30), instruction(14, 12)) + alu.io.B := Mux(decoder.needImm,decoder.immData,regFile.io.outputB) + alu.io.op := decoder.uOp regFile.io.input := alu.io.result } - is(FENCE) { + is(InstType.FENCE) { // we don't have multicore, pipeline, etc. now, so we don't need this command } - is(SYSTEM) { - switch(instruction(31, 20)) { - is(SystemCommand.MRET) { + is(InstType.SYSTEM) { + switch(decoder.uOp) { + is(UOp.MRET) { csr.io.flipStatusMIE := true.B csr.io.address := CSRAddress.mepc pc := csr.io.outputValue @@ -174,22 +157,3 @@ class CPU extends Module { } } -object CommandType extends Enumeration { - val LUI = "b01101".U - val AUIPC = "b00101".U - val JAL = "b11011".U - val JALR = "b11001".U - val BRANCH = "b11000".U - val LOAD = "b00000".U - val STORE = "b01000".U - val CALCULATE_IMM = "b00100".U - val CALCULATE_REG = "b01100".U - val FENCE = "b00011".U - val SYSTEM = "b11100".U -} - -object SystemCommand extends Enumeration { - val MRET = "h302".U - val ECALL = "b000".U - val EBREAK = "b001".U -} diff --git a/src/main/scala/Decoder.scala b/src/main/scala/Decoder.scala new file mode 100644 index 0000000..772fbb0 --- /dev/null +++ b/src/main/scala/Decoder.scala @@ -0,0 +1,248 @@ +import chisel3._ +import chisel3.experimental.ChiselEnum +import chisel3.util._ + +class Decoder extends Bundle { + import DecodeTable._ + val uOp = UOp() + val instType = InstType() + val needImm = Bool() + val rs1Addr = UInt(5.W) + val rs2Addr = UInt(5.W) + val rdAddr = UInt(5.W) + val immData = UInt(32.W) + val csrIdx = UInt(12.W) + val maskLevel = UInt(2.W) + + def decode(inst: UInt): Decoder = { + val immSel = Wire(ImmSel()) + + val decoder = ListLookup(inst, decodeDefault, decodeTable) + val signals = Seq(uOp, instType, immSel) + signals zip decoder foreach { case (s, d) => s := d } + + val rd = inst(11, 7) + val rs1 = inst(19, 15) + val rs2 = inst(24, 20) + val immI = Cat(Fill(20, inst(31)), inst(31, 20)) + val immS = Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)) + val immB = Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) + val immU = Cat(inst(31, 12), 0.U(12.W)) + val immJ = Cat(Fill(11, inst(31)), inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) + val shamt = Cat(Fill(26, false.B), inst(25, 20)) + val zimm = Cat(Fill(27, false.B), inst(19, 15)) + + + needImm := immSel =/= ImmSel.NOIMM + rs1Addr := rs1 + rs2Addr := rs2 + rdAddr := rd + immData := MuxLookup(immSel.asUInt(), 0.U(32.W), Array( + ImmSel.I.asUInt() -> immI, + ImmSel.S.asUInt() -> immS, + ImmSel.B.asUInt() -> immB, + ImmSel.U.asUInt() -> immU, + ImmSel.J.asUInt() -> immJ, + ImmSel.SHAMT.asUInt() -> shamt, + ImmSel.ZIMM.asUInt() -> zimm + ).toSeq) + maskLevel := inst(13, 12) + csrIdx := inst(31, 20) + this + } +} + +object Instructions extends Enumeration { + val BEQ = BitPat("b?????????????????000?????1100011") + val BNE = BitPat("b?????????????????001?????1100011") + val BLT = BitPat("b?????????????????100?????1100011") + val BGE = BitPat("b?????????????????101?????1100011") + val BLTU = BitPat("b?????????????????110?????1100011") + val BGEU = BitPat("b?????????????????111?????1100011") + val JALR = BitPat("b?????????????????000?????1100111") + val JAL = BitPat("b?????????????????????????1101111") + val LUI = BitPat("b?????????????????????????0110111") + val AUIPC = BitPat("b?????????????????????????0010111") + val ADDI = BitPat("b?????????????????000?????0010011") + val SLLI = BitPat("b000000???????????001?????0010011") + val SLTI = BitPat("b?????????????????010?????0010011") + val SLTIU = BitPat("b?????????????????011?????0010011") + val XORI = BitPat("b?????????????????100?????0010011") + val SRLI = BitPat("b000000???????????101?????0010011") + val SRAI = BitPat("b010000???????????101?????0010011") + val ORI = BitPat("b?????????????????110?????0010011") + val ANDI = BitPat("b?????????????????111?????0010011") + val ADD = BitPat("b0000000??????????000?????0110011") + val SUB = BitPat("b0100000??????????000?????0110011") + val SLL = BitPat("b0000000??????????001?????0110011") + val SLT = BitPat("b0000000??????????010?????0110011") + val SLTU = BitPat("b0000000??????????011?????0110011") + val XOR = BitPat("b0000000??????????100?????0110011") + val SRL = BitPat("b0000000??????????101?????0110011") + val SRA = BitPat("b0100000??????????101?????0110011") + val OR = BitPat("b0000000??????????110?????0110011") + val AND = BitPat("b0000000??????????111?????0110011") + val LB = BitPat("b?????????????????000?????0000011") + val LH = BitPat("b?????????????????001?????0000011") + val LW = BitPat("b?????????????????010?????0000011") + val LBU = BitPat("b?????????????????100?????0000011") + val LHU = BitPat("b?????????????????101?????0000011") + val LWU = BitPat("b?????????????????110?????0000011") + val SB = BitPat("b?????????????????000?????0100011") + val SH = BitPat("b?????????????????001?????0100011") + val SW = BitPat("b?????????????????010?????0100011") + val FENCE = BitPat("b?????????????????000?????0001111") + val FENCE_I = BitPat("b?????????????????001?????0001111") + val ECALL = BitPat("b00000000000000000000000001110011") + val EBREAK = BitPat("b00000000000100000000000001110011") + val MRET = BitPat("b00110000001000000000000001110011") + val SRET = BitPat("b00010000001000000000000001110011") + val SFENCE_VMA = BitPat("b0001001??????????000000001110011") + val WFI = BitPat("b00010000010100000000000001110011") + val CSRRW = BitPat("b?????????????????001?????1110011") + val CSRRS = BitPat("b?????????????????010?????1110011") + val CSRRC = BitPat("b?????????????????011?????1110011") + val CSRRWI = BitPat("b?????????????????101?????1110011") + val CSRRSI = BitPat("b?????????????????110?????1110011") + val CSRRCI = BitPat("b?????????????????111?????1110011") +} + +object DecodeTable { + import Instructions._ + val decodeDefault = List(UOp.NOP, InstType.NONE, ImmSel.NOIMM) + val decodeTable = Array( + BEQ -> List(UOp.BEQ , InstType.BRANCH , ImmSel.B), + BNE -> List(UOp.BNE , InstType.BRANCH , ImmSel.B), + BLT -> List(UOp.BLT , InstType.BRANCH , ImmSel.B), + BGE -> List(UOp.BGE , InstType.BRANCH , ImmSel.B), + BLTU -> List(UOp.BLTU , InstType.BRANCH , ImmSel.B), + BGEU -> List(UOp.BGEU , InstType.BRANCH , ImmSel.B), + JALR -> List(UOp.JALR , InstType.JALR , ImmSel.I), + JAL -> List(UOp.JAL , InstType.JAL , ImmSel.J), + LUI -> List(UOp.LUI , InstType.LUI , ImmSel.U), + AUIPC -> List(UOp.AUIPC , InstType.AUIPC , ImmSel.U), + ADDI -> List(UOp.ADD , InstType.CALCULATE, ImmSel.I), + SLLI -> List(UOp.SLL , InstType.CALCULATE, ImmSel.SHAMT), + SLTI -> List(UOp.SLT , InstType.CALCULATE, ImmSel.I), + SLTIU -> List(UOp.SLTU , InstType.CALCULATE, ImmSel.I), + XORI -> List(UOp.XOR , InstType.CALCULATE, ImmSel.I), + SRLI -> List(UOp.SRL , InstType.CALCULATE, ImmSel.SHAMT), + SRAI -> List(UOp.SRA , InstType.CALCULATE, ImmSel.SHAMT), + ORI -> List(UOp.OR , InstType.CALCULATE, ImmSel.I), + ANDI -> List(UOp.AND , InstType.CALCULATE, ImmSel.I), + ADD -> List(UOp.ADD , InstType.CALCULATE, ImmSel.NOIMM), + SUB -> List(UOp.SUB , InstType.CALCULATE, ImmSel.NOIMM), + SLL -> List(UOp.SLL , InstType.CALCULATE, ImmSel.NOIMM), + SLT -> List(UOp.SLT , InstType.CALCULATE, ImmSel.NOIMM), + SLTU -> List(UOp.SLTU , InstType.CALCULATE, ImmSel.NOIMM), + XOR -> List(UOp.XOR , InstType.CALCULATE, ImmSel.NOIMM), + SRL -> List(UOp.SRL , InstType.CALCULATE, ImmSel.NOIMM), + SRA -> List(UOp.SRA , InstType.CALCULATE, ImmSel.NOIMM), + OR -> List(UOp.OR , InstType.CALCULATE, ImmSel.NOIMM), + AND -> List(UOp.AND , InstType.CALCULATE, ImmSel.NOIMM), + LB -> List(UOp.LB , InstType.LOAD , ImmSel.I), + LH -> List(UOp.LH , InstType.LOAD , ImmSel.I), + LW -> List(UOp.LW , InstType.LOAD , ImmSel.I), + LBU -> List(UOp.LBU , InstType.LOAD , ImmSel.I), + LHU -> List(UOp.LHU , InstType.LOAD , ImmSel.I), + LWU -> List(UOp.LWU , InstType.LOAD , ImmSel.I), + SB -> List(UOp.SB , InstType.STORE , ImmSel.S), + SH -> List(UOp.SH , InstType.STORE , ImmSel.S), + SW -> List(UOp.SW , InstType.STORE , ImmSel.S), + CSRRW -> List(UOp.CSRRW , InstType.CALCULATE, ImmSel.NOIMM), + CSRRS -> List(UOp.CSRRS , InstType.CALCULATE, ImmSel.NOIMM), + CSRRC -> List(UOp.CSRRC , InstType.CALCULATE, ImmSel.NOIMM), + CSRRWI -> List(UOp.CSRRW , InstType.CALCULATE, ImmSel.ZIMM), + CSRRSI -> List(UOp.CSRRS , InstType.CALCULATE, ImmSel.ZIMM), + CSRRCI -> List(UOp.CSRRC , InstType.CALCULATE, ImmSel.ZIMM), + FENCE -> List(UOp.FENCE , InstType.FENCE , ImmSel.NOIMM), + FENCE_I -> List(UOp.FENCE_I , InstType.FENCE , ImmSel.NOIMM), + ECALL -> List(UOp.ECALL , InstType.SYSTEM , ImmSel.NOIMM), + EBREAK -> List(UOp.EBREAK , InstType.SYSTEM , ImmSel.NOIMM), + MRET -> List(UOp.MRET , InstType.SYSTEM , ImmSel.NOIMM), + SRET -> List(UOp.SRET , InstType.SYSTEM , ImmSel.NOIMM), + SFENCE_VMA -> List(UOp.SFENCE_VMA, InstType.FENCE , ImmSel.NOIMM), + WFI -> List(UOp.WFI , InstType.SYSTEM , ImmSel.NOIMM) + + ) +} + + +//micro operations +object UOp extends ChiselEnum { + val + NOP, + //branch and jump + BEQ, + BNE, + BLT, + BGE, + BLTU, + BGEU, + JALR, + JAL, + //arithmetic and logic + LUI, + AUIPC, + ADD, + SUB, + SLL, + SLT, + SLTU, + XOR, + SRL, + SRA, + OR, + AND, + //load and store + LB, + LH, + LW, + LBU, + LHU, + LWU, + SB, + SH, + SW, + //privilege + ECALL, + EBREAK, + MRET, + SRET, + FENCE, + FENCE_I, + SFENCE_VMA, + WFI, + //csr + CSRRW, + CSRRS, + CSRRC = Value +} + +object InstType extends ChiselEnum { + val + NONE, + LUI, + AUIPC, + JAL, + JALR, + BRANCH, + CALCULATE, + LOAD, + STORE, + FENCE, + SYSTEM = Value +} + + +object ImmSel extends ChiselEnum { + val + I, + U, + J, + S, + B, + ZIMM, + SHAMT, + NOIMM = Value +} \ No newline at end of file diff --git a/src/main/scala/Imm.scala b/src/main/scala/Imm.scala deleted file mode 100644 index 1cda526..0000000 --- a/src/main/scala/Imm.scala +++ /dev/null @@ -1,41 +0,0 @@ -import chisel3._ -import chisel3.util._ - -class Imm extends Module { - val io = IO(new Bundle { - val instruction = Input(Bits(32.W)) - val result = Output(SInt(32.W)) - }) - val I = io.instruction(31, 20).asSInt - val S = Cat(io.instruction(31, 25), io.instruction(11, 7)).asSInt - val B = Cat(io.instruction(31), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)).asSInt - val U = Cat(io.instruction(31, 12), 0.U(12.W)).asSInt - val J = Cat(io.instruction(31), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W)).asSInt - io.result := 0xdead.S(32.W) - switch(io.instruction(6, 2)) { - is("b00100".U) { - io.result := I - } - is("b00000".U) { - io.result := I - } - is("b11001".U) { - io.result := I - } - is("b01000".U) { - io.result := S - } - is("b11000".U) { - io.result := B - } - is("b01101".U) { - io.result := U - } - is("b00101".U) { - io.result := U - } - is("b11011".U) { - io.result := J - } - } -} diff --git a/src/test/scala/ALUTest.scala b/src/test/scala/ALUTest.scala index 8dacec8..1037b88 100644 --- a/src/test/scala/ALUTest.scala +++ b/src/test/scala/ALUTest.scala @@ -4,7 +4,7 @@ import org.scalatest.{FlatSpec, Matchers} class ALUTest(alu: ALU) extends PeekPokeTester(alu) { - import ALUOperation._ + import UOp._ val cases = Array( (1, 2, ADD, 3.U), diff --git a/src/test/scala/ImmTest.scala b/src/test/scala/ImmTest.scala deleted file mode 100644 index f6ea62e..0000000 --- a/src/test/scala/ImmTest.scala +++ /dev/null @@ -1,29 +0,0 @@ -import chisel3._ -import chisel3.iotesters._ -import org.scalatest.{FlatSpec, Matchers} - -class ImmTest(imm: Imm) extends PeekPokeTester(imm) { - val cases = Array( - ("hfe010113", -32), // I - ("h00112e23", 28), // S - ("hf4e7d4e3", -184), // B - ("h000007b7", 0), // U - // J - ("h130000ef", 304)) - for ((instruction, result) <- cases) { - poke(imm.io.instruction, instruction.U) - expect(imm.io.result, result) - // just for render vcd - step(1) - } -} - -class ImmSpec extends FlatSpec with Matchers { - behavior of "ImmSpec" - - it should "generate imm successfully" in { - chisel3.iotesters.Driver.execute(Array("--generate-vcd-output", "on"), () => new Imm) { imm => - new ImmTest(imm) - } should be(true) - } -}