fix regfile output (#36)

this substraction cause a magic bug.
shuosc · Apr 28, 2021 · a913040 · a913040
1 parent fe3e78b
commit a913040
Showing 1 changed file with 4 additions and 12 deletions.
diff --git a/src/main/scala/RegFile.scala b/src/main/scala/RegFile.scala
@@ -13,18 +13,10 @@ class RegFile extends Module {
 
     val writeEnable = Input(Bool())
   })
-  val regs = Reg(Vec(31, UInt(32.W)))
-  if (io.addressA == 0.U) {
-    io.outputA := 0.U
-  } else {
-    io.outputA := regs(io.addressA - 1.U)
-  }
-  if (io.addressB == 0.U) {
-    io.outputB := 0.U
-  } else {
-    io.outputB := regs(io.addressB - 1.U)
-  }
+  val regs = Reg(Vec(32, UInt(32.W)))
+  io.outputA := regs(io.addressA)
+  io.outputB := regs(io.addressB)
   when(io.writeEnable & io.addressInput.orR()) {
-    regs(io.addressInput - 1.U) := io.input
+    regs(io.addressInput) := io.input
   }
 }