From a913040f69d7cd337c80583af904ad17d9e4b622 Mon Sep 17 00:00:00 2001 From: Dian Zhou Date: Wed, 28 Apr 2021 22:46:18 +0800 Subject: [PATCH] fix regfile output (#36) this substraction cause a magic bug. --- src/main/scala/RegFile.scala | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/main/scala/RegFile.scala b/src/main/scala/RegFile.scala index 0c34504..6f83211 100644 --- a/src/main/scala/RegFile.scala +++ b/src/main/scala/RegFile.scala @@ -13,18 +13,10 @@ class RegFile extends Module { val writeEnable = Input(Bool()) }) - val regs = Reg(Vec(31, UInt(32.W))) - if (io.addressA == 0.U) { - io.outputA := 0.U - } else { - io.outputA := regs(io.addressA - 1.U) - } - if (io.addressB == 0.U) { - io.outputB := 0.U - } else { - io.outputB := regs(io.addressB - 1.U) - } + val regs = Reg(Vec(32, UInt(32.W))) + io.outputA := regs(io.addressA) + io.outputB := regs(io.addressB) when(io.writeEnable & io.addressInput.orR()) { - regs(io.addressInput - 1.U) := io.input + regs(io.addressInput) := io.input } }