From 26d9454c50524663ccfe3bf2c22d648a2bfdf146 Mon Sep 17 00:00:00 2001
From: Lars Rademacher <rademacher.lars@gmx.de>
Date: Tue, 23 Feb 2021 16:45:44 +0100
Subject: [PATCH] Added new motor pwm dump (3-phase inverter)

Synthetic motor pwm data that are used in sigrok-test project for
timing PD's new feature of different end condition.
---
 pwm/motor_pwm/README       |  20 ++++++++++++++++++++
 pwm/motor_pwm/motor_pwm.sr | Bin 0 -> 633 bytes
 2 files changed, 20 insertions(+)
 create mode 100644 pwm/motor_pwm/README
 create mode 100644 pwm/motor_pwm/motor_pwm.sr

diff --git a/pwm/motor_pwm/README b/pwm/motor_pwm/README
new file mode 100644
index 0000000..ba7cc5f
--- /dev/null
+++ b/pwm/motor_pwm/README
@@ -0,0 +1,20 @@
+-------------------------------------------------------------------------------
+3-phase motor pwm signals (high and low side, active low)
+-------------------------------------------------------------------------------
+
+This is a synthetic motor pwm signal (three-phase inverter) containing high and 
+low side signals, which are active low (switch is active at low level).
+phase U: constantly 10% duty cycle, 
+phase V: constantly 50% duty cycle, 
+phase W: constantly 90% duty cycle
+
+It is very important to satisfy a minimum required dead-time between switching 
+off the high side and switching on the low side and vice-versa to prevent phase
+short-circuits. This dead-time can be observed here to be ~1.4us.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Salae Logic16 clone operated at 16MHz.
+
diff --git a/pwm/motor_pwm/motor_pwm.sr b/pwm/motor_pwm/motor_pwm.sr
new file mode 100644
index 0000000000000000000000000000000000000000..0ad414d140a442347a0e46883e4e5b8b06f53f60
GIT binary patch
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literal 0
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