diff --git a/components/asic/bm1368.c b/components/asic/bm1368.c index 12ec8c4a5..802a70dfb 100644 --- a/components/asic/bm1368.c +++ b/components/asic/bm1368.c @@ -265,7 +265,7 @@ uint8_t BM1368_init(uint64_t frequency, uint16_t asic_count) {0x00, 0x3C, 0x80, 0x00, 0x8b, 0x00}, {0x00, 0x3C, 0x80, 0x00, 0x80, 0x18}, {0x00, 0x14, 0x00, 0x00, 0x00, 0xFF}, - {0x00, 0x54, 0x00, 0x00, 0x00, 0x03}, + {0x00, 0x54, 0x00, 0x00, 0x00, 0x03}, //Analog Mux {0x00, 0x58, 0x02, 0x11, 0x11, 0x11} }; diff --git a/components/asic/bm1370.c b/components/asic/bm1370.c index 7ab12d506..05bc06788 100644 --- a/components/asic/bm1370.c +++ b/components/asic/bm1370.c @@ -111,7 +111,7 @@ static void _send_simple(uint8_t * data, uint8_t total_length) { unsigned char * buf = malloc(total_length); memcpy(buf, data, total_length); - SERIAL_send(buf, total_length, false); + SERIAL_send(buf, total_length, BM1370_SERIALTX_DEBUG); free(buf); } @@ -196,6 +196,11 @@ static void do_frequency_ramp_up(float target_frequency) { float current = 56.25; float step = 6.25; + if (target_frequency == 0) { + ESP_LOGI(TAG, "Skipping frequency ramp"); + return; + } + ESP_LOGI(TAG, "Ramping up frequency from %.2f MHz to %.2f MHz with step %.2f MHz", current, target_frequency, step); BM1370_send_hash_frequency(-1, current, 0.001); @@ -233,14 +238,13 @@ static uint8_t _send_init(uint64_t frequency, uint16_t asic_count) BM1370_set_version_mask(STRATUM_DEFAULT_VERSION_MASK); //Reg_A8 - unsigned char init5[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0xA8, 0x00, 0x07, 0x00, 0x00, 0x03}; - _send_simple(init5, 11); + //unsigned char init5[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0xA8, 0x00, 0x07, 0x00, 0x00, 0x03}; + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0xA8, 0x00, 0x07, 0x00, 0x00}, 6, BM1370_SERIALTX_DEBUG); //Misc Control - //**TX: 55 AA 51 09 00 18 F0 00 C1 00 04 //command all chips, write chip address 00, register 18, data F0 00 C1 00 - Misc Control - //unsigned char init6[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x18, 0xF0, 0x00, 0xC1, 0x00, 0x04}; //from S21Pro dump - unsigned char init6[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x18, 0xFF, 0x0F, 0xC1, 0x00, 0x00}; - _send_simple(init6, 11); + //TX: 55 AA 51 09 [00 18 F0 00 C1 00] 04 //command all chips, write chip address 00, register 18, data F0 00 C1 00 - Misc Control + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x18, 0xF0, 0x00, 0xC1, 0x00}, 6, BM1370_SERIALTX_DEBUG); //from S21Pro dump + //_send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x18, 0xFF, 0x0F, 0xC1, 0x00}, 6, BM1370_SERIALTX_DEBUG); //from S21 dump //chain inactive _send_chain_inactive(); @@ -256,53 +260,59 @@ static uint8_t _send_init(uint64_t frequency, uint16_t asic_count) } //Core Register Control - unsigned char init9[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x3C, 0x80, 0x00, 0x8B, 0x00, 0x12}; - _send_simple(init9, 11); + //unsigned char init9[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x3C, 0x80, 0x00, 0x8B, 0x00, 0x12}; + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x3C, 0x80, 0x00, 0x8B, 0x00}, 6, BM1370_SERIALTX_DEBUG); //Core Register Control - //**TX: 55 AA 51 09 00 3C 80 00 80 0C 11 //command all chips, write chip address 00, register 3C, data 80 00 80 0C - Core Register Control - //unsigned char init10[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x3C, 0x80, 0x00, 0x80, 0x0C, 0x11}; //from S21Pro dump - unsigned char init10[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x3C, 0x80, 0x00, 0x80, 0x18, 0x1F}; - _send_simple(init10, 11); + //TX: 55 AA 51 09 [00 3C 80 00 80 0C] 11 //command all chips, write chip address 00, register 3C, data 80 00 80 0C - Core Register Control + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x3C, 0x80, 0x00, 0x80, 0x0C}, 6, BM1370_SERIALTX_DEBUG); //from S21Pro dump + //_send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x3C, 0x80, 0x00, 0x80, 0x18}, 6, BM1370_SERIALTX_DEBUG); //from S21 dump //set ticket mask // unsigned char init11[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x14, 0x00, 0x00, 0x00, 0xFF, 0x08}; - // _send_simple(init11, 11); BM1370_set_job_difficulty_mask(BM1370_ASIC_DIFFICULTY); - //Analog Mux Control - unsigned char init12[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x54, 0x00, 0x00, 0x00, 0x03, 0x1D}; - _send_simple(init12, 11); + //Analog Mux Control -- not sent on S21 Pro? + // unsigned char init12[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x54, 0x00, 0x00, 0x00, 0x03, 0x1D}; + // _send_simple(init12, 11); //Set the IO Driver Strength on chip 00 - //**TX: 55 AA 51 09 00 58 00 01 11 11 0D //command all chips, write chip address 00, register 58, data 01 11 11 11 - Set the IO Driver Strength on chip 00 - //unsigned char init13[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x58, 0x00, 0x01, 0x11, 0x11, 0x0D}; //from S21Pro dump - unsigned char init13[11] = {0x55, 0xAA, 0x51, 0x09, 0x00, 0x58, 0x02, 0x11, 0x11, 0x11, 0x06}; - _send_simple(init13, 11); + //TX: 55 AA 51 09 [00 58 00 01 11 11] 0D //command all chips, write chip address 00, register 58, data 01 11 11 11 - Set the IO Driver Strength on chip 00 + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x58, 0x00, 0x01, 0x11, 0x11}, 6, BM1370_SERIALTX_DEBUG); //from S21Pro dump + //_send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x58, 0x02, 0x11, 0x11, 0x11}, 6, BM1370_SERIALTX_DEBUG); //from S21Pro dump + for (uint8_t i = 0; i < chip_counter; i++) { - //Reg_A8 + //TX: 55 AA 41 09 00 [A8 00 07 01 F0] 15 // Reg_A8 unsigned char set_a8_register[6] = {i * address_interval, 0xA8, 0x00, 0x07, 0x01, 0xF0}; _send_BM1370((TYPE_CMD | GROUP_SINGLE | CMD_WRITE), set_a8_register, 6, BM1370_SERIALTX_DEBUG); - //Misc Control + //TX: 55 AA 41 09 00 [18 F0 00 C1 00] 0C // Misc Control unsigned char set_18_register[6] = {i * address_interval, 0x18, 0xF0, 0x00, 0xC1, 0x00}; _send_BM1370((TYPE_CMD | GROUP_SINGLE | CMD_WRITE), set_18_register, 6, BM1370_SERIALTX_DEBUG); - //Core Register Control + //TX: 55 AA 41 09 00 [3C 80 00 8B 00] 1A // Core Register Control unsigned char set_3c_register_first[6] = {i * address_interval, 0x3C, 0x80, 0x00, 0x8B, 0x00}; _send_BM1370((TYPE_CMD | GROUP_SINGLE | CMD_WRITE), set_3c_register_first, 6, BM1370_SERIALTX_DEBUG); - //Core Register Control - //unsigned char set_3c_register_second[6] = {i * address_interval, 0x3C, 0x80, 0x00, 0x80, 0x0C}; //from S21Pro dump - unsigned char set_3c_register_second[6] = {i * address_interval, 0x3C, 0x80, 0x00, 0x80, 0x18}; + //TX: 55 AA 41 09 00 [3C 80 00 80 0C] 19 // Core Register Control + unsigned char set_3c_register_second[6] = {i * address_interval, 0x3C, 0x80, 0x00, 0x80, 0x0C}; _send_BM1370((TYPE_CMD | GROUP_SINGLE | CMD_WRITE), set_3c_register_second, 6, BM1370_SERIALTX_DEBUG); - //Core Register Control + //TX: 55 AA 41 09 00 [3C 80 00 82 AA] 05 // Core Register Control unsigned char set_3c_register_third[6] = {i * address_interval, 0x3C, 0x80, 0x00, 0x82, 0xAA}; _send_BM1370((TYPE_CMD | GROUP_SINGLE | CMD_WRITE), set_3c_register_third, 6, BM1370_SERIALTX_DEBUG); } + //Some misc settings? + // TX: 55 AA 51 09 [00 B9 00 00 44 80] 0D //command all chips, write chip address 00, register B9, data 00 00 44 80 + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0xB9, 0x00, 0x00, 0x44, 0x80}, 6, BM1370_SERIALTX_DEBUG); + // TX: 55 AA 51 09 [00 54 00 00 00 02] 18 //command all chips, write chip address 00, register 54, data 00 00 00 02 - Analog Mux Control - rumored to control the temp diode + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x54, 0x00, 0x00, 0x00, 0x02}, 6, BM1370_SERIALTX_DEBUG); + // TX: 55 AA 51 09 [00 B9 00 00 44 80] 0D //command all chips, write chip address 00, register B9, data 00 00 44 80 -- duplicate of first command in series + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0xB9, 0x00, 0x00, 0x44, 0x80}, 6, BM1370_SERIALTX_DEBUG); + // TX: 55 AA 51 09 [00 3C 80 00 8D EE] 1B //command all chips, write chip address 00, register 3C, data 80 00 8D EE + _send_BM1370((TYPE_CMD | GROUP_ALL | CMD_WRITE), (uint8_t[]){0x00, 0x3C, 0x80, 0x00, 0x8D, 0xEE}, 6, BM1370_SERIALTX_DEBUG); + + //ramp up the hash frequency do_frequency_ramp_up(frequency); - //BM1370_send_hash_frequency(frequency); - //register 10 is still a bit of a mystery. discussion: https://github.com/skot/ESP-Miner/pull/167 // unsigned char set_10_hash_counting[6] = {0x00, 0x10, 0x00, 0x00, 0x11, 0x5A}; //S19k Pro Default diff --git a/main/EMC2101.c b/main/EMC2101.c index daf1237ee..b941ea814 100644 --- a/main/EMC2101.c +++ b/main/EMC2101.c @@ -29,6 +29,18 @@ esp_err_t EMC2101_init(bool invertPolarity) { ESP_ERROR_CHECK(i2c_bitaxe_register_write_byte(emc2101_dev_handle, EMC2101_FAN_CONFIG, 0b00100011)); } + //set Ideality Factor + ESP_ERROR_CHECK(i2c_bitaxe_register_write_byte(emc2101_dev_handle, EMC2101_IDEALITY_FACTOR, EMC2101_DEFAULT_IDEALITY)); + + //set Beta Compensation + ESP_ERROR_CHECK(i2c_bitaxe_register_write_byte(emc2101_dev_handle, EMC2101_BETA_COMPENSATION, EMC2101_DEFAULT_BETA)); + + //set filtering + ESP_ERROR_CHECK(i2c_bitaxe_register_write_byte(emc2101_dev_handle, EMC2101_TEMP_FILTER, EMC2101_DEFAULT_FILTER)); + + //set conversion rate + ESP_ERROR_CHECK(i2c_bitaxe_register_write_byte(emc2101_dev_handle, EMC2101_REG_DATA_RATE, EMC2101_DEFAULT_DATARATE)); + return ESP_OK; } @@ -86,8 +98,10 @@ float EMC2101_get_external_temp(void) // Greater than 200C is probably an erroneous reading... if (result > 200){ - return EMC2101_get_internal_temp(); + ESP_LOGE(TAG, "EMC2101 Invalid result: %04X", reading); + result = 0; } + return result; } diff --git a/main/EMC2101.h b/main/EMC2101.h index 00c82a471..305255561 100644 --- a/main/EMC2101.h +++ b/main/EMC2101.h @@ -3,6 +3,85 @@ #include "i2c_bitaxe.h" +#define EMC2101_BETA_11 0x00 +#define EMC2101_BETA_18 0x01 +#define EMC2101_BETA_25 0x02 +#define EMC2101_BETA_33 0x03 +#define EMC2101_BETA_43 0x04 +#define EMC2101_BETA_100 0x05 +#define EMC2101_BETA_233 0x06 +#define EMC2101_BETA_DISABLED 0x07 +#define EMC2101_BETA_AUTO 0x08 + +#define EMC2101_FILTER_DISABLED 0x00 +#define EMC2101_FILTER_1 0x01 +#define EMC2101_FILTER_2 0x02 + +#define EMC2101_DATARATE_1_16_HZ 0x00 +#define EMC2101_DATARATE_1_8_HZ 0x01 +#define EMC2101_DATARATE_1_4_HZ 0x02 +#define EMC2101_DATARATE_1_2_HZ 0x03 +#define EMC2101_DATARATE_1_HZ 0x04 +#define EMC2101_DATARATE_2_HZ 0x05 +#define EMC2101_DATARATE_4_HZ 0x06 +#define EMC2101_DATARATE_8_HZ 0x07 +#define EMC2101_DATARATE_16_HZ 0x08 //default +#define EMC2101_DATARATE_32_HZ 0x09 + +#define EMC2101_IDEALITY_0_9949 0x08 +#define EMC2101_IDEALITY_0_9962 0x09 +#define EMC2101_IDEALITY_0_9975 0x0A +#define EMC2101_IDEALITY_0_9988 0x0B +#define EMC2101_IDEALITY_1_0001 0x0C +#define EMC2101_IDEALITY_1_0014 0x0D +#define EMC2101_IDEALITY_1_0027 0x0E +#define EMC2101_IDEALITY_1_0040 0x0F +#define EMC2101_IDEALITY_1_0053 0x10 +#define EMC2101_IDEALITY_1_0066 0x11 +#define EMC2101_IDEALITY_1_0080 0x12 //default +#define EMC2101_IDEALITY_1_0093 0x13 +#define EMC2101_IDEALITY_1_0106 0x14 +#define EMC2101_IDEALITY_1_0119 0x15 +#define EMC2101_IDEALITY_1_0133 0x16 +#define EMC2101_IDEALITY_1_0146 0x17 +#define EMC2101_IDEALITY_1_0159 0x18 +#define EMC2101_IDEALITY_1_0172 0x19 +#define EMC2101_IDEALITY_1_0185 0x1A +#define EMC2101_IDEALITY_1_0200 0x1B +#define EMC2101_IDEALITY_1_0212 0x1C +#define EMC2101_IDEALITY_1_0226 0x1D +#define EMC2101_IDEALITY_1_0239 0x1E +#define EMC2101_IDEALITY_1_0253 0x1F +#define EMC2101_IDEALITY_1_0267 0x20 +#define EMC2101_IDEALITY_1_0280 0x21 +#define EMC2101_IDEALITY_1_0293 0x22 +#define EMC2101_IDEALITY_1_0306 0x23 +#define EMC2101_IDEALITY_1_0319 0x24 +#define EMC2101_IDEALITY_1_0332 0x25 +#define EMC2101_IDEALITY_1_0345 0x26 +#define EMC2101_IDEALITY_1_0358 0x27 +#define EMC2101_IDEALITY_1_0371 0x28 +#define EMC2101_IDEALITY_1_0384 0x29 +#define EMC2101_IDEALITY_1_0397 0x2A +#define EMC2101_IDEALITY_1_0410 0x2B +#define EMC2101_IDEALITY_1_0423 0x2C +#define EMC2101_IDEALITY_1_0436 0x2D +#define EMC2101_IDEALITY_1_0449 0x2E +#define EMC2101_IDEALITY_1_0462 0x2F +#define EMC2101_IDEALITY_1_0475 0x30 +#define EMC2101_IDEALITY_1_0488 0x31 +#define EMC2101_IDEALITY_1_0501 0x32 +#define EMC2101_IDEALITY_1_0514 0x33 +#define EMC2101_IDEALITY_1_0527 0x34 +#define EMC2101_IDEALITY_1_0540 0x35 +#define EMC2101_IDEALITY_1_0553 0x36 +#define EMC2101_IDEALITY_1_0566 0x37 + +#define EMC2101_DEFAULT_IDEALITY EMC2101_IDEALITY_1_0319 ///< Default ideality factor +#define EMC2101_DEFAULT_BETA EMC2101_BETA_11 ///< Default beta compensation +#define EMC2101_DEFAULT_FILTER EMC2101_FILTER_1 ///< Default temp filter setting +#define EMC2101_DEFAULT_DATARATE EMC2101_DATARATE_32_HZ ///< Default temp conversion rate + #define EMC2101_I2CADDR_DEFAULT 0x4C ///< EMC2101 default i2c address #define EMC2101_CHIP_ID 0x16 ///< EMC2101 default device id from part id #define EMC2101_ALT_CHIP_ID 0x28 ///< EMC2101 alternate device id from part id @@ -18,6 +97,8 @@ #define EMC2101_REG_CONFIG 0x03 ///< configuration register #define EMC2101_REG_DATA_RATE 0x04 ///< Data rate config #define EMC2101_TEMP_FORCE 0x0C ///< Temp force setting for LUT testing +#define EMC2101_IDEALITY_FACTOR 0x17 ///< Beta Compensation Register +#define EMC2101_BETA_COMPENSATION 0x18 ///< Beta Compensation Register #define EMC2101_TACH_LSB 0x46 ///< Tach RPM data low byte #define EMC2101_TACH_MSB 0x47 ///< Tach RPM data high byte #define EMC2101_TACH_LIMIT_LSB 0x48 ///< Tach low-speed setting low byte. INVERSE OF THE SPEED diff --git a/main/self_test/self_test.c b/main/self_test/self_test.c index 89fcc9d5e..e2ac62c6b 100644 --- a/main/self_test/self_test.c +++ b/main/self_test/self_test.c @@ -18,6 +18,9 @@ #define POWER_CONSUMPTION_TARGET_GAMMA 11 //watts #define POWER_CONSUMPTION_MARGIN 3 //+/- watts +//define this to just print die temp endlessly +//#define TEMP_TESTING + static const char * TAG = "self_test"; bool should_test(GlobalState * GLOBAL_STATE) { @@ -118,6 +121,21 @@ static bool core_voltage_pass(GlobalState * GLOBAL_STATE) return false; } +#ifdef TEMP_TESTING + static void run_temp_cal(void) { + float external = 0, internal = 0; + + while (1) { + external = EMC2101_get_external_temp(); + internal = EMC2101_get_internal_temp(); + ESP_LOGI(TAG, "ASIC: %.3f, AIR: %.3f [%.3f]", external, internal, external - internal); + vTaskDelay(500 / portTICK_PERIOD_MS); + } + + } +#endif + + void self_test(void * pvParameters) { GlobalState * GLOBAL_STATE = (GlobalState *) pvParameters; @@ -175,7 +193,7 @@ void self_test(void * pvParameters) } uint8_t result = VCORE_init(GLOBAL_STATE); - VCORE_set_voltage(nvs_config_get_u16(NVS_CONFIG_ASIC_VOLTAGE, CONFIG_ASIC_VOLTAGE) / 1000.0, GLOBAL_STATE); + VCORE_set_voltage(1150 / 1000.0, GLOBAL_STATE); // VCore regulator testing switch (GLOBAL_STATE->device_model) { @@ -220,11 +238,17 @@ void self_test(void * pvParameters) default: } + uint8_t chips_detected = 0; SERIAL_init(); - uint8_t chips_detected = (GLOBAL_STATE->ASIC_functions.init_fn)(GLOBAL_STATE->POWER_MANAGEMENT_MODULE.frequency_value, GLOBAL_STATE->asic_count); + chips_detected = (GLOBAL_STATE->ASIC_functions.init_fn)(GLOBAL_STATE->POWER_MANAGEMENT_MODULE.frequency_value, GLOBAL_STATE->asic_count); ESP_LOGI(TAG, "%u chips detected, %u expected", chips_detected, GLOBAL_STATE->asic_count); + #ifdef TEMP_TESTING + run_temp_cal(); + #endif + + int baud = (*GLOBAL_STATE->ASIC_functions.set_max_baud_fn)(); vTaskDelay(10 / portTICK_PERIOD_MS); SERIAL_set_baud(baud);