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Fix Rust PLIC layout for ASIC #88

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hegza opened this issue Nov 1, 2024 · 0 comments
Open

Fix Rust PLIC layout for ASIC #88

hegza opened this issue Nov 1, 2024 · 0 comments

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@hegza
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hegza commented Nov 1, 2024

plic_codegen macro from riscv-peripherals works perfectly well for Headsail HPC (VP). However, if we want to do bare metal interrupts on ASIC, we could fork riscv-peripherals and fix the spacing in the codegen, like we do for OpenSBI at https://gitlab.tuni.fi/soc-hub/common/sw/baseport/-/blob/main/board/unknown-headsail/patches/opensbi/0003-Add-Headsail-SoC-PLIC-hotfix.patch.
@hegza hegza changed the title Fix Rust PLIC layout for Headsail Fix Rust PLIC layout for ASIC Nov 1, 2024
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