External Clocks
The Hermes-Lite 2.0 main board has two connectors for external clocks on the front panel, CL1 and CL2. CL1 is an input and accepts a clock from a master radio to synchronize two radios. It can also be used potentially as an alternate precision reference clock input. CL2 is an output and generates a master clock to synchronize a slave radio. CL2 can be configured from 1MHz to 200MHz and can potentially be used as the local oscillator for a transverter.
The clock generator in the Hermes-Lite 2.0 is the 5P49V5923. A detailed description of the device registers is found in the programming guide.
The gateware makes the clock generator registers accessible to software via the i2c interface at protocol address 0x3a with no response expected or 0x7a with response expected. The i2c address of the clock generator is 0xd4. To write a clock generator register, software must send 0x3c,0x06,0xea,reg,data as the 5 bytes of command and control. 0x3c is the protocol address. 0x06 is the i2c write cookie. 0xea can be written as the concatenation of 0b1,0x6a where the single set bit 0b1 enables the i2c stop bit and the value 0x6a is the i2c address shifted right by 1 bit. The reg byte is the clock generator register address. The data byte is the value to write.
Likewise, to read a clock generator register, software must send 0x3c,0x07,0xea,reg,dont_care as the 5 bytes of command and control. This is similar to the write command except 0x07 is the read cookie. Software will see the byte read as part of the response described on the protocol wiki page.
It is helpful when programming software for the Hermes-Lite 2.0 to be able to insert arbitrary command and control sequences into the stream sent to the Hermes-Lite 2.0, and to handle responses. An example of how to do this, including clock generator methods, are part of Quisk. See the download link on that page for the source code, and then the file hermes/quisk_hardware.py.
When the Hermes-Lite 2.0 is powered on, a state machine in the gateware does initial programming of the clock generator. This turns on clock output 1, the one connected to the AD9866, and sets the frequency to 76.8MHz. The register write sequence is shown below.
| Register | Value | Description |
|---|---|---|
| 0x17 | 0x04 | FB_intdiv[11:4] |
| 0x18 | 0x40 | FB_intdiv[3:0] |
| 0x1e | 0xe8 | RC control register |
| 0x1f | 0x80 | RC control register |
| 0x2d | 0x01 | OD1_intdiv[11:4] |
| 0x2e | 0x10 | OD1_intdiv[3:0] |
| 0x60 | 0x3b | Clock 1 output configuration |
The value FB_intdiv[11:0] is a 12-bit value which multiplies the input clock to set the VCO frequency. For the current Hermes-Lite 2.0 configuration we have a 38.4MHz precision oscillator which is multiplied by 0x044 to run the VCO at 2611.2MHz.
The VCO frequency has a hardcoded divide by 2, and then is further divided by OD1_intdiv. For the Hermes-Lite 2.0, this is 2611.2/2/0x011 which equals 76.8MHz. Although the clock generator is capable of fractional division, we are not using that to keep jitter to a minimum.
The other values for RC control register and Clock 1 output configuration complete setup for a 3.3V CMOS output use of clock 1. They were determined using the Timing Commander Software. This software is a good way to understand how to set various clock generator registers.
CL2 can be set to generate a 76.8MHz synchronous output for a slave radio. The general idea is to set the output divider for clock 2 (OD2_intdiv) to be the same as clock 1, reset both divider counters to align the edges, but include a skew value for clock 2 so that once the clock passes through the clock generator in the slave radio, it is still aligned with the master when both clocks arrive at the AD9866.
| Register | Value | Description |
|---|---|---|
| 0x62 | 0x3b | Set clock2 to CMOS 3.3V |
| 0x3d | 0x01 | OD1_intdiv[11:4] |
| 0x3e | 0x10 | OD1_intdiv[3:0] |
| 0x31 | 0x81 | Enable divider for clock 2 |
| 0x3c | 0x00 | integer skew if required |
| 0x3f | 0x1f | fractional skew |
| 0x63 | 0x01 | Enable clock 2 output |
This configuration is very similar to the initial clock 1 configuration. It includes integer and fractional skew values. These values were determined experimentally to best align the final clocks at the two AD9866 devices. The values may be refined in the future. If the integer skew is 0x00, it need not be written.
Once clock 2 is setup and enabled, the clock generator must be reset to properly align clock 2 with clock 1. This can't be done through software as the reset process turns off the clock generator and this can't be tolerated for a long period of time. The protocol now supports this reset by writing 1 bit[0] at protocol address 0x39. Internally, this writes 0x43 and then 0x63 to clock generator register 0x76.
To turn off the CL2 clock, please program the following:
| Register | Value | Description |
|---|---|---|
| 0x31 | 0x80 | Disable divider for clock 2 |
| 0x63 | 0x00 | Disable clock 2 output |
CL1 can be set as the source of the clock generator so that a slave radio can synchronize with a master. The general idea is to switch the input from crystal oscillator to external, and then connect clock 1 output directly to the new input from within the clock generator. The PLL is not used in this case as there is no known way to align the output clocks from two separate clock generators. The path used through clock buffer and mux directly to OUT1 mux is seen in the functional block diagram on page 2 of the datasheet. The clock buffer and muxes add a small delay. This is why there is a small fractional skew added to clock 2 of the master. It is untested how much jitter or phase noise is added by the extra buffer and muxes, but no evidence of increased noise is seen on any waterfall displays.
To switch to the CL1 input, please program:
| Register | Value | Description |
|---|---|---|
| 0x17 | 0x02 | FB_intdiv[11:4] Adjust multiplication for new 76.8MHz reference |
| 0x18 | 0x20 | FB_intdiv[3:0] |
| 0x10 | 0xc0 | Enable both local oscillator and external clock inputs |
| 0x13 | 0x03 | Switch to external clock |
| 0x10 | 0x44 | Enable external clock input only plus refmode |
| 0x21 | 0x0c | Use previous channel, bypass divider |
To switch back to the local crystal oscillator, please program:
| Register | Value | Description |
|---|---|---|
| 0x10 | 0xc4 | Enable both local oscillator and external clock inputs plus refmod |
| 0x21 | 0x81 | Enable divider |
| 0x13 | 0x00 | Switch to local oscillator |
| 0x10 | 0x80 | Enable local oscillator, no external clock and refmod |
| 0x17 | 0x04 | FB_intdiv[11:4] Adjust multiplication for new 38.4MHz reference |
| 0x18 | 0x40 | FB_intdiv[3:0] |
Besides synchronizing clocks, all delay elements in the gateware receive path as well as numerical oscillators must be synchronized.
Two HL2s must be linked as shown below. Note that on one HL2 the red wire of the 6-pin ribbon cable is on the right and the other HL2 has it on the left. The red wire must be on opposite sides for each HL2.
Enable the HL2 link by setting bit 31 at address 0x39.
Designate one radio as the master producing a clock on CL2 and the other a slave accepting a clock on CL1. Synchronize the clocks as described in the previous sections. Clocks must be synchronized for the next steps to work properly.
There are two resets associated with synchronized RX. Reseting all receive elements will flush all RX buffers, stall the UDP upstream to PC very briefly (should not be noticeable by software), clear the EP4 sequence number, and clear all filter and decimation counters. This guarantees that receive samples at the same offset within UDP packets with the same EP4 sequence number should be coherent. This more costly reset all should only be required once after clocks are synchronized and the hl2 link enabled.
Reset all is bit 25 at address 0x39. Reset occurs every time the HL2 receives a command word with this bit set. Do not disable the hl2 link which is enabled by bit 31 at address 0x39 when sending this reset.
The phase angle of each receiver NCO is not aligned by default. Resetting NCOs causes all NCOs phase accumulators to be reset to 0 in a synchronous fasion. The current use model is to set receivers in the master and slave to the same frequency, and then do the less costly reset NCOs. Note that all NCOs are reset so any two receivers can be synchronized.
Reset NCOs is bit 24 at address 0x39. Reset occurs every time the HL2 receives a command word with this bit set. Do not disable the hl2 link which is enabled by bit 31 at address 0x39 when sending this reset. You can't send both Reset All and Reset NCOs in the same packet. The HL2 will currently ignore a command with both bits 24 and 25 set.