Throughput gap between different TDD periods

[HaoxinSEU]

Hello,

When using different TDD periods, it seems that the maximum throughput is different.

For example, we are using USRP with 20 MHz BW, when setting the period as 10 slots:

  tdd_ul_dl_cfg: 
    dl_ul_tx_period: 10                   
    nof_dl_slots: 6                        
    nof_dl_symbols: 6               
    nof_ul_slots: 3                       
    nof_ul_symbols: 6                   

The throughput for DL and UL is 57.7 Mbps and 17.9 Mbps respectively.

When setting the period as 4 slots:

  tdd_ul_dl_cfg: 
    dl_ul_tx_period: 4                   
    nof_dl_slots: 2                       
    nof_dl_symbols: 6               
    nof_ul_slots: 1                       
    nof_ul_symbols: 6 

The throughput for DL and UL is 52.7 and 14.7 Mbps.

There are more UL symbols in the period now, but the UL throughput decreases. In theory the control overhead should not change. So we are wondering if this difference is normal and what could be the reason?

Any insight will be much appreciated!

[herlesupreeth]

By default min k1 and min k2 is set to 4 so when using the second TDD pattern (4slots) you may want to reduce the min k1 and min k2 to 2. You can do that from gnb configuration file

[HaoxinSEU]

Hi @herlesupreeth ,

Thanks for your reply! We see that these two parameters can contribute to different latencies. But why are they also related to the throughput gap? Do you mean we may waste some slots if k1 and k2 are too large compared to the period?

Thanks again!

[herlesupreeth]

min k1 and min k2 based on a TDD pattern mainly affects latency

UL slots are not only used for data (PUSCH) but also for PUCCH to send Ack and CSI reports. Also in the case of TDD pattern periodicity of 4 slots the nof UL slots are less compared to the TDD pattern with 10 slots

[frankist]

Do you mean we may waste some slots if k1 and k2 are too large compared to the period?

Yes, I think that was what was likely happening. Reducing the min k1/k2 gives the scheduler more options to allocate the PUSCH. If k2>=4 for a TDD pattern period of 4 slots, the UL-PDCCH and the PUSCH would likely have to be placed in different TDD patterns. However, the best way to understand what this combination of parameters causes is by looking at the mac logs in debug.

[HaoxinSEU]

Thanks for your reply! We will do more experiments with different min k1 and k2 to see their effects.