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timing_report.txt
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timing_report.txt
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Wed Oct 18 23:58:09 2023
| Host : ubuntu2004 running 64-bit Ubuntu 20.04.4 LTS
| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2 -file /home/ubuntu/Desktop/fir_vivado/fir/timing_report.txt
| Design : fir
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.12 2019-11-22
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
Rule Severity Description Violations
--------- ---------------- --------------------------- ----------
TIMING-17 Critical Warning Non-clocked sequential cell 68
RTGT-1 Advisory RAM retargeting possibility 4
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (62)
6. checking no_output_delay (119)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (62)
-------------------------------
There are 62 input ports with no input delay specified. (HIGH)
araddr[0]
araddr[10]
araddr[11]
araddr[1]
araddr[2]
araddr[3]
araddr[4]
araddr[5]
araddr[6]
araddr[7]
araddr[8]
araddr[9]
arvalid
awaddr[0]
awaddr[10]
awaddr[11]
awaddr[1]
awaddr[2]
awaddr[3]
awaddr[4]
awaddr[5]
awaddr[6]
awaddr[7]
awaddr[8]
awaddr[9]
awvalid
axis_rst_n
sm_tready
ss_tvalid
wdata[0]
wdata[10]
wdata[11]
wdata[12]
wdata[13]
wdata[14]
wdata[15]
wdata[16]
wdata[17]
wdata[18]
wdata[19]
wdata[1]
wdata[20]
wdata[21]
wdata[22]
wdata[23]
wdata[24]
wdata[25]
wdata[26]
wdata[27]
wdata[28]
wdata[29]
wdata[2]
wdata[30]
wdata[31]
wdata[3]
wdata[4]
wdata[5]
wdata[6]
wdata[7]
wdata[8]
wdata[9]
wvalid
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (119)
---------------------------------
There are 119 ports with no output delay specified. (HIGH)
arready
awready
data_A[2]
data_A[3]
data_A[4]
data_A[5]
data_Di[0]
data_Di[10]
data_Di[11]
data_Di[12]
data_Di[13]
data_Di[14]
data_Di[15]
data_Di[16]
data_Di[17]
data_Di[18]
data_Di[19]
data_Di[1]
data_Di[20]
data_Di[21]
data_Di[22]
data_Di[23]
data_Di[24]
data_Di[25]
data_Di[26]
data_Di[27]
data_Di[28]
data_Di[29]
data_Di[2]
data_Di[30]
data_Di[31]
data_Di[3]
data_Di[4]
data_Di[5]
data_Di[6]
data_Di[7]
data_Di[8]
data_Di[9]
data_WE[0]
data_WE[1]
data_WE[2]
data_WE[3]
rdata[0]
rdata[10]
rdata[11]
rdata[12]
rdata[13]
rdata[14]
rdata[15]
rdata[16]
rdata[17]
rdata[18]
rdata[19]
rdata[1]
rdata[20]
rdata[21]
rdata[22]
rdata[23]
rdata[24]
rdata[25]
rdata[26]
rdata[27]
rdata[28]
rdata[29]
rdata[2]
rdata[30]
rdata[31]
rdata[3]
rdata[4]
rdata[5]
rdata[6]
rdata[7]
rdata[8]
rdata[9]
rvalid
sm_tdata[0]
sm_tdata[10]
sm_tdata[11]
sm_tdata[12]
sm_tdata[13]
sm_tdata[14]
sm_tdata[15]
sm_tdata[16]
sm_tdata[17]
sm_tdata[18]
sm_tdata[19]
sm_tdata[1]
sm_tdata[20]
sm_tdata[21]
sm_tdata[22]
sm_tdata[23]
sm_tdata[24]
sm_tdata[25]
sm_tdata[26]
sm_tdata[27]
sm_tdata[28]
sm_tdata[29]
sm_tdata[2]
sm_tdata[30]
sm_tdata[31]
sm_tdata[3]
sm_tdata[4]
sm_tdata[5]
sm_tdata[6]
sm_tdata[7]
sm_tdata[8]
sm_tdata[9]
sm_tlast
sm_tvalid
ss_tready
tap_A[2]
tap_A[3]
tap_A[4]
tap_A[5]
tap_WE[0]
tap_WE[1]
tap_WE[2]
tap_WE[3]
wready
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.006 0.000 0 189 0.132 0.000 0 189 1.810 0.000 0 114
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk {0.000 2.310} 4.620 216.450
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk 0.006 0.000 0 189 0.132 0.000 0 189 1.810 0.000 0 114
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
(none)
(none) clk
(none) clk
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk
To Clock: clk
Setup : 0 Failing Endpoints, Worst Slack 0.006ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.132ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.810ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.006ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[0]/CE
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 4.232ns (logic 1.145ns (27.056%) route 3.087ns (72.944%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 f len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
f rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 f rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
f rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 f rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
f rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 f rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
f DATA_BRAM_addr[3]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[3]_i_1/O
net (fo=4, unplaced) 0.497 6.473 data_addr_wen
FDCE r DATA_BRAM_addr_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[0]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_CE) -0.202 6.478 DATA_BRAM_addr_reg[0]
-------------------------------------------------------------------
required time 6.478
arrival time -6.473
-------------------------------------------------------------------
slack 0.006
Slack (MET) : 0.006ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[1]/CE
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 4.232ns (logic 1.145ns (27.056%) route 3.087ns (72.944%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 f len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
f rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 f rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
f rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 f rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
f rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 f rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
f DATA_BRAM_addr[3]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[3]_i_1/O
net (fo=4, unplaced) 0.497 6.473 data_addr_wen
FDCE r DATA_BRAM_addr_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[1]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_CE) -0.202 6.478 DATA_BRAM_addr_reg[1]
-------------------------------------------------------------------
required time 6.478
arrival time -6.473
-------------------------------------------------------------------
slack 0.006
Slack (MET) : 0.006ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[2]/CE
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 4.232ns (logic 1.145ns (27.056%) route 3.087ns (72.944%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 f len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
f rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 f rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
f rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 f rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
f rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 f rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
f DATA_BRAM_addr[3]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[3]_i_1/O
net (fo=4, unplaced) 0.497 6.473 data_addr_wen
FDCE r DATA_BRAM_addr_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[2]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_CE) -0.202 6.478 DATA_BRAM_addr_reg[2]
-------------------------------------------------------------------
required time 6.478
arrival time -6.473
-------------------------------------------------------------------
slack 0.006
Slack (MET) : 0.006ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[3]/CE
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 4.232ns (logic 1.145ns (27.056%) route 3.087ns (72.944%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 f len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
f rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 f rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
f rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 f rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
f rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 f rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
f DATA_BRAM_addr[3]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[3]_i_1/O
net (fo=4, unplaced) 0.497 6.473 data_addr_wen
FDCE r DATA_BRAM_addr_reg[3]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[3]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_CE) -0.202 6.478 DATA_BRAM_addr_reg[3]
-------------------------------------------------------------------
required time 6.478
arrival time -6.473
-------------------------------------------------------------------
slack 0.006
Slack (MET) : 0.749ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[0]/D
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 3.735ns (logic 1.145ns (30.656%) route 2.590ns (69.344%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 r len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
r rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 r rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
r rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 r rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
r rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 r rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
r DATA_BRAM_addr[0]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[0]_i_1/O
net (fo=1, unplaced) 0.000 5.976 DATA_BRAM_addr[0]_i_1_n_0
FDCE r DATA_BRAM_addr_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[0]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_D) 0.044 6.724 DATA_BRAM_addr_reg[0]
-------------------------------------------------------------------
required time 6.724
arrival time -5.976
-------------------------------------------------------------------
slack 0.749
Slack (MET) : 0.749ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[1]/D
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 3.735ns (logic 1.145ns (30.656%) route 2.590ns (69.344%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 r len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
r rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 r rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
r rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 r rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
r rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 r rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
r DATA_BRAM_addr[1]_i_1/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[1]_i_1/O
net (fo=1, unplaced) 0.000 5.976 DATA_BRAM_addr[1]_i_1_n_0
FDCE r DATA_BRAM_addr_reg[1]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[1]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_D) 0.044 6.724 DATA_BRAM_addr_reg[1]
-------------------------------------------------------------------
required time 6.724
arrival time -5.976
-------------------------------------------------------------------
slack 0.749
Slack (MET) : 0.749ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[2]/D
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 3.735ns (logic 1.145ns (30.656%) route 2.590ns (69.344%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 r len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
r rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 r rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
r rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 r rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
r rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 r rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
r DATA_BRAM_addr[2]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.124 5.976 r DATA_BRAM_addr[2]_i_1/O
net (fo=1, unplaced) 0.000 5.976 DATA_BRAM_addr[2]_i_1_n_0
FDCE r DATA_BRAM_addr_reg[2]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[2]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_D) 0.044 6.724 DATA_BRAM_addr_reg[2]
-------------------------------------------------------------------
required time 6.724
arrival time -5.976
-------------------------------------------------------------------
slack 0.749
Slack (MET) : 0.749ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: DATA_BRAM_addr_reg[3]/D
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 3.735ns (logic 1.145ns (30.656%) route 2.590ns (69.344%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.584 1.556 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.101 1.657 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.584 2.241 axis_clk_IBUF_BUFG
FDCE r len_reg[31]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.719 r len_reg[31]/Q
net (fo=2, unplaced) 0.752 3.471 len[31]
r rvalid_OBUF_inst_i_9/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.766 r rvalid_OBUF_inst_i_9/O
net (fo=1, unplaced) 0.449 4.215 rvalid_OBUF_inst_i_9_n_0
r rvalid_OBUF_inst_i_5/I4
LUT5 (Prop_lut5_I4_O) 0.124 4.339 r rvalid_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.902 5.241 rvalid_OBUF_inst_i_5_n_0
r rvalid_OBUF_inst_i_3/I1
LUT4 (Prop_lut4_I1_O) 0.124 5.365 r rvalid_OBUF_inst_i_3/O
net (fo=8, unplaced) 0.487 5.852 rvalid_OBUF_inst_i_3_n_0
r DATA_BRAM_addr[3]_i_2/I3
LUT6 (Prop_lut6_I3_O) 0.124 5.976 r DATA_BRAM_addr[3]_i_2/O
net (fo=1, unplaced) 0.000 5.976 DATA_BRAM_addr[3]_i_2_n_0
FDCE r DATA_BRAM_addr_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 4.620 4.620 r
0.000 4.620 r axis_clk (IN)
net (fo=0) 0.000 4.620 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 5.458 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.439 5.897 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I0
BUFGCTRL (Prop_bufgctrl_I0_O)
0.091 5.988 r axis_clk_IBUF_BUFG_inst/O
net (fo=113, unplaced) 0.439 6.427 axis_clk_IBUF_BUFG
FDCE r DATA_BRAM_addr_reg[3]/C
clock pessimism 0.289 6.716
clock uncertainty -0.035 6.680
FDCE (Setup_fdce_C_D) 0.044 6.724 DATA_BRAM_addr_reg[3]
-------------------------------------------------------------------
required time 6.724
arrival time -5.976
-------------------------------------------------------------------
slack 0.749
Slack (MET) : 0.779ns (required time - arrival time)
Source: len_reg[31]/C
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Destination: state_reg[1]/D
(rising edge-triggered cell FDCE clocked by clk {[email protected] [email protected] period=4.620ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.620ns (clk [email protected] - clk [email protected])
Data Path Delay: 3.705ns (logic 1.145ns (30.904%) route 2.560ns (69.096%))
Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.807ns = ( 6.427 - 4.620 )
Source Clock Delay (SCD): 2.241ns
Clock Pessimism Removal (CPR): 0.289ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r