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Update amm2lb_verilog.j2 pytest #21: Commit 924f9fb pushed by stdefeber
September 13, 2024 12:25 2m 23s fix_avalon_reads
fix_avalon_reads
September 13, 2024 12:25 2m 23s
Fixed avalon reads pytest #20: Commit 43447e6 pushed by stdefeber
September 12, 2024 14:11 2m 18s fix_avalon_reads
fix_avalon_reads
September 12, 2024 14:11 2m 18s
Update amm2lb_vhdl.j2 pytest #19: Commit 60b0169 pushed by stdefeber
September 12, 2024 13:42 2m 30s fix_avalon_reads
fix_avalon_reads
September 12, 2024 13:42 2m 30s
Fixed avalon reads pytest #18: Commit b0b843c pushed by stdefeber
September 12, 2024 13:35 2m 31s fix_avalon_reads
fix_avalon_reads
September 12, 2024 13:35 2m 31s
Fixed avalon reads pytest #17: Commit 2086d9e pushed by stdefeber
September 12, 2024 13:32 3m 31s fix_avalon_reads
fix_avalon_reads
September 12, 2024 13:32 3m 31s
Corrected instantiation pytest #16: Commit 235aad1 pushed by stdefeber
August 14, 2024 14:52 3m 4s feature/wishbone
feature/wishbone
August 14, 2024 14:52 3m 4s
fixed typos pytest #15: Commit 4c33074 pushed by stdefeber
August 14, 2024 14:38 2m 45s feature/wishbone
feature/wishbone
August 14, 2024 14:38 2m 45s
Adding missing wb signals to dut of rmap tc's pytest #14: Commit e4d3e26 pushed by stdefeber
August 14, 2024 14:07 2m 59s feature/wishbone
feature/wishbone
August 14, 2024 14:07 2m 59s
readdata -> wb_dat_o pytest #13: Commit db5a273 pushed by stdefeber
August 14, 2024 13:49 2m 45s feature/wishbone
feature/wishbone
August 14, 2024 13:49 2m 45s
Removed useless signal and waiting for ack in a different way pytest #12: Commit 53b735a pushed by stdefeber
August 14, 2024 13:41 2m 27s feature/wishbone
feature/wishbone
August 14, 2024 13:41 2m 27s
Reset of FSM incorrectly implemented, text mods pytest #11: Commit 9e0c20c pushed by stdefeber
August 14, 2024 12:36 3m 36s feature/wishbone
feature/wishbone
August 14, 2024 12:36 3m 36s
Added missing wb master pytest #10: Commit 499cf3f pushed by stdefeber
August 14, 2024 11:49 3m 3s feature/wishbone
feature/wishbone
August 14, 2024 11:49 3m 3s
Moved FSM state definition before jinja if statement pytest #9: Commit 33963a2 pushed by stdefeber
August 14, 2024 11:40 3m 1s feature/wishbone
feature/wishbone
August 14, 2024 11:40 3m 1s
Added missing verilog heaader file for WB to local bus pytest #8: Commit 10ad9bb pushed by stdefeber
August 14, 2024 11:27 4m 8s feature/wishbone
feature/wishbone
August 14, 2024 11:27 4m 8s
Update test_lb_bridge.py pytest #7: Commit 2914ee7 pushed by stdefeber
August 14, 2024 11:11 3m 9s feature/wishbone
feature/wishbone
August 14, 2024 11:11 3m 9s
Added missing wishbone to the mix pytest #6: Commit a58e530 pushed by stdefeber
August 14, 2024 10:16 2m 37s feature/wishbone
feature/wishbone
August 14, 2024 10:16 2m 37s
Create test-feature.yml pytest #5: Commit 9823613 pushed by stdefeber
August 14, 2024 10:07 3m 13s master
master
August 14, 2024 10:07 3m 13s
Update test_lb_bridge.py pytest #4: Commit f22a8d4 pushed by stdefeber
August 14, 2024 10:01 2m 41s master
master
August 14, 2024 10:01 2m 41s
Update test_lb_bridge.py pytest #3: Commit 83defb5 pushed by stdefeber
August 14, 2024 09:42 2m 46s master
master
August 14, 2024 09:42 2m 46s
Update test_lb_bridge.py pytest #2: Commit 5109c7e pushed by stdefeber
August 14, 2024 09:26 2m 32s master
master
August 14, 2024 09:26 2m 32s
Create manual.yml pytest #1: Commit 67481c7 pushed by stdefeber
August 14, 2024 09:18 2m 42s master
master
August 14, 2024 09:18 2m 42s