Capture 32 bit input

[Stefan-Olt]

Hi,
I would like to sample 32 bit input (at 40 MHz) for my project. My first idea is to run the pll0_clk at twice the speed and buffer the second half of each sample:

    always @(posedge pll0_clk) begin
        if (clock_adc == 0) begin
            clock_adc <= 1;
            fifo_in <= adcin[15:0];
            tmp_reg <= adcin[31:16];
        end else begin
            clock_adc <= 0;
            fifo_in <= tmp_reg;
        end
        counter <= counter + 1'b1;
    end

The problem I see is synchronization: I would have to ensure that every frame contains an even number of samples, otherwise if I start capturing at some point all data would be miss-aligned by 2 bytes. Any good idea on that? Or is it a better approach to change the fifo sample size to 32 bit and modify hsdaoh_core somehow to work with 32 bit samples?
Best regards
Stefan

[steve-m]

In my opinion it's definitely easier to use a 32 bit fifo and deal with the 32->16 bit conversion in the clk_pixel process.
In the sdr branch (https://github.com/steve-m/hsdaoh-fpga/tree/sdr) I implemented 2x 10 bit ADC input this way, using a 20 bit FIFO and then using a state machine controlling the FIFO readout accordingly to get 16 bit output (the corresponding host unpacking code can be found in the sdr branch of the hsdaoh repo).

I also wanted to do the same for 2x cheap 12 bit AD9226 boards for vhsdecode purposes, I guess you want to use it as an interface for MISRC ;)

[Stefan-Olt]

Yes, that's my intention. I cannot get the fx3 board working reliable and Cypress has this bad licensing terms that forbids you to distribute any binary using their SDK without a Cypress product.
I see the SDR branch is a much better starting point, I think I'm able to figure out how to get 32 bit working from there.

Btw, I'm happy for any input on MISRC, I'm not a professional electrical engineer, if you have any ideas/improvements feel free to open issues/make pull requests.