From 66a8237ed66eed53360b501b3f90547b614cb34c Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 9 Feb 2024 17:09:06 +0100 Subject: [PATCH] [docs] add cache clear operation --- docs/datasheet/soc_dcache.adoc | 6 ++---- docs/datasheet/soc_icache.adoc | 6 ++---- docs/datasheet/soc_xip.adoc | 3 +++ 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/docs/datasheet/soc_dcache.adoc b/docs/datasheet/soc_dcache.adoc index 588881376..2aecac5ce 100644 --- a/docs/datasheet/soc_dcache.adoc +++ b/docs/datasheet/soc_dcache.adoc @@ -24,13 +24,12 @@ equal to 4 bytes) and `DCACHE_NUM_BLOCKS` (the total amount of cache blocks; has equal to 1) generics. The data cache provides only a single set, hence it is direct-mapped. -**Cached/Unached Accesses** +**Cached/Uncached Accesses** The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF` will not be cached at all (see section <<_address_space>>). - .Caching Internal Memories [NOTE] The data cache is intended to accelerate data access to **processor-external** memories @@ -39,8 +38,7 @@ when using only processor-internal data and instruction memories. .Manual Cache Clear/Reload [NOTE] -By executing the `fence` instruction (<<_i_isa_extension>>) the cache is cleared and a reload from -main memory is triggered. +By executing the `fence(.i)` instruction the cache is cleared and a reload from main memory is triggered. .Retrieve Cache Configuration from Software [TIP] diff --git a/docs/datasheet/soc_icache.adoc b/docs/datasheet/soc_icache.adoc index 31f25de80..a3e2a1600 100644 --- a/docs/datasheet/soc_icache.adoc +++ b/docs/datasheet/soc_icache.adoc @@ -27,13 +27,12 @@ set-associative) generics. If the cache associativity is greater than one the LR used) is used. -**Cached/Unached Accesses** +**Cached/Uncached Accesses** The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF` will not be cached at all (see section <<_address_space>>). - .Caching Internal Memories [NOTE] The instruction cache is intended to accelerate instruction fetches from **processor-external** memories @@ -42,8 +41,7 @@ when using only processor-internal data and instruction memories. .Manual Cache Clear/Reload [NOTE] -By executing the `fence.i` instruction (<<_zifencei_isa_extension>>) the cache is cleared and a reload from -main memory is triggered. This also allows to implement self-modifying code. +By executing the `fence(.i)` instruction the cache is cleared and a reload from main memory is triggered. .Retrieve Cache Configuration from Software [TIP] diff --git a/docs/datasheet/soc_xip.adoc b/docs/datasheet/soc_xip.adoc index cc1e9d200..55772b989 100644 --- a/docs/datasheet/soc_xip.adoc +++ b/docs/datasheet/soc_xip.adoc @@ -175,6 +175,9 @@ cache layout: When the cache is implemented, the XIP module operates in **burst mode** utilizing the flash's _incremental read_ capabilities. Thus, several bytes (= `XIP_CACHE_BLOCK_SIZE`) are read consecutively from the flash using a single read command. +The XIP cache is cleared when the XIP module is disabled (`XIP_CTRL_EN = 0`), when XIP mode is disabled +(`XIP_CTRL_XIP_EN = 0`) or when the CPU issues a `fence(.i)` instruction. + **Register Map**