From 750f141ef1803abd96a8ea60fa33d5a52635bcbb Mon Sep 17 00:00:00 2001 From: stnolting Date: Thu, 3 Oct 2024 22:10:43 +0200 Subject: [PATCH] [top] set CLOCK_FREQUENCY = 0 as default --- docs/datasheet/soc.adoc | 2 +- rtl/core/neorv32_package.vhd | 2 +- rtl/core/neorv32_top.vhd | 6 +++++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index ac2c531a4..642c04609 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -196,7 +196,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt |======================= | Name | Type | Default | Description 4+^| **General** -| `CLOCK_FREQUENCY` | natural | - | The clock frequency of the processor's `clk_i` input port in Hertz (Hz). +| `CLOCK_FREQUENCY` | natural | 0 | The clock frequency of the processor's `clk_i` input port in Hertz (Hz). | `CLOCK_GATING_EN` | boolean | false | Enable clock gating when CPU is in sleep mode (see sections <<_sleep_mode>> and <<_processor_clocking>>). | `INT_BOOTLOADER_EN` | boolean | false | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image. | `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSR). diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 0ffd3cdab..0fca399c8 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -668,7 +668,7 @@ package neorv32_package is component neorv32_top generic ( -- General -- - CLOCK_FREQUENCY : natural; + CLOCK_FREQUENCY : natural := 0; CLOCK_GATING_EN : boolean := false; HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000"; diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index fc86aa405..9b5e2d932 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -22,7 +22,7 @@ use neorv32.neorv32_package.all; entity neorv32_top is generic ( -- General -- - CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000"; -- JEDEC ID: continuation codes + vendor ID @@ -374,6 +374,10 @@ begin assert not (io_sysinfo_en_c = false) report "[NEORV32] SYSINFO module disabled - some parts of the NEORV32 software framework will no longer work!" severity warning; + -- Clock speed not defined -- + assert not (CLOCK_FREQUENCY = 0) report + "[NEORV32] CLOCK_FREQUENCY must be configured according to the frequency of clk_i port!" severity warning; + end generate; -- /sanity_checks