From 7e7e360b7fc6cf67f245afabe611faf76637a2f9 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 9 Feb 2024 16:58:30 +0100 Subject: [PATCH] :warning: [top] remove fence signals --- rtl/core/neorv32_top.vhd | 23 ++++--------------- .../neorv32_SystemTop_AvalonMM.vhd | 8 ------- .../neorv32_SystemTop_axi4lite.vhd | 3 --- sim/neorv32_tb.vhd | 3 --- sim/simple/neorv32_tb.simple.vhd | 3 --- 5 files changed, 4 insertions(+), 36 deletions(-) diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index 6e94b15ad..77997e84c 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -186,11 +186,7 @@ entity neorv32_top is slink_rx_rdy_o : out std_ulogic; -- RX ready to receive slink_tx_dat_o : out std_ulogic_vector(31 downto 0); -- TX output data slink_tx_val_o : out std_ulogic; -- TX valid output - slink_tx_rdy_i : in std_ulogic := 'L'; -- TX ready to send - - -- Advanced memory control signals -- - fence_o : out std_ulogic; -- indicates an executed FENCE operation - fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + slink_tx_rdy_i : in std_ulogic := 'L'; -- TX ready to send -- XIP (execute in place via SPI) signals (available if XIP_EN = true) -- xip_csn_o : out std_ulogic; -- chip-select, low-active @@ -298,10 +294,7 @@ architecture neorv32_top_rtl of neorv32_top is signal cg_en : cg_en_t; -- CPU status -- - signal cpu_debug : std_ulogic; -- cpu is in debug mode - signal cpu_sleep : std_ulogic; -- cpu is in sleep mode - signal i_fence : std_ulogic; -- instruction fence - signal d_fence : std_ulogic; -- data fence + signal cpu_debug, cpu_sleep : std_ulogic; -- cpu is in debug/sleep mode -- debug module interface (DMI) -- signal dmi_req : dmi_req_t; @@ -358,8 +351,8 @@ begin -- say hello -- assert false report - "The NEORV32 RISC-V Processor, " & - "version 0x" & to_hstring32_f(hw_version_c) & ", " & + "[NEORV32] The NEORV32 RISC-V Processor " & + "(version 0x" & to_hstring32_f(hw_version_c) & "), " & "github.com/stnolting/neorv32" severity note; -- show main SoC configuration -- @@ -556,8 +549,6 @@ begin rstn_i => rstn_sys, sleep_o => cpu_sleep, debug_o => cpu_debug, - ifence_o => i_fence, - dfence_o => d_fence, -- interrupts -- msi_i => msw_irq_i, mei_i => mext_irq_i, @@ -572,10 +563,6 @@ begin dbus_rsp_i => cpu_d_rsp ); - -- advanced memory control -- - fence_o <= d_fence; - fencei_o <= i_fence; - -- fast interrupt requests (FIRQs) -- cpu_firq(00) <= firq.wdt; -- highest priority cpu_firq(01) <= firq.cfs; @@ -609,7 +596,6 @@ begin port map ( clk_i => clk_cpu, rstn_i => rstn_sys, - clear_i => i_fence, cpu_req_i => cpu_i_req, cpu_rsp_o => cpu_i_rsp, bus_req_o => icache_req, @@ -637,7 +623,6 @@ begin port map ( clk_i => clk_cpu, rstn_i => rstn_sys, - clear_i => d_fence, cpu_req_i => cpu_d_req, cpu_rsp_o => cpu_d_rsp, bus_req_o => dcache_req, diff --git a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd index f902939ea..606a9c2ce 100644 --- a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd +++ b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd @@ -151,10 +151,6 @@ entity neorv32_top_avalonmm is writedata_o : out std_logic_vector(31 downto 0); readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o : out std_ulogic; -- indicates an executed FENCE operation - fencei_o : out std_ulogic; -- indicates an executed FENCEI operation - -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_ulogic; -- chip-select, low-active xip_clk_o : out std_ulogic; -- serial clock @@ -350,10 +346,6 @@ begin wb_ack_i => wb_ack_i, wb_err_i => wb_err_i, - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => fence_o, - fencei_o => fencei_o, - -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => xip_csn_o, xip_clk_o => xip_clk_o, diff --git a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd index b00877f4d..3194dd5d3 100644 --- a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd +++ b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd @@ -458,9 +458,6 @@ begin slink_tx_dat_o => s0_axis_tdata_int, -- TX output data slink_tx_val_o => s0_axis_tvalid_int, -- TX valid output slink_tx_rdy_i => s0_axis_tready_int, -- TX ready to send - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => open, -- indicates an executed FENCE operation - fencei_o => open, -- indicates an executed FENCEI operation -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => xip_csn_o_int, -- chip-select, low-active xip_clk_o => xip_clk_o_int, -- serial clock diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd index 9508a50b6..08bc2ef9f 100644 --- a/sim/neorv32_tb.vhd +++ b/sim/neorv32_tb.vhd @@ -336,9 +336,6 @@ begin slink_tx_dat_o => slink_dat, -- TX output data slink_tx_val_o => slink_val, -- TX valid output slink_tx_rdy_i => slink_rdy, -- TX ready to send - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => open, -- indicates an executed FENCE operation - fencei_o => open, -- indicates an executed FENCEI operation -- XIP (execute in place via SPI) signals (available if XIP_EN = true) -- xip_csn_o => open, -- chip-select, low-active xip_clk_o => open, -- serial clock diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd index 1eb91ad1f..7d5a92b31 100644 --- a/sim/simple/neorv32_tb.simple.vhd +++ b/sim/simple/neorv32_tb.simple.vhd @@ -284,9 +284,6 @@ begin slink_tx_dat_o => slink_dat, -- TX output data slink_tx_val_o => slink_val, -- TX valid output slink_tx_rdy_i => slink_rdy, -- TX ready to send - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => open, -- indicates an executed FENCE operation - fencei_o => open, -- indicates an executed FENCEI operation -- XIP (execute in place via SPI) signals (available if XIP_EN = true) -- xip_csn_o => open, -- chip-select, low-active xip_clk_o => open, -- serial clock