diff --git a/rtl/core/neorv32_cpu_cp_muldiv.vhd b/rtl/core/neorv32_cpu_cp_muldiv.vhd index 313dc0e30..994415943 100644 --- a/rtl/core/neorv32_cpu_cp_muldiv.vhd +++ b/rtl/core/neorv32_cpu_cp_muldiv.vhd @@ -110,7 +110,7 @@ begin elsif rising_edge(clk_i) then -- defaults -- ctrl.out_en <= '0'; - ctrl.cnt <= std_ulogic_vector(to_unsigned(XLEN-2, index_size_f(XLEN))); -- cycle counter initialization + ctrl.cnt <= std_ulogic_vector(to_unsigned(XLEN-2, ctrl.cnt'length)); -- cycle counter initialization -- fsm -- case ctrl.state is diff --git a/rtl/core/neorv32_fifo.vhd b/rtl/core/neorv32_fifo.vhd index 20a16f69d..8578f2e47 100644 --- a/rtl/core/neorv32_fifo.vhd +++ b/rtl/core/neorv32_fifo.vhd @@ -17,8 +17,8 @@ use neorv32.neorv32_package.all; entity neorv32_fifo is generic ( - FIFO_DEPTH : natural := 4; -- number of fifo entries; has to be a power of two; min 1 - FIFO_WIDTH : natural := 32; -- size of data elements in fifo + FIFO_DEPTH : natural := 4; -- number of FIFO entries; has to be a power of two; min 1 + FIFO_WIDTH : natural := 32; -- size of data elements in FIFO FIFO_RSYNC : boolean := false; -- false = async read; true = sync read FIFO_SAFE : boolean := false; -- true = allow read/write only if data available FULL_RESET : boolean := false -- true = reset all memory cells (cannot be mapped to BRAM) @@ -50,7 +50,7 @@ architecture neorv32_fifo_rtl of neorv32_fifo is signal fifo_mem : fifo_mem_t; -- for fifo_depth_c > 1 signal fifo_reg : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- for fifo_depth_c = 1 - -- Fifo control and status -- + -- FIFO control and status -- signal we, re, match, empty, full, half, free, avail : std_ulogic; -- write/read pointer -- diff --git a/rtl/core/neorv32_twi.vhd b/rtl/core/neorv32_twi.vhd index 8aa4f0c6a..c9bf29046 100644 --- a/rtl/core/neorv32_twi.vhd +++ b/rtl/core/neorv32_twi.vhd @@ -1,5 +1,5 @@ -- ================================================================================ -- --- NEORV32 SoC - Two-Wire Interface Controller (TWI) -- +-- NEORV32 SoC - Two-Wire Interface Host Controller (TWI) -- -- -------------------------------------------------------------------------------- -- -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 -- -- Copyright (c) NEORV32 contributors. -- @@ -38,14 +38,14 @@ architecture neorv32_twi_rtl of neorv32_twi is -- control register -- constant ctrl_en_c : natural := 0; -- r/w: module enable (reset when zero) - constant ctrl_prsc0_c : natural := 1; -- r/w: CLK prsc bit 0 - constant ctrl_prsc2_c : natural := 3; -- r/w: CLK prsc bit 2 + constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler bit 0 + constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler bit 2 constant ctrl_cdiv0_c : natural := 4; -- r/w: clock divider bit 0 constant ctrl_cdiv3_c : natural := 7; -- r/w: clock divider bit 3 constant ctrl_clkstr_en_c : natural := 8; -- r/w: enable clock stretching -- - constant ctrl_fifo_size0_c : natural := 15; -- r/-: log2(fifo size), bit 0 (lsb) - constant ctrl_fifo_size3_c : natural := 18; -- r/-: log2(fifo size), bit 3 (msb) + constant ctrl_fifo_size0_c : natural := 15; -- r/-: log2(FIFO size), bit 0 (LSB) + constant ctrl_fifo_size3_c : natural := 18; -- r/-: log2(FIFO size), bit 3 (MSB) -- constant ctrl_sense_scl_c : natural := 27; -- r/-: current state of the SCL bus line constant ctrl_sense_sda_c : natural := 28; -- r/-: current state of the SDA bus line diff --git a/rtl/core/neorv32_xbus.vhd b/rtl/core/neorv32_xbus.vhd index e2421e515..526ea96ac 100644 --- a/rtl/core/neorv32_xbus.vhd +++ b/rtl/core/neorv32_xbus.vhd @@ -99,7 +99,7 @@ begin bus_rw <= '0'; elsif rising_edge(clk_i) then if (pending = '0') then -- idle, waiting for request - timeout_cnt <= std_ulogic_vector(to_unsigned(TIMEOUT_VAL, index_size_f(TIMEOUT_VAL)+1)); + timeout_cnt <= std_ulogic_vector(to_unsigned(TIMEOUT_VAL, timeout_cnt'length)); pending <= bus_req.stb; else -- busy, transfer in progress timeout_cnt <= std_ulogic_vector(unsigned(timeout_cnt) - 1);