From cff3c3c4b34ec51345b3db41f4d036c734feac2f Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Wed, 18 Oct 2023 21:46:09 +0200
Subject: [PATCH] [openocd] cleanup

* update neorv32-specific CSRs
* remove redundant (maybe deprecated???) memory access type configuration
---
 sw/openocd/openocd_neorv32.cfg | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/sw/openocd/openocd_neorv32.cfg b/sw/openocd/openocd_neorv32.cfg
index 6e5e0de8b..4c2029027 100644
--- a/sw/openocd/openocd_neorv32.cfg
+++ b/sw/openocd/openocd_neorv32.cfg
@@ -1,8 +1,8 @@
-# NEORV32 openOCD configuration file
+# NEORV32 on-chip debugger openOCD configuration file
 
 # ----------------------------------------------
 # Physical interface configuration
-# -> Adjust this for your adapter
+# -> ADJUST THIS FOR YOUR ADAPTER / SETUP
 # ----------------------------------------------
 
 # Default: FT2232H breakout board
@@ -29,17 +29,15 @@ jtag newtap $_CHIPNAME cpu -irlen 5
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
 
-# access memory only via program buffer
-riscv set_mem_access progbuf
-
 # expose NEORV32-specific CSRs
-riscv expose_csrs 2048=cfusel
-riscv expose_csrs 2049=cfureg
+riscv expose_csrs 2048=cfureg0
+riscv expose_csrs 2049=cfureg1
+riscv expose_csrs 2050=cfureg2
+riscv expose_csrs 2051=cfureg3
 riscv expose_csrs 4032=mxisa
 
-# enable access error reports
+# enable memory access error reports
 gdb_report_data_abort enable
-#gdb_report_register_access_error enable
 
 # ----------------------------------------------
 # Start session