TWI: Usage of "to_bit()" to filter 'H'

[andkae]

neorv32/rtl/core/neorv32_twi.vhd

Line 286 in 0e194c0

twi_sda_in <= std_ulogic(twi_sda_io);

In a TB can the I2C Pull-up emulated by the asignment of 'H'. To convert this weak high ('H') to a strong High ('1') ccould be used the following statement:

twi_sda_in <= to_stdulogic(to_bit(twi_sda_io));
twi_scl_in <= to_stdulogic(to_bit(twi_scl_io));

This avoid the read-in 'H' levels into the processors deeper logic. What do you think

Cheers,
Andreas

[stnolting]

Nice fix! 👍

But I am not sure if this is really necessary. H should be evaluated the same way as 1 in the relevant VHDL code pieces (-> see #332 (comment)). And it is a nice feature of VHDL to have "pulled-high" state here giving us additional (precious) information in simulation.

However, I am no expert here. @umarcor what do you think about this? 😉

[stnolting]

For simulation-only it would be nice to convert the TWI signals into a binary value (0 or 1). At least for the TWI clock line this is helpful, as we need to check this for "clock stretching".

Currently, clock stretching is detected by this logic (all signals are of type std_ulogic/std_ulogic_vector):

clk_gen.halt <= '1' when (io_con.scl_out = '1') and ((io_con.scl_in_ff(1) = '0') else '0';

However, io_con.scl_in_ff(1) could also be 'L', which is functionally OK but will cause a simulation mismatch as ((io_con.scl_in_ff(1) = '0') will evaluate to false, right?

I am not sure what exactly happens when we are using (to_bit(io_con.scl_in_ff(1) = '0'). For this very special case it might be handy to have a conversion function that at least converts

• '0' or 'L' -> '0'
• '1' or 'H' -> '1'

Is this what to_bit does?!

@umarcor maybe you can help out 😉

[andkae]

Hi Stephan,

Is this what to_bit does?!

Yes

    FUNCTION To_bit       ( s : std_ulogic        
    --synopsys synthesis_off
			    ; xmap : BIT := '0'
    --synopsys synthesis_on
			  ) RETURN BIT IS
    -- pragma built_in SYN_FEED_THRU
    -- pragma subpgm_id 205
    BEGIN
    --synopsys synthesis_off
            CASE s IS
                WHEN '0' | 'L' => RETURN ('0');
                WHEN '1' | 'H' => RETURN ('1');
                WHEN OTHERS => RETURN xmap;
            END CASE;
    --synopsys synthesis_on
    END;

https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_1164.vhd

[stnolting]

Oh, I should have found that out, too... 😅
Anyway, thanks for the info! I'll add those conversion functions (the way you have proposed) to #340.

[andkae]

No worry, sometimes you overlook something :)