Advanced debugging with GDB + SVD file (without an IDE!)

[stnolting]

GitHub user @bnahill provides an awesome project (https://github.com/bnahill/PyCortexMDebug) that allows to import SVD files right into GDB. This way you can conveniently inspect peripherals directly in GDB - no IDE required!

Although PyCortexMDebug is intended for ARM cores it also works with the NEORV32's SVD file as it follows ARM's CMSIS standard. 🎉

---

Start GDB (directly calling the binary) or invoke it from one of the example projects using the makefile's gdb target.

$ riscv32-unknown-elf-gdb

neorv32/sw/example/hello_world$ make gdb

After GDB has started source the gdb.py script from PyCortexMDebug-master/scripts. This might take some seconds.

(gdb) source path/to/PyCortexMDebug-master/scripts/gdb.py

Now import the core's SVD file. Use the absolute file path here.

(gdb) svd absolute/path/to/neorv32/sw/svd/neorv32.svd
Loading SVD file absolute/path/to/neorv32/sw/svd/neorv32.svd...

Show a list of all provided peripheral. Note that this list does not show the actually implemented modules - it just shows all the information from the SVD file.

(gdb) svd
Available Peripherals:
        CFS:      Custom functions subsystem
        SDI:      Serial data interface controller
        SLINK:    Stream Link Interface
        DMA:      Direct memory access controller
        CRC:      Cyclic redundancy check unit
        PWM:      Pulse-width modulation controller
        XIP:      Execute In Place Module
        GPTMR:    General purpose timer
        ONEWIRE:  1-Wire Interface Controller
        XIRQ:     External interrupts controller
        MTIME:    Machine timer
        UART0:    Primary universal asynchronous receiver and transmitter
        UART1:    Secondary universal asynchronous receiver and transmitter
        SPI:      Serial peripheral interface controller
        TWI:      Two-wire interface controller
        TRNG:     True random number generator
        WDT:      Watchdog timer
        GPIO:     General purpose input/output port
        NEOLED:   Smart LED hardware interface
        SYSINFO:  System configuration information memory

Inspect the SYSINFO module - show registers values in hexadecimal presentation:

(gdb) svd/x SYSINFO
Registers in SYSINFO:
        CLK:               0x05F5E100  Clock speed in Hz
        SYSINFO_reserved:  0x00000000  reserved
        SOC:               0xFFBFF06F  SoC configuration
        CACHE:             0x00261126  Cache configuration
        ISPACE_BASE:       0x00000000  Instruction memory address space base address
        DSPACE_BASE:       0x80000000  Data memory address space base address
        IMEM_SIZE:         0x00008000  Internal instruction memory (IMEM) size in bytes
        DMEM_SIZE:         0x00002000  Internal data memory (DMEM) size in bytes

Check NEORV32_SYSINFO->SOC to see the actual processor/SoC configuration.

(gdb) svd SYSINFO SOC
Fields in SYSINFO > SOC:
        SYSINFO_SOC_BOOTLOADER:      1  Bootloader implemented
        SYSINFO_SOC_MEM_EXT:         1  External bus interface implemented
        SYSINFO_SOC_MEM_INT_IMEM:    1  Processor-internal instruction memory implemented
        SYSINFO_SOC_MEM_INT_DMEM:    1  Processor-internal data memory implemented
        SYSINFO_SOC_MEM_EXT_ENDIAN:  0  External bus interface uses BIG-endian byte-order
        SYSINFO_SOC_ICACHE:          1  Processor-internal instruction cache implemented
        SYSINFO_SOC_DCACHE:          1  Processor-internal data cache implemented
        SYSINFO_SOC_IO_CRC:          1  Cyclic redundancy check unit implemented
        SYSINFO_SOC_IO_SLINK:        1  Stream link interface implemented
        SYSINFO_SOC_IO_DMA:          1  Direct memory access controller implemented
        SYSINFO_SOC_IO_GPIO:         1  General purpose input/output port unit implemented
        SYSINFO_SOC_IO_MTIME:        1  Machine system timer implemented
        SYSINFO_SOC_IO_UART0:        1  Primary universal asynchronous receiver/transmitter 0 implemented
        SYSINFO_SOC_IO_SPI:          1  Serial peripheral interface implemented
        SYSINFO_SOC_IO_TWI:          1  Two-wire interface implemented
        SYSINFO_SOC_IO_PWM:          1  Pulse-width modulation unit implemented
        SYSINFO_SOC_IO_WDT:          1  Watchdog timer implemented
        SYSINFO_SOC_IO_CFS:          0  Custom functions subsystem implemented
        SYSINFO_SOC_IO_TRNG:         1  True random number generator implemented
        SYSINFO_SOC_IO_SDI:          1  Serial data interface implemented
        SYSINFO_SOC_IO_UART1:        1  Secondary universal asynchronous receiver/transmitter 1 implemented
        SYSINFO_SOC_IO_NEOLED:       1  NeoPixel-compatible smart LED interface implemented
        SYSINFO_SOC_IO_XIRQ:         1  External interrupt controller implemented
        SYSINFO_SOC_IO_GPTMR:        1  General purpose timer implemented
        SYSINFO_SOC_IO_XIP:          1  Execute in place module implemented
        SYSINFO_SOC_IO_ONEWIRE:      1  1-wire interface controller implemented
        SYSINFO_SOC_OCD:             1  On-chip debugger implemented