Only external memory

[fpardoseco]

Hi,

I am trying to simulate a RiscV neorv32 using only external memory and I have a some concerns:

• I assume that I have to have a top design where I instantiate the riscV and the wishbone (slave) that allows the communciation with the memories conected to such slave wishbone.
• I also assume that I need to connect the wishbone signal from riscv-v with the corresponding signals from the wishbone ram interface (slave). Is this correct?
• I am a little lost about the memory space, should I define the base addresses and memory size for both data and isntructions memory or the riscv automatically assigns the 0xE0000000 and 0x80000000 bases addreses for data and instructions memory?

Thanks in advance for your help.

[stnolting]

Hey @fpardoseco!

I assume that I have to have a top design where I instantiate the riscV and the wishbone (slave) that allows the communciation with the memories conected to such slave wishbone.

That's right. Basically, you just need the processor itself and (if you want to use the default memory layout) two Wishbone memories - one for data and one for instructions.

I also assume that I need to connect the wishbone signal from riscv-v with the corresponding signals from the wishbone ram interface (slave). Is this correct?

That's also correct. Depending on your Wishbone memories you might also need an "interconnect" or switch between the core and the two memories.

I am a little lost about the memory space, should I define the base addresses and memory size for both data and isntructions memory or the riscv automatically assigns the 0xE0000000 and 0x80000000 bases addreses for data and instructions memory?

Let's stick with the default memory layout here. If you disable the processor-internal IMEM and DMEM all the according accesses are redirected to the external bus interface. Hence, you'll need to map your external memories accordingly:

• base address 0x00000000: start address of your external instruction memory
• base address 0x80000000: start address of your external data memory

This address mapping has to be done by your external Wishbone system.

If you like, you can use this simple Wishbone memory for building your system (remove the .txt suffix):
wb_mem.vhd.txt

The nice thing about this memory is that is does the address checking internally. Hence, you do not need an extra address decoder / bus switch / interconnect. Just connect all XBUS output signals to all Wishbone devices and OR the read-back signals before they go back to the processor:

xbus_adr_o --o--> wb_addr_i (data memory)
             |
             +--> wb_addr_i (instruction memory)

xbus_dat_o --o--> wb_data_i (data memory)
             |
             +--> wb_data_i (instruction memory)

xbus_we_o  --o--> wb_we_i (data memory)
             |
             +--> wb_we_i (instruction memory)

xbus_sel_o --o--> wb_sel_i (data memory)
             |
             +--> wb_sel_i (instruction memory)

xbus_stb_o --o--> wb_stb_i (data memory)
             |
             +--> wb_stb_i (instruction memory)

xbus_cyc_o --o--> wb_cyc_i (data memory)
             |
             +--> wb_cyc_i (instruction memory)


              +----+
              |    |<--- wb_data_o (data memory)
xbus_dat_i <--| OR | 
              |    |<--- wb_data_o (instruction memory)
              +----+

              +----+
              |    |<--- wb_ack_o (data memory)
xbus_ack_i <--| OR | 
              |    |<--- wb_ack_o (instruction memory)
              +----+

              +----+
              |    |<--- wb_err_o (data memory)
xbus_err_i <--| OR | 
              |    |<--- wb_err_o (instruction memory)
              +----+

[fpardoseco]

@stnolting thanks for your answer !