Vivado Integration for simulation

[Akralan]

Hello,

as part of a training course, I would like to use the NEORV32.
I'm trying to follow the steps in the user guide (2. General Hardware Setup) in order to integrate it into Vivado (2023.2) but I'm running into problems.

I'm new to Vivado, so I'm looking for help.
I have the impression that my error is potentially simple, but I can't get rid of it.

When I add the files rtl/core and rtl/core/mem (*.default), vivado warns me that some files are missing and I get quite a few errors in the files.
Can anyone help me?

Thanks in advance

[stnolting]

This looks like a library problem. You need to set the VHDL library to "neorv32" for every single (core) file.

Btw, if you are planning to use a block design you can also import the processor as IP block: https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block

[Akralan]

Hello,

thank you for your quick reply.
Yeah I asked the question a little bit to early and by using your arty a7 tcl setup it worked perfectly.

I have an other problem now with trying to use the bootloader
my host computer is receiving the strings from the uart but i can't get to send a char when I'm trying to abort the autoboot sequence.
I've verified the pin assignment and my wires so I don't really know what to try

Also, as you can see, after the IMEM and DMEM lines I don't have the bytes @0x00000000 and I don't know if this is normal.

Thanks in advance for your help

[stnolting]

Yeah I asked the question a little bit to early and by using your arty a7 tcl setup it worked perfectly.

👍

my host computer is receiving the strings from the uart but i can't get to send a char when I'm trying to abort the autoboot sequence.

Those empty lines look strange. Please check your terminal settings - especially the newline settings:

I've verified the pin assignment and my wires so I don't really know what to try

Can you try "shortening" your UART adapter's RX and TX lines? Just to check that data is send as expected. By the way, are you using a Linux or Windows machine?

Also, as you can see, after the IMEM and DMEM lines I don't have the bytes @0x00000000 and I don't know if this is normal.

That's fine. The address information has been trimmed (see https://stnolting.github.io/neorv32/#_bootloader_console). But I think I need to update the according user guide section. 😅

[Akralan]

I tried shortening the RX and TX of the USB-UART bridge and it was a good idea because I'm receving nothing on Tera Term so I think the problem might come from the bridge.

I will retry to send a program via the bootloader with a new bridge and tell you if it's working.
Also I'm using Windows

Thank you

Do you think it would be easy to migrate the NEORV32 to Versal ?

[stnolting]

I tried shortening the RX and TX of the USB-UART bridge and it was a good idea because I'm receving nothing on Tera Term so I think the problem might come from the bridge.

I know that problem - happens to me all the time when using those FTDI breakout boards 😉

Do you think it would be easy to migrate the NEORV32 to Versal ?

The FPGA part of the Versal devices is still "just" an FPGA. So it should be no problem to implement a NEORV32 core (or maybe several hundreds?! 😅) on that.