diff --git a/.github/workflows/Linty.yml b/.github/workflows/Linty.yml new file mode 100644 index 000000000..44e098b98 --- /dev/null +++ b/.github/workflows/Linty.yml @@ -0,0 +1,67 @@ +name: Linty +on: + push: + paths: + - 'rtl/**' + - 'sim/**' + - '.github/workflows/Linty.yml' + workflow_dispatch: + +jobs: + linty: + # if: github.event_name != 'pull_request' && github.ref == 'refs/heads/main' + name: Linty + timeout-minutes: 10 + runs-on: ubuntu-latest + + steps: + - name: Git Checkout + uses: actions/checkout@v4 + with: + fetch-depth: 0 + + - name: Create sonar-project.properties + run: | + echo "sonar.projectKey=neorv32" > $GITHUB_WORKSPACE/sonar-project.properties + echo "sonar.sources=./rtl/core" >> $GITHUB_WORKSPACE/sonar-project.properties + + - name: Create linty_read.ys + run: | + cp $GITHUB_WORKSPACE/rtl/file_list_soc.f $GITHUB_WORKSPACE/.github/linty_read.ys + sed -i 's/NEORV32_RTL_PATH_PLACEHOLDER/verific -work neorv32 -vhdl .\/..\/rtl/g' $GITHUB_WORKSPACE/.github/linty_read.ys + echo "verific -L neorv32 -vhdl ./../rtl/core/neorv32_top.vhd" >> $GITHUB_WORKSPACE/.github/linty_read.ys + + - name: Create linty_hierarchy.ys + run: | + echo "hierarchy -top neorv32_top" > $GITHUB_WORKSPACE/.github/linty_hierarchy.ys + + - name: Cache + uses: actions/cache@v3.3.0 + with: + path: ~/.sonar/cache + key: sonar + restore-keys: sonar + + - name: Run Linty + run: | + docker run \ + -e SONAR_HOST_URL=https://oss.linty-services.com \ + -e SONAR_TOKEN="${{ secrets.LINTY_TOKEN }}" \ + -e GITHUB_TOKEN="${{ secrets.GITHUB_TOKEN }}" \ + -e GITHUB_REPOSITORY_OWNER="$GITHUB_REPOSITORY_OWNER" \ + -e GITHUB_REPOSITORY="$GITHUB_REPOSITORY" \ + -e TABBY_CAD_LICENSE="$TABBY_CAD_LICENSE" \ + -v "$PWD:/usr/src" \ + lintyservices/linty-scanner:latest + env: + TABBY_CAD_LICENSE: ${{ secrets.TABBY_CAD_LICENSE }} + + - name: Debug + if: always() + uses: actions/upload-artifact@v3 + with: + name: debug + path: | + ./bugfinder_workdir/ + ./.linty/ + include-hidden-files: true diff --git a/README.md b/README.md index cb4becd07..6aee10c3b 100644 --- a/README.md +++ b/README.md @@ -70,15 +70,16 @@ not working as expected. See how to [contribute](https://github.com/stnolting/ne | Task / Subproject | Repository | CI Status | |:------------------|:-----------|:----------| -| GitHub pages (docs) | [neorv32](https://github.com/stnolting/neorv32) | [![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32) | -| Build documentation | [neorv32](https://github.com/stnolting/neorv32) | [![Documentation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) | -| Processor verification | [neorv32](https://github.com/stnolting/neorv32) | [![Processor](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&longCache=true&style=flat-square&label=Processor%20Check&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) | -| VUnit testbench | [neorv32-vunit](https://github.com/stnolting/neorv32-vunit) | [![neorv32-vunit](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-vunit/vunit.yml?branch=main&longCache=true&style=flat-square&label=neorv32-vunit&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-vunit/actions/workflows/vunit.yml) | -| RISCOF core verification | [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) | [![neorv32-riscof](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-riscof&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml) | -| FPGA implementations | [neorv32-setups](https://github.com/stnolting/neorv32-setups) | [![Implementation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main&longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation) | -| All-Verilog version | [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) | [![neorv32-verilog](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-verilog&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml) | -| FreeRTOS port | [neorv32-freertos](https://github.com/stnolting/neorv32-freertos) | [![neorv32-freertos](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-freertos/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-freertos%20sim&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml) | -| Prebuilt GCC toolchains | [riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt) | [![Prebuilt_Toolchains](https://img.shields.io/github/actions/workflow/status/stnolting/riscv-gcc-prebuilt/main.yml?branch=main&longCache=true&style=flat-square&label=Prebuilt%20Toolchains&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/riscv-gcc-prebuilt/actions/workflows/main.yml) | +| Code quality ([Linty](https://linty-services.com)) | [neorv32](https://github.com/stnolting/neorv32) | [![Quality Gate Status](https://oss.linty-services.com/api/project_badges/measure?project=neorv32&metric=alert_status&token=sqb_97b392f36051f7887215e61c53d6f0f858ca2697)](https://oss.linty-services.com/dashboard?id=neorv32) | +| GitHub pages (docs) | [neorv32](https://github.com/stnolting/neorv32) | [![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32) | +| Build documentation | [neorv32](https://github.com/stnolting/neorv32) | [![Documentation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) | +| Processor verification | [neorv32](https://github.com/stnolting/neorv32) | [![Processor](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&longCache=true&style=flat-square&label=Processor%20Check&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) | +| VUnit testbench | [neorv32-vunit](https://github.com/stnolting/neorv32-vunit) | [![neorv32-vunit](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-vunit/vunit.yml?branch=main&longCache=true&style=flat-square&label=neorv32-vunit&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-vunit/actions/workflows/vunit.yml) | +| RISCOF core verification | [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) | [![neorv32-riscof](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-riscof&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml) | +| FPGA implementations | [neorv32-setups](https://github.com/stnolting/neorv32-setups) | [![Implementation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main&longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation) | +| All-Verilog version | [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) | [![neorv32-verilog](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-verilog&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml) | +| FreeRTOS port | [neorv32-freertos](https://github.com/stnolting/neorv32-freertos) | [![neorv32-freertos](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-freertos/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-freertos%20sim&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml) | +| Prebuilt GCC toolchains | [riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt) | [![Prebuilt_Toolchains](https://img.shields.io/github/actions/workflow/status/stnolting/riscv-gcc-prebuilt/main.yml?branch=main&longCache=true&style=flat-square&label=Prebuilt%20Toolchains&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/riscv-gcc-prebuilt/actions/workflows/main.yml) | The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program