Quartus 20.1 failing to flash Patmos onto DE2-115 #95
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I built now patmos using Quartus 19.1 and 20.1 and attached the log here. Would be interesting why quartus uses logic cells instead of RAM cells Synthesis log output of v19.1: Synthesis log output of v20.1: |
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I posted a question on Reddit, according to this the reason for the high usage of logic cells instead of using RAM Blocks is that there is asynchronous access to the RAM Block. Quartus 19.1 infered pass through logic where v20.1 uninferes RAM Blocks and uses logic cells. It looks like there is an issue with the generated verilog code from chisel. Synthesis log output of v19.1: Synthesis log output of v20.1: |
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Please provide the link to the Reddit question. Seems like we are dependent on an implementation detail (how Quatus infers stuff). Can we change the code to always use RAM regardless of Quatus version? |
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That is the link to the answer. The generated code looks like the example to me. I skimmed through the settings of quartus but nothing really catched my eye. Edit: |
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Mmh, this is very bad. I guess/hope we can fix this when changing some of the Chisel code. We used a dedicated register and an asynchronous RAM, where Quartus 19 could infer a block RAM, which has a register input. Chisel has also a SyncRam, where the register is implicit. Maybe that would then work in Quartus 20. |
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I think we should do the forwarding manual ourself. |
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Added forwarding to all memories, which almost solves this issue. All memories are now mapped to on-chip memories except the data cache. Don't know what the difference is, as all caches use the same MemBlock module. |
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The issue with the data cache is the tag memory that has logic in the output (the comparators). Q17 did OK infer the memories, but newer Quartus does implement the tag memories in registers. I assume there should be an option in Quartus to force using on-chip memories. |
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Discussed in #94
Originally posted by LehrChristoph September 14, 2021
Hi all,
I started to develop a container image which provides all dependencies and has the compiler etc set up. With the setup script more or less everything worked fine, but when I try synthesizing patmos the Quartus fitter takes around 17 minutes on my AMD Ryzen 7 5800X, in comparison to Quartus 19.1 it only takes 7-8 seconds.
Additionally when flashing the hello puts example onto my DE2-115 Board the process exits with an error, using 19.1 the program exits normal.
That behaviour is quite strange for me, and I'm a little lost looking for the error although Quartus 20.1 should still support the Cyclone IV FPGA line.
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