This is an almost literal translation of Keccak's reference VHDL implementation mid-range core to the Bluespec SystemVerilog (BSV) language. Our goals are:
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Easier integration with Bluespec and/or Verilog projects, specially when simulating with iverilog, whose support for mixed VHDL/Verilog simulation is still at early stages.
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Be easier to understand and customize. As Bluespec is more flexible for static elaboration than VHDL, our code is more compact although it implements the same architecture.
Typing make will test the implementation against the test vectors (using Bluesim) and
subsequently build the mkKeccak.v hardware core.
To prove that our implementation is equivalent to the reference implementation, we synthesized both implementations (for NumSlices=32) several times targeting an Altera Cyclone V device (5CSEMA5F31C6), varying the Quartus II fitter seed each time. The figure below presents histograms for the clock frequency and logic utilization obtained by each implementation.
The reference implementation (VHDL) tends to achieve a slightly higher clock frequency, whereas our implementation (BSV) occupies somewhat less area. Overall, both implementations produce similar results, as expected.