-
Notifications
You must be signed in to change notification settings - Fork 0
/
Processor.bsv
338 lines (316 loc) · 15.8 KB
/
Processor.bsv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
import ClientServer::*;
import GetPut::*;
import Connectable::*;
import FIFO::*;
import FIFOF::*;
import SpecialFIFOs::*;
import RegFile::*;
import FShow::*;
import AvalonCommon::*;
import AvalonMaster::*;
import Cache::*;
import Instructions::*;
import Trace::*;
import RFile::*;
import Divider::*;
typedef union tagged {
struct { Ridx r; Bit#(32) data; } WbREG;
struct { Ridx r; Bit#(24) addr; Bit#(2) line; } WbLB;
struct { Ridx r; Bit#(24) addr; Bit#(2) line; } WbLBU;
struct { Ridx r; Bit#(24) addr; Bit#(1) line; } WbLH;
struct { Ridx r; Bit#(24) addr; Bit#(1) line; } WbLHU;
struct { Ridx r; Bit#(24) addr; } WbLW;
struct { Bit#( 8) data; Bit#(24) addr; Bit#(2) line; } WbSB;
struct { Bit#(16) data; Bit#(24) addr; Bit#(1) line; } WbSH;
struct { Bit#(32) data; Bit#(24) addr; } WbSW;
} WBOp deriving (Eq, Bits);
instance FShow#(WBOp);
function Fmt fshow(WBOp op);
case (op) matches
tagged WbREG .s: return $format("WbREG{r:%0d,data:%h}", s.r, s.data);
tagged WbLB .s: return $format("WbLB {r:%0d,addr:%h,line:%h}", s.r, s.addr, s.line);
tagged WbLBU .s: return $format("WbLBU{r:%0d,addr:%h,line:%h}", s.r, s.addr, s.line);
tagged WbLH .s: return $format("WbLH {r:%0d,addr:%h,line:%h}", s.r, s.addr, s.line);
tagged WbLHU .s: return $format("WbLHU{r:%0d,addr:%h,line:%h}", s.r, s.addr, s.line);
tagged WbLW .s: return $format("WbLW {r:%0d,addr:%h}", s.r, s.addr);
tagged WbSB .s: return $format("WbSB {data:%h,addr:%h,line:%h}", s.data, s.addr, s.line);
tagged WbSH .s: return $format("WbSH {data:%h,addr:%h,line:%h}", s.data, s.addr, s.line);
tagged WbSW .s: return $format("WbSW {data:%h,addr:%h}", s.data, s.addr);
endcase
endfunction
endinstance
module mkProcessor#(module#(AvalonMaster#(24,32)) mkMaster,
function Bool ignoreCache(Bit#(24) addr),
Bit#(24) resetAddr, Bit#(24) irqAddr)
(AvalonMasterWires#(24,32));
AvalonMaster#(24,32) masterAdapter <- mkMaster;
Cache#(24,12,12) cache <- mkCache(ignoreCache);
Reg #(Bit#(24)) fetchPC <- mkReg(resetAddr);
FIFOF#(Bit#(24)) jumpTo <- mkBypassFIFOF;
FIFOF#(Bit#(24)) execPC <- mkPipelineFIFOF;
FIFOF#(Bit#(32)) instFIFO <- mkBypassFIFOF;
FIFOF#(Bit#(32)) dataFIFO <- mkBypassFIFOF;
FIFOF#(WBOp) pendingLoad <- mkPipelineFIFOF;
FIFOF#(WBOp) execToWB <- mkPipelineFIFOF;
RFile rf <- mkRFile;
Reg#(Bit#(32)) lo <- mkReg(0);
Reg#(Bit#(32)) hi <- mkReg(0);
Divider divider <- mkDivider;
Reg#(Bool) dividerPending <- mkReg(False);
Reg#(Bool) irqEnabled <- mkReg(False);
FIFOF#(Bit#(32)) irqFIFO <- mkUGFIFOF;
Reg#(Bit#(24)) irqReturnAddr <- mkRegU;
Reg#(Bool) clearCache <- mkReg(False);
mkConnection(cache.busClient.request, masterAdapter.busServer.request);
mkConnection(masterAdapter.busServer.response, cache.busClient.response);
mkConnection(cache.instCache.response, toPut(instFIFO));
mkConnection(cache.dataCache.response, toPut(dataFIFO));
rule getIrq(irqEnabled && irqFIFO.notFull);
let irq <- masterAdapter.irqGet.get;
irqFIFO.enq(irq);
endrule
rule clearTheCaches(clearCache);
clearCache <= False;
cache.clear;
endrule
rule dividerGetResult(dividerPending);
match {.r,.q} <- divider.response.get;
hi <= r;
lo <= q;
dividerPending <= False;
endrule
rule fetchAhead(!jumpTo.notEmpty && !clearCache);
let pc = fetchPC;
if(irqEnabled && irqFIFO.notEmpty)
begin
trace($format("[IRQ] irqReturnAddr=%h", fetchPC));
irqReturnAddr <= fetchPC;
irqEnabled <= False;
pc = irqAddr;
end
fetchPC <= pc + 1;
trace($format("[Fetch %h]", pc));
cache.instCache.request.put(AvalonRequest{command: Read, addr: pc, data: ?});
execPC.enq(pc);
endrule
rule fetchJump(jumpTo.notEmpty && !clearCache);
let pc = fetchPC;
let newpc = jumpTo.first;
if(irqEnabled && irqFIFO.notEmpty)
begin
trace($format("[IRQ] [@BDS] irqReturnAddr=%h", newpc));
irqReturnAddr <= newpc;
irqEnabled <= False;
newpc = irqAddr;
end
fetchPC <= newpc;
trace($format("[Fetch %h] [jump %h]", pc, newpc));
cache.instCache.request.put(AvalonRequest{command: Read, addr: pc, data: ?});
execPC.enq(pc);
jumpTo.deq;
endrule
rule exec(!pendingLoad.notEmpty && !dividerPending && !clearCache);
Instr inst = unpack(instFIFO.first);
let pc = execPC.first;
let pc1 = pc+1;
trace($format("[Exec %h] ", pc)+fshow(inst));
instFIFO.deq;
execPC.deq;
function Bit#(32) zextSh(Sham sh) = zeroExtend(sh);
case (inst) matches
tagged ADD .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)+rf.rd2(s.rt) });
tagged ADDI .s: execToWB.enq(WbREG{r:s.rt, data:rf.rd1(s.rs)+signExtend(s.im) });
tagged ADDIU .s: execToWB.enq(WbREG{r:s.rt, data:rf.rd1(s.rs)+signExtend(s.im) });
tagged ADDU .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)+rf.rd2(s.rt) });
tagged LUI .s: execToWB.enq(WbREG{r:s.rt, data:{s.im,16'b0} });
tagged SUB .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)-rf.rd2(s.rt) });
tagged SUBU .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)-rf.rd2(s.rt) });
tagged SLL .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rt)<<zextSh(s.sa) });
tagged SLLV .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rt)<<zextSh(rf.rd2(s.rs)[4:0]) });
tagged SRA .s: execToWB.enq(WbREG{r:s.rd, data:signedShiftRight(rf.rd1(s.rt),zextSh(s.sa)) });
tagged SRAV .s: execToWB.enq(WbREG{r:s.rd, data:signedShiftRight(rf.rd1(s.rt),zextSh(rf.rd2(s.rs)[4:0])) });
tagged SRL .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rt)>>zextSh(s.sa) });
tagged SRLV .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rt)>>zextSh(rf.rd2(s.rs)[4:0]) });
tagged AND .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)&rf.rd2(s.rt) });
tagged ANDI .s: execToWB.enq(WbREG{r:s.rt, data:rf.rd1(s.rs)&zeroExtend(s.im) });
tagged NOR .s: execToWB.enq(WbREG{r:s.rd, data:~(rf.rd1(s.rs)|rf.rd2(s.rt)) });
tagged OR .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)|rf.rd2(s.rt) });
tagged ORI .s: execToWB.enq(WbREG{r:s.rt, data:rf.rd1(s.rs)|zeroExtend(s.im) });
tagged XOR .s: execToWB.enq(WbREG{r:s.rd, data:rf.rd1(s.rs)^rf.rd2(s.rt) });
tagged XORI .s: execToWB.enq(WbREG{r:s.rt, data:rf.rd1(s.rs)^zeroExtend(s.im) });
tagged SLT .s: execToWB.enq(WbREG{r:s.rd, data:zeroExtend(pack(signedLT(rf.rd1(s.rs),rf.rd2(s.rt)))) });
tagged SLTI .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(signedLT(rf.rd1(s.rs),signExtend(s.im))))});
tagged SLTIU .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack( rf.rd1(s.rs)<signExtend(s.im)) )});
tagged SLTU .s: execToWB.enq(WbREG{r:s.rd, data:zeroExtend(pack( rf.rd1(s.rs)<rf.rd2(s.rt))) });
tagged DIV .s:
action
dividerPending <= True;
divider.request.put(tuple3(rf.rd1(s.rs),rf.rd2(s.rt),True));
endaction
tagged DIVU .s:
action
dividerPending <= True;
divider.request.put(tuple3(rf.rd1(s.rs),rf.rd2(s.rt),False));
endaction
tagged MULT .s:
action
Int#(64) r1 = unpack(signExtend(rf.rd1(s.rs)));
Int#(64) r2 = unpack(signExtend(rf.rd2(s.rt)));
Bit#(64) mult = pack(r1*r2);
hi <= mult[63:32];
lo <= mult[31: 0];
endaction
tagged MULTU .s:
action
UInt#(64) r1 = unpack(zeroExtend(rf.rd1(s.rs)));
UInt#(64) r2 = unpack(zeroExtend(rf.rd2(s.rt)));
Bit#(64) mult = pack(r1*r2);
hi <= mult[63:32];
lo <= mult[31: 0];
endaction
tagged MFHI .s: execToWB.enq(WbREG{r:s.rd, data:hi});
tagged MFLO .s: execToWB.enq(WbREG{r:s.rd, data:lo});
tagged BEQ .s: if(rf.rd1(s.rs)==rf.rd2(s.rt)) jumpTo.enq(pc1 + signExtend(s.of));
tagged BGEZ .s: if(signedGE(rf.rd1(s.rs),0)) jumpTo.enq(pc1 + signExtend(s.of));
tagged BGTZ .s: if(signedGT(rf.rd1(s.rs),0)) jumpTo.enq(pc1 + signExtend(s.of));
tagged BLEZ .s: if(signedLE(rf.rd1(s.rs),0)) jumpTo.enq(pc1 + signExtend(s.of));
tagged BLTZ .s: if(signedLT(rf.rd1(s.rs),0)) jumpTo.enq(pc1 + signExtend(s.of));
tagged BNE .s: if(rf.rd1(s.rs)!=rf.rd2(s.rt)) jumpTo.enq(pc1 + signExtend(s.of));
tagged J .s: jumpTo.enq(truncate(s.tg));
tagged JAL .s:
action
execToWB.enq(WbREG{r:31, data:zeroExtend(pc+2)<<2});
jumpTo.enq(truncate(s.tg));
endaction
tagged JALR .s:
action
execToWB.enq(WbREG{r:s.rd, data:zeroExtend(pc+2)<<2});
jumpTo.enq(truncate(rf.rd1(s.rs)>>2));
endaction
tagged JR .s: jumpTo.enq(truncate(rf.rd1(s.rs)>>2));
tagged LB .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbLB{r:s.rt, addr:truncate(addr>>2), line:addr[1:0]});
endaction
tagged LBU .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbLBU{r:s.rt, addr:truncate(addr>>2), line:addr[1:0]});
endaction
tagged LH .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbLH{r:s.rt, addr:truncate(addr>>2), line:addr[1]});
endaction
tagged LHU .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbLHU{r:s.rt, addr:truncate(addr>>2), line:addr[1]});
endaction
tagged LW .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbLW{r:s.rt, addr:truncate(addr>>2)});
endaction
tagged SB .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbSB{data:truncate(rf.rd2(s.rt)), addr:truncate(addr>>2), line:addr[1:0]});
endaction
tagged SH .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbSH{data:truncate(rf.rd2(s.rt)), addr:truncate(addr>>2), line:addr[1]});
endaction
tagged SW .s:
action
Bit#(32) addr = rf.rd1(s.rb)+signExtend(s.of);
execToWB.enq(WbSW{data:rf.rd2(s.rt), addr:truncate(addr>>2)});
endaction
tagged SYSC .s:
case (s.sc)
20'h0000: $finish();
20'h0001: $display("[Display] %h", rf.rd1(4));
20'h0002: clearCache <= True;
20'h0003: irqEnabled <= False;
20'h0004: irqEnabled <= True;
20'h0005: execToWB.enq(WbREG{r:4, data:(irqFIFO.notEmpty ? irqFIFO.first : 0)});
20'h0006: if(irqFIFO.notEmpty) begin jumpTo.enq(irqReturnAddr); irqFIFO.deq; irqEnabled <= True; end
endcase
tagged ILLEGAL : $display("Exec error: Invalid instruction %h at pc=%h", pack(inst), pc);
endcase
endrule
rule wbLoadResult(dataFIFO.notEmpty && !clearCache);
let wbOp = pendingLoad.first;
let data = dataFIFO.first;
trace($format("[wbLoadResult] [data=%h] ",data)+fshow(wbOp));
function Bit#(8) byteLine(Bit#(32) d, Bit#(2) line);
return (case(line)
2'h0: d[31:24];
2'h1: d[23:16];
2'h2: d[15: 8];
2'h3: d[ 7: 0];
endcase);
endfunction
function Bit#(16) halfLine(Bit#(32) d, Bit#(1) line);
return (case(line)
1'h0: d[31:16];
1'h1: d[15: 0];
endcase);
endfunction
function Bit#(32) byteSub(Bit#(32) d, Bit#(2) line, Bit#(8) newd);
case(line)
2'h0: d[31:24] = newd;
2'h1: d[23:16] = newd;
2'h2: d[15: 8] = newd;
2'h3: d[ 7: 0] = newd;
endcase
return d;
endfunction
function Bit#(32) halfSub(Bit#(32) d, Bit#(1) line, Bit#(16) newd);
case(line)
1'h0: d[31:16] = newd;
1'h1: d[15: 0] = newd;
endcase
return d;
endfunction
case (wbOp) matches
tagged WbREG .s: $display("WB error: wbREG shouldn't cause a pending load");
tagged WbLB .s: rf.wr(s.r, signExtend(byteLine(data, s.line)));
tagged WbLBU .s: rf.wr(s.r, zeroExtend(byteLine(data, s.line)));
tagged WbLH .s: rf.wr(s.r, signExtend(halfLine(data, s.line)));
tagged WbLHU .s: rf.wr(s.r, zeroExtend(halfLine(data, s.line)));
tagged WbLW .s: rf.wr(s.r, data);
tagged WbSB .s: cache.dataCache.request.put(AvalonRequest{command: Write, addr: truncate(s.addr),
data: byteSub(data, s.line, s.data)});
tagged WbSH .s: cache.dataCache.request.put(AvalonRequest{command: Write, addr: truncate(s.addr),
data: halfSub(data, s.line, s.data)});
tagged WbSW .s: $display("WB error: wbSW shouldn't cause a pending load");
endcase
dataFIFO.deq;
pendingLoad.deq;
endrule
rule wbFromExec(!dataFIFO.notEmpty && !clearCache);
let wbOp = execToWB.first;
trace($format("[wbFromExec] ")+fshow(wbOp));
function Action reqLoad(Bit#(24) addr) = action
cache.dataCache.request.put(AvalonRequest{command:Read, addr:truncate(addr), data:?});
pendingLoad.enq(wbOp);
endaction;
case (wbOp) matches
tagged WbREG .s: rf.wr(s.r, s.data);
tagged WbLB .s: reqLoad(s.addr);
tagged WbLBU .s: reqLoad(s.addr);
tagged WbLH .s: reqLoad(s.addr);
tagged WbLHU .s: reqLoad(s.addr);
tagged WbLW .s: reqLoad(s.addr);
tagged WbSB .s: reqLoad(s.addr);
tagged WbSH .s: reqLoad(s.addr);
tagged WbSW .s:
cache.dataCache.request.put(AvalonRequest{command:Write, addr:truncate(s.addr), data:s.data});
endcase
execToWB.deq;
endrule
return masterAdapter.masterWires;
endmodule