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basys3 flterm unable to open kernel image, no such file or dir #638

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nickoe opened this issue Feb 1, 2021 · 0 comments
Open

basys3 flterm unable to open kernel image, no such file or dir #638

nickoe opened this issue Feb 1, 2021 · 0 comments

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@nickoe
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nickoe commented Feb 1, 2021

I was asked to report this bug, so here it is:

I am trying to run on the basys3. I am testing litex-buildenv 690901d

[FLTERM] Received firmware download request from the device.
[FLTERM] Unable to open kernel image (request ignored).: No such file or directory
Timeout

Complete log:

(LX P=basys3 C=vexriscv) [nickoe@x280-arch litex-buildenv]$ make firmware-load
mkdir -p build/basys3_base_vexriscv
time python -u ./make.py --platform=basys3 --target=base --cpu-type=vexriscv --iprange=192.168.100     --no-compile-gateware \
	2>&1 | tee -a /home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/output.20210201-210058.log; (exit ${PIPESTATUS[0]})
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-02-01 21:00:58)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35t-cpg236-1.
INFO:SoC:System clock: 100.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00008000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00008000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCCSRHandler:info CSR allocated at Location 6.
INFO:SoCCSRHandler:cas CSR allocated at Location 7.
INFO:SoCCSRHandler:spiflash CSR allocated at Location 8.
INFO:SoCBusHandler:spiflash Region added at Origin: 0x20000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False.
INFO:SoCRegion:Region size rounded internally from 0x00dd7f00 to 0x01000000.
INFO:SoCBusHandler:user_flash Region added at Origin: 0x20228000, Size: 0x00dd7f00, Mode: RW, Cached: True Linker: True.
INFO:SoCBusHandler:spiflash added as Bus Slave.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00008000, Mode: RW, Cached: True Linker: False
spiflash            : Origin: 0x20000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False
user_flash          : Origin: 0x20228000, Size: 0x00dd7f00, Mode: RW, Cached: True Linker: True
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- spiflash
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (9)
- ctrl           : 0
- cpu            : 1
- identifier_mem : 2
- uart_phy       : 3
- uart           : 4
- timer0         : 5
- info           : 6
- cas            : 7
- spiflash       : 8
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libcompiler_rt'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libcompiler_rt'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       i2c.o
 CC       memtest.o
 AR       libbase.a
 AR       libbase-nofloat.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libbase'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitedram'
 CC       sdram.o
 AR       liblitedram.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitedram'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libliteeth'
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/libliteeth'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitespi'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/liblitesdcard'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/bios'
 CC       isr.o
 CC       boot.o
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/boot.c: In function 'flashboot':
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/boot.c:480:11: warning: unused variable 'result' [-Wunused-variable]
  480 |  uint32_t result;
      |           ^~~~~~
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/cmds/cmd_spiflash.c: In function 'fw':
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/cmds/cmd_spiflash.c:54:3: warning: implicit declaration of function 'write_to_flash' [-Wimplicit-function-declaration]
   54 |   write_to_flash(addr + i * 4, (unsigned char *)&value, 4);
      |   ^~~~~~~~~~~~~~
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/cmds/cmd_spiflash.c: In function 'fe':
/home/nickoe/litex_test/litex-buildenv/third_party/litex/litex/soc/software/bios/cmds/cmd_spiflash.c:69:2: warning: implicit declaration of function 'erase_flash' [-Wimplicit-function-declaration]
   69 |  erase_flash();
      |  ^~~~~~~~~~~
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python -m litex.soc.software.mkmscimg bios.bin --little
python -m litex.soc.software.memusage bios.elf /home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 21.96KiB 	(68.63%)
RAM usage: 1.64KiB 	(5.13%)

make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/bios'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/uip'
 CC       clock-arch.o
 CC       liteethmac-drv.o
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:35:25: warning: 'txbuffer1' defined but not used [-Wunused-variable]
   35 | static ethernet_buffer *txbuffer1;
      |                         ^~~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:34:25: warning: 'txbuffer0' defined but not used [-Wunused-variable]
   34 | static ethernet_buffer *txbuffer0;
      |                         ^~~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:33:25: warning: 'txbuffer' defined but not used [-Wunused-variable]
   33 | static ethernet_buffer *txbuffer;
      |                         ^~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:32:21: warning: 'txlen' defined but not used [-Wunused-variable]
   32 | static unsigned int txlen;
      |                     ^~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:31:21: warning: 'txslot' defined but not used [-Wunused-variable]
   31 | static unsigned int txslot;
      |                     ^~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:30:25: warning: 'rxbuffer1' defined but not used [-Wunused-variable]
   30 | static ethernet_buffer *rxbuffer1;
      |                         ^~~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:29:25: warning: 'rxbuffer0' defined but not used [-Wunused-variable]
   29 | static ethernet_buffer *rxbuffer0;
      |                         ^~~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:28:25: warning: 'rxbuffer' defined but not used [-Wunused-variable]
   28 | static ethernet_buffer *rxbuffer;
      |                         ^~~~~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:27:21: warning: 'rxlen' defined but not used [-Wunused-variable]
   27 | static unsigned int rxlen;
      |                     ^~~~~
/home/nickoe/litex_test/litex-buildenv/firmware/uip/liteethmac-drv.c:26:21: warning: 'rxslot' defined but not used [-Wunused-variable]
   26 | static unsigned int rxslot;
      |                     ^~~~~~
 AR       libuip.a
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/uip'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/stub'
 CC       main.o
 CC       isr.o
 LD       firmware.elf
chmod -x firmware.elf
 OBJCOPY  firmware.bin
chmod -x firmware.bin
python -m litex.soc.software.mkmscimg -f --little firmware.bin -o firmware.fbi
make[1]: Leaving directory '/home/nickoe/litex_test/litex-buildenv/build/basys3_base_vexriscv/software/stub'

real	0m2,080s
user	0m1,754s
sys	0m0,336s
flterm --port=/dev/ttyUSB1 --kernel=build/basys3_base_vexriscv/software/firmware/firmware.bin --speed=115200
[FLTERM] v2.4-29-g47d3b15 Starting...

litex> 
litex> help

LiteX BIOS, available commands:

crc              - Compute CRC32 of a part of the address space
help             - Print this help

reboot           - Reboot the system
ident            - Identifier of the system

flush_cpu_dcache - Flush CPU data cache

memspeed         - Run a memory speed test
memtest          - Run a memory test
mc               - Copy address space
mw               - Write address space
mr               - Read address space
serialboot       - Boot from Serial (SFL)
flashboot        - Boot from Flash

fe               - Erase whole flash
fw               - Write to flash


litex> 
litex> serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[FLTERM] Received firmware download request from the device.
[FLTERM] Unable to open kernel image (request ignored).: No such file or directory
Timeout

litex>
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@nickoe